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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2007-02-05 11:45:38 -0500
committerJeff Garzik <jeff@garzik.org>2007-02-09 17:39:39 -0500
commit409ba47c297fd13849909adea63f183f55d52418 (patch)
tree033a0705142e06acd4c6f3bca703cf304d61f726 /drivers/ata
parent49554c19569c91d0943b67ca731c9abfc857883f (diff)
(2.6.20) pata_oldpiix: fix PIO2 underclocking
Fix the PIO mode 2 using mode 0 timings -- this driver should enable the fast timing bank starting with PIO2, just like the ata_piix driver does. Also, fix/rephrase some comments while at it. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata')
-rw-r--r--drivers/ata/pata_oldpiix.c18
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/ata/pata_oldpiix.c b/drivers/ata/pata_oldpiix.c
index b76d2b466614..45215aa05e72 100644
--- a/drivers/ata/pata_oldpiix.c
+++ b/drivers/ata/pata_oldpiix.c
@@ -25,7 +25,7 @@
25#include <linux/ata.h> 25#include <linux/ata.h>
26 26
27#define DRV_NAME "pata_oldpiix" 27#define DRV_NAME "pata_oldpiix"
28#define DRV_VERSION "0.5.2" 28#define DRV_VERSION "0.5.3"
29 29
30/** 30/**
31 * oldpiix_pre_reset - probe begin 31 * oldpiix_pre_reset - probe begin
@@ -94,19 +94,21 @@ static void oldpiix_set_piomode (struct ata_port *ap, struct ata_device *adev)
94 { 2, 1 }, 94 { 2, 1 },
95 { 2, 3 }, }; 95 { 2, 3 }, };
96 96
97 if (pio > 2) 97 if (pio > 1)
98 control |= 1; /* TIME1 enable */ 98 control |= 1; /* TIME */
99 if (ata_pio_need_iordy(adev)) 99 if (ata_pio_need_iordy(adev))
100 control |= 2; /* IE IORDY */ 100 control |= 2; /* IE */
101 101
102 /* Intel specifies that the PPE functionality is for disk only */ 102 /* Intel specifies that the prefetch/posting is for disk only */
103 if (adev->class == ATA_DEV_ATA) 103 if (adev->class == ATA_DEV_ATA)
104 control |= 4; /* PPE enable */ 104 control |= 4; /* PPE */
105 105
106 pci_read_config_word(dev, idetm_port, &idetm_data); 106 pci_read_config_word(dev, idetm_port, &idetm_data);
107 107
108 /* Enable PPE, IE and TIME as appropriate. Clear the other 108 /*
109 drive timing bits */ 109 * Set PPE, IE and TIME as appropriate.
110 * Clear the other drive's timing bits.
111 */
110 if (adev->devno == 0) { 112 if (adev->devno == 0) {
111 idetm_data &= 0xCCE0; 113 idetm_data &= 0xCCE0;
112 idetm_data |= control; 114 idetm_data |= control;