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authorPaul Bolle <pebolle@tiscali.nl>2014-05-21 15:35:37 -0400
committerTejun Heo <tj@kernel.org>2014-05-21 15:36:22 -0400
commitd0f5aa9cf6a479884cda95018363ba9ed31d9cbd (patch)
tree2817c162cbc43805876ffb919926676be43443bf /drivers/ata
parenta1a205df6ee224f62c6d21cedebcb723db17fe0d (diff)
sata_fsl: remove check for CONFIG_MPC8315_DS
A check for CONFIG_MPC8315_DS was added in v2.6.24. But the related Kconfig symbol was never added to the tree. So the code behind this check has effectively been dead for over six years. Remove it. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'drivers/ata')
-rw-r--r--drivers/ata/sata_fsl.c14
1 files changed, 0 insertions, 14 deletions
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index e8f150e45446..616a6d2ac20c 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -774,20 +774,6 @@ static int sata_fsl_port_start(struct ata_port *ap)
774 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 774 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
775 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 775 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
776 776
777#ifdef CONFIG_MPC8315_DS
778 /*
779 * Workaround for 8315DS board 3gbps link-up issue,
780 * currently limit SATA port to GEN1 speed
781 */
782 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
783 temp &= ~(0xF << 4);
784 temp |= (0x1 << 4);
785 sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp);
786
787 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
788 dev_warn(dev, "scr_control, speed limited to %x\n", temp);
789#endif
790
791 return 0; 777 return 0;
792} 778}
793 779