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authorMark Lord <liml@rtr.ca>2008-05-02 02:07:51 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-05-06 11:37:38 -0400
commit8e7decdb8b132ee970a2636931b7653dec6af472 (patch)
treecb636da92b98089aba3f87c0f0b975df72590375 /drivers/ata
parent07ab85de4d960b6f39395e51c1853485ad120de5 (diff)
sata_mv more cosmetic changes
More cosmetic changes; no code changes. -- try and improve consistency of naming. -- add missing _OFS to tails of register offset definitions. -- rename mv_setup_ifctl() to mv_setup_ifcfg(), since that's what it really does. -- remove/move some dead comments Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/ata')
-rw-r--r--drivers/ata/sata_mv.c122
1 files changed, 63 insertions, 59 deletions
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 842b1a15b78c..4eabb737a48d 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -91,9 +91,9 @@ enum {
91 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 91 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
92 92
93 MV_SATAHC0_REG_BASE = 0x20000, 93 MV_SATAHC0_REG_BASE = 0x20000,
94 MV_FLASH_CTL = 0x1046c, 94 MV_FLASH_CTL_OFS = 0x1046c,
95 MV_GPIO_PORT_CTL = 0x104f0, 95 MV_GPIO_PORT_CTL_OFS = 0x104f0,
96 MV_RESET_CFG = 0x180d8, 96 MV_RESET_CFG_OFS = 0x180d8,
97 97
98 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 98 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 99 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
@@ -147,18 +147,21 @@ enum {
147 /* PCI interface registers */ 147 /* PCI interface registers */
148 148
149 PCI_COMMAND_OFS = 0xc00, 149 PCI_COMMAND_OFS = 0xc00,
150 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
150 151
151 PCI_MAIN_CMD_STS_OFS = 0xd30, 152 PCI_MAIN_CMD_STS_OFS = 0xd30,
152 STOP_PCI_MASTER = (1 << 2), 153 STOP_PCI_MASTER = (1 << 2),
153 PCI_MASTER_EMPTY = (1 << 3), 154 PCI_MASTER_EMPTY = (1 << 3),
154 GLOB_SFT_RST = (1 << 4), 155 GLOB_SFT_RST = (1 << 4),
155 156
156 MV_PCI_MODE = 0xd00, 157 MV_PCI_MODE_OFS = 0xd00,
158 MV_PCI_MODE_MASK = 0x30,
159
157 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 160 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
158 MV_PCI_DISC_TIMER = 0xd04, 161 MV_PCI_DISC_TIMER = 0xd04,
159 MV_PCI_MSI_TRIGGER = 0xc38, 162 MV_PCI_MSI_TRIGGER = 0xc38,
160 MV_PCI_SERR_MASK = 0xc28, 163 MV_PCI_SERR_MASK = 0xc28,
161 MV_PCI_XBAR_TMOUT = 0x1d04, 164 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
162 MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 165 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
163 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 166 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
164 MV_PCI_ERR_ATTRIBUTE = 0x1d48, 167 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
@@ -225,16 +228,18 @@ enum {
225 PHY_MODE4 = 0x314, 228 PHY_MODE4 = 0x314,
226 PHY_MODE2 = 0x330, 229 PHY_MODE2 = 0x330,
227 SATA_IFCTL_OFS = 0x344, 230 SATA_IFCTL_OFS = 0x344,
231 SATA_TESTCTL_OFS = 0x348,
228 SATA_IFSTAT_OFS = 0x34c, 232 SATA_IFSTAT_OFS = 0x34c,
229 VENDOR_UNIQUE_FIS_OFS = 0x35c, 233 VENDOR_UNIQUE_FIS_OFS = 0x35c,
230 234
231 FIS_CFG_OFS = 0x360, 235 FISCFG_OFS = 0x360,
232 FIS_CFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 236 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
237 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
233 238
234 MV5_PHY_MODE = 0x74, 239 MV5_PHY_MODE = 0x74,
235 MV5_LT_MODE = 0x30, 240 MV5_LTMODE_OFS = 0x30,
236 MV5_PHY_CTL = 0x0C, 241 MV5_PHY_CTL_OFS = 0x0C,
237 SATA_INTERFACE_CFG = 0x050, 242 SATA_INTERFACE_CFG_OFS = 0x050,
238 243
239 MV_M2_PREAMP_MASK = 0x7e0, 244 MV_M2_PREAMP_MASK = 0x7e0,
240 245
@@ -332,10 +337,16 @@ enum {
332 EDMA_CMD_OFS = 0x28, /* EDMA command register */ 337 EDMA_CMD_OFS = 0x28, /* EDMA command register */
333 EDMA_EN = (1 << 0), /* enable EDMA */ 338 EDMA_EN = (1 << 0), /* enable EDMA */
334 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 339 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
335 ATA_RST = (1 << 2), /* reset trans/link/phy */ 340 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
341
342 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
343 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
344 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
336 345
337 EDMA_IORDY_TMOUT = 0x34, 346 EDMA_IORDY_TMOUT_OFS = 0x34,
338 EDMA_ARB_CFG = 0x38, 347 EDMA_ARB_CFG_OFS = 0x38,
348
349 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
339 350
340 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */ 351 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
341 352
@@ -359,6 +370,7 @@ enum {
359#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 370#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
360#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 371#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
361#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 372#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
373#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
362#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) 374#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
363 375
364#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 376#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
@@ -1059,22 +1071,22 @@ static void mv6_dev_config(struct ata_device *adev)
1059 1071
1060static void mv_config_fbs(void __iomem *port_mmio, int enable_fbs) 1072static void mv_config_fbs(void __iomem *port_mmio, int enable_fbs)
1061{ 1073{
1062 u32 old_fcfg, new_fcfg, old_ltmode, new_ltmode; 1074 u32 old_fiscfg, new_fiscfg, old_ltmode, new_ltmode;
1063 /* 1075 /*
1064 * Various bit settings required for operation 1076 * Various bit settings required for operation
1065 * in FIS-based switching (fbs) mode on GenIIe: 1077 * in FIS-based switching (fbs) mode on GenIIe:
1066 */ 1078 */
1067 old_fcfg = readl(port_mmio + FIS_CFG_OFS); 1079 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1068 old_ltmode = readl(port_mmio + LTMODE_OFS); 1080 old_ltmode = readl(port_mmio + LTMODE_OFS);
1069 if (enable_fbs) { 1081 if (enable_fbs) {
1070 new_fcfg = old_fcfg | FIS_CFG_SINGLE_SYNC; 1082 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1071 new_ltmode = old_ltmode | LTMODE_BIT8; 1083 new_ltmode = old_ltmode | LTMODE_BIT8;
1072 } else { /* disable fbs */ 1084 } else { /* disable fbs */
1073 new_fcfg = old_fcfg & ~FIS_CFG_SINGLE_SYNC; 1085 new_fiscfg = old_fiscfg & ~FISCFG_SINGLE_SYNC;
1074 new_ltmode = old_ltmode & ~LTMODE_BIT8; 1086 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1075 } 1087 }
1076 if (new_fcfg != old_fcfg) 1088 if (new_fiscfg != old_fiscfg)
1077 writelfl(new_fcfg, port_mmio + FIS_CFG_OFS); 1089 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
1078 if (new_ltmode != old_ltmode) 1090 if (new_ltmode != old_ltmode)
1079 writelfl(new_ltmode, port_mmio + LTMODE_OFS); 1091 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
1080} 1092}
@@ -1894,7 +1906,7 @@ static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
1894 1906
1895static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 1907static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1896{ 1908{
1897 writel(0x0fcfffff, mmio + MV_FLASH_CTL); 1909 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
1898} 1910}
1899 1911
1900static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 1912static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
@@ -1913,7 +1925,7 @@ static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1913{ 1925{
1914 u32 tmp; 1926 u32 tmp;
1915 1927
1916 writel(0, mmio + MV_GPIO_PORT_CTL); 1928 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
1917 1929
1918 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 1930 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1919 1931
@@ -1931,14 +1943,14 @@ static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1931 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 1943 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1932 1944
1933 if (fix_apm_sq) { 1945 if (fix_apm_sq) {
1934 tmp = readl(phy_mmio + MV5_LT_MODE); 1946 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
1935 tmp |= (1 << 19); 1947 tmp |= (1 << 19);
1936 writel(tmp, phy_mmio + MV5_LT_MODE); 1948 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
1937 1949
1938 tmp = readl(phy_mmio + MV5_PHY_CTL); 1950 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
1939 tmp &= ~0x3; 1951 tmp &= ~0x3;
1940 tmp |= 0x1; 1952 tmp |= 0x1;
1941 writel(tmp, phy_mmio + MV5_PHY_CTL); 1953 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
1942 } 1954 }
1943 1955
1944 tmp = readl(phy_mmio + MV5_PHY_MODE); 1956 tmp = readl(phy_mmio + MV5_PHY_MODE);
@@ -1956,11 +1968,6 @@ static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1956{ 1968{
1957 void __iomem *port_mmio = mv_port_base(mmio, port); 1969 void __iomem *port_mmio = mv_port_base(mmio, port);
1958 1970
1959 /*
1960 * The datasheet warns against setting ATA_RST when EDMA is active
1961 * (but doesn't say what the problem might be). So we first try
1962 * to disable the EDMA engine before doing the ATA_RST operation.
1963 */
1964 mv_reset_channel(hpriv, mmio, port); 1971 mv_reset_channel(hpriv, mmio, port);
1965 1972
1966 ZERO(0x028); /* command */ 1973 ZERO(0x028); /* command */
@@ -1975,7 +1982,7 @@ static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1975 ZERO(0x024); /* respq outp */ 1982 ZERO(0x024); /* respq outp */
1976 ZERO(0x020); /* respq inp */ 1983 ZERO(0x020); /* respq inp */
1977 ZERO(0x02c); /* test control */ 1984 ZERO(0x02c); /* test control */
1978 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 1985 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
1979} 1986}
1980#undef ZERO 1987#undef ZERO
1981 1988
@@ -2021,13 +2028,13 @@ static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
2021 struct mv_host_priv *hpriv = host->private_data; 2028 struct mv_host_priv *hpriv = host->private_data;
2022 u32 tmp; 2029 u32 tmp;
2023 2030
2024 tmp = readl(mmio + MV_PCI_MODE); 2031 tmp = readl(mmio + MV_PCI_MODE_OFS);
2025 tmp &= 0xff00ffff; 2032 tmp &= 0xff00ffff;
2026 writel(tmp, mmio + MV_PCI_MODE); 2033 writel(tmp, mmio + MV_PCI_MODE_OFS);
2027 2034
2028 ZERO(MV_PCI_DISC_TIMER); 2035 ZERO(MV_PCI_DISC_TIMER);
2029 ZERO(MV_PCI_MSI_TRIGGER); 2036 ZERO(MV_PCI_MSI_TRIGGER);
2030 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 2037 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
2031 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS); 2038 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
2032 ZERO(MV_PCI_SERR_MASK); 2039 ZERO(MV_PCI_SERR_MASK);
2033 ZERO(hpriv->irq_cause_ofs); 2040 ZERO(hpriv->irq_cause_ofs);
@@ -2045,10 +2052,10 @@ static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2045 2052
2046 mv5_reset_flash(hpriv, mmio); 2053 mv5_reset_flash(hpriv, mmio);
2047 2054
2048 tmp = readl(mmio + MV_GPIO_PORT_CTL); 2055 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
2049 tmp &= 0x3; 2056 tmp &= 0x3;
2050 tmp |= (1 << 5) | (1 << 6); 2057 tmp |= (1 << 5) | (1 << 6);
2051 writel(tmp, mmio + MV_GPIO_PORT_CTL); 2058 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
2052} 2059}
2053 2060
2054/** 2061/**
@@ -2121,7 +2128,7 @@ static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
2121 void __iomem *port_mmio; 2128 void __iomem *port_mmio;
2122 u32 tmp; 2129 u32 tmp;
2123 2130
2124 tmp = readl(mmio + MV_RESET_CFG); 2131 tmp = readl(mmio + MV_RESET_CFG_OFS);
2125 if ((tmp & (1 << 0)) == 0) { 2132 if ((tmp & (1 << 0)) == 0) {
2126 hpriv->signal[idx].amps = 0x7 << 8; 2133 hpriv->signal[idx].amps = 0x7 << 8;
2127 hpriv->signal[idx].pre = 0x1 << 5; 2134 hpriv->signal[idx].pre = 0x1 << 5;
@@ -2137,7 +2144,7 @@ static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
2137 2144
2138static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2145static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2139{ 2146{
2140 writel(0x00000060, mmio + MV_GPIO_PORT_CTL); 2147 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
2141} 2148}
2142 2149
2143static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 2150static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
@@ -2235,11 +2242,6 @@ static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2235{ 2242{
2236 void __iomem *port_mmio = mv_port_base(mmio, port); 2243 void __iomem *port_mmio = mv_port_base(mmio, port);
2237 2244
2238 /*
2239 * The datasheet warns against setting ATA_RST when EDMA is active
2240 * (but doesn't say what the problem might be). So we first try
2241 * to disable the EDMA engine before doing the ATA_RST operation.
2242 */
2243 mv_reset_channel(hpriv, mmio, port); 2245 mv_reset_channel(hpriv, mmio, port);
2244 2246
2245 ZERO(0x028); /* command */ 2247 ZERO(0x028); /* command */
@@ -2254,7 +2256,7 @@ static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2254 ZERO(0x024); /* respq outp */ 2256 ZERO(0x024); /* respq outp */
2255 ZERO(0x020); /* respq inp */ 2257 ZERO(0x020); /* respq inp */
2256 ZERO(0x02c); /* test control */ 2258 ZERO(0x02c); /* test control */
2257 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 2259 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2258} 2260}
2259 2261
2260#undef ZERO 2262#undef ZERO
@@ -2297,38 +2299,39 @@ static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2297 return; 2299 return;
2298} 2300}
2299 2301
2300static void mv_setup_ifctl(void __iomem *port_mmio, int want_gen2i) 2302static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
2301{ 2303{
2302 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG); 2304 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
2303 2305
2304 ifctl = (ifctl & 0xf7f) | 0x9b1000; /* from chip spec */ 2306 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
2305 if (want_gen2i) 2307 if (want_gen2i)
2306 ifctl |= (1 << 7); /* enable gen2i speed */ 2308 ifcfg |= (1 << 7); /* enable gen2i speed */
2307 writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG); 2309 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
2308} 2310}
2309 2311
2310/*
2311 * Caller must ensure that EDMA is not active,
2312 * by first doing mv_stop_edma() where needed.
2313 */
2314static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 2312static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
2315 unsigned int port_no) 2313 unsigned int port_no)
2316{ 2314{
2317 void __iomem *port_mmio = mv_port_base(mmio, port_no); 2315 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2318 2316
2317 /*
2318 * The datasheet warns against setting EDMA_RESET when EDMA is active
2319 * (but doesn't say what the problem might be). So we first try
2320 * to disable the EDMA engine before doing the EDMA_RESET operation.
2321 */
2319 mv_stop_edma_engine(port_mmio); 2322 mv_stop_edma_engine(port_mmio);
2320 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); 2323 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2321 2324
2322 if (!IS_GEN_I(hpriv)) { 2325 if (!IS_GEN_I(hpriv)) {
2323 /* Enable 3.0gb/s link speed */ 2326 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2324 mv_setup_ifctl(port_mmio, 1); 2327 mv_setup_ifcfg(port_mmio, 1);
2325 } 2328 }
2326 /* 2329 /*
2327 * Strobing ATA_RST here causes a hard reset of the SATA transport, 2330 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
2328 * link, and physical layers. It resets all SATA interface registers 2331 * link, and physical layers. It resets all SATA interface registers
2329 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 2332 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2330 */ 2333 */
2331 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); 2334 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2332 udelay(25); /* allow reset propagation */ 2335 udelay(25); /* allow reset propagation */
2333 writelfl(0, port_mmio + EDMA_CMD_OFS); 2336 writelfl(0, port_mmio + EDMA_CMD_OFS);
2334 2337
@@ -2392,7 +2395,7 @@ static int mv_hardreset(struct ata_link *link, unsigned int *class,
2392 sata_scr_read(link, SCR_STATUS, &sstatus); 2395 sata_scr_read(link, SCR_STATUS, &sstatus);
2393 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 2396 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2394 /* Force 1.5gb/s link speed and try again */ 2397 /* Force 1.5gb/s link speed and try again */
2395 mv_setup_ifctl(mv_ap_base(ap), 0); 2398 mv_setup_ifcfg(mv_ap_base(ap), 0);
2396 if (time_after(jiffies + HZ, deadline)) 2399 if (time_after(jiffies + HZ, deadline))
2397 extra = HZ; /* only extend it once, max */ 2400 extra = HZ; /* only extend it once, max */
2398 } 2401 }
@@ -2590,6 +2593,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2590 " and avoid the final two gigabytes on" 2593 " and avoid the final two gigabytes on"
2591 " all RocketRAID BIOS initialized drives.\n"); 2594 " all RocketRAID BIOS initialized drives.\n");
2592 } 2595 }
2596 /* drop through */
2593 case chip_6042: 2597 case chip_6042:
2594 hpriv->ops = &mv6xxx_ops; 2598 hpriv->ops = &mv6xxx_ops;
2595 hp_flags |= MV_HP_GEN_IIE; 2599 hp_flags |= MV_HP_GEN_IIE;