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authorTejun Heo <htejun@gmail.com>2007-02-01 01:06:36 -0500
committerJeff Garzik <jeff@garzik.org>2007-02-09 17:39:38 -0500
commit0d5ff566779f894ca9937231a181eb31e4adff0e (patch)
treed1c7495c932581c1d41aa7f0fdb303348da49106 /drivers/ata/sata_vsc.c
parent1a68ff13c8a9b517de3fd4187dc525412a6eba1b (diff)
libata: convert to iomap
Convert libata core layer and LLDs to use iomap. * managed iomap is used. Pointer to pcim_iomap_table() is cached at host->iomap and used through out LLDs. This basically replaces host->mmio_base. * if possible, pcim_iomap_regions() is used Most iomap operation conversions are taken from Jeff Garzik <jgarzik@pobox.com>'s iomap branch. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/sata_vsc.c')
-rw-r--r--drivers/ata/sata_vsc.c80
1 files changed, 40 insertions, 40 deletions
diff --git a/drivers/ata/sata_vsc.c b/drivers/ata/sata_vsc.c
index af77f71bdaa5..7596e9ace50b 100644
--- a/drivers/ata/sata_vsc.c
+++ b/drivers/ata/sata_vsc.c
@@ -50,6 +50,8 @@
50#define DRV_VERSION "2.0" 50#define DRV_VERSION "2.0"
51 51
52enum { 52enum {
53 VSC_MMIO_BAR = 0,
54
53 /* Interrupt register offsets (from chip base address) */ 55 /* Interrupt register offsets (from chip base address) */
54 VSC_SATA_INT_STAT_OFFSET = 0x00, 56 VSC_SATA_INT_STAT_OFFSET = 0x00,
55 VSC_SATA_INT_MASK_OFFSET = 0x04, 57 VSC_SATA_INT_MASK_OFFSET = 0x04,
@@ -104,7 +106,7 @@ static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
104{ 106{
105 if (sc_reg > SCR_CONTROL) 107 if (sc_reg > SCR_CONTROL)
106 return 0xffffffffU; 108 return 0xffffffffU;
107 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); 109 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
108} 110}
109 111
110 112
@@ -113,7 +115,7 @@ static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
113{ 115{
114 if (sc_reg > SCR_CONTROL) 116 if (sc_reg > SCR_CONTROL)
115 return; 117 return;
116 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); 118 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
117} 119}
118 120
119 121
@@ -122,7 +124,7 @@ static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
122 void __iomem *mask_addr; 124 void __iomem *mask_addr;
123 u8 mask; 125 u8 mask;
124 126
125 mask_addr = ap->host->mmio_base + 127 mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
126 VSC_SATA_INT_MASK_OFFSET + ap->port_no; 128 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
127 mask = readb(mask_addr); 129 mask = readb(mask_addr);
128 if (ctl & ATA_NIEN) 130 if (ctl & ATA_NIEN)
@@ -149,25 +151,25 @@ static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
149 } 151 }
150 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 152 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
151 writew(tf->feature | (((u16)tf->hob_feature) << 8), 153 writew(tf->feature | (((u16)tf->hob_feature) << 8),
152 (void __iomem *) ioaddr->feature_addr); 154 ioaddr->feature_addr);
153 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), 155 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
154 (void __iomem *) ioaddr->nsect_addr); 156 ioaddr->nsect_addr);
155 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), 157 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
156 (void __iomem *) ioaddr->lbal_addr); 158 ioaddr->lbal_addr);
157 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), 159 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
158 (void __iomem *) ioaddr->lbam_addr); 160 ioaddr->lbam_addr);
159 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), 161 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
160 (void __iomem *) ioaddr->lbah_addr); 162 ioaddr->lbah_addr);
161 } else if (is_addr) { 163 } else if (is_addr) {
162 writew(tf->feature, (void __iomem *) ioaddr->feature_addr); 164 writew(tf->feature, ioaddr->feature_addr);
163 writew(tf->nsect, (void __iomem *) ioaddr->nsect_addr); 165 writew(tf->nsect, ioaddr->nsect_addr);
164 writew(tf->lbal, (void __iomem *) ioaddr->lbal_addr); 166 writew(tf->lbal, ioaddr->lbal_addr);
165 writew(tf->lbam, (void __iomem *) ioaddr->lbam_addr); 167 writew(tf->lbam, ioaddr->lbam_addr);
166 writew(tf->lbah, (void __iomem *) ioaddr->lbah_addr); 168 writew(tf->lbah, ioaddr->lbah_addr);
167 } 169 }
168 170
169 if (tf->flags & ATA_TFLAG_DEVICE) 171 if (tf->flags & ATA_TFLAG_DEVICE)
170 writeb(tf->device, (void __iomem *) ioaddr->device_addr); 172 writeb(tf->device, ioaddr->device_addr);
171 173
172 ata_wait_idle(ap); 174 ata_wait_idle(ap);
173} 175}
@@ -179,12 +181,12 @@ static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
179 u16 nsect, lbal, lbam, lbah, feature; 181 u16 nsect, lbal, lbam, lbah, feature;
180 182
181 tf->command = ata_check_status(ap); 183 tf->command = ata_check_status(ap);
182 tf->device = readw((void __iomem *) ioaddr->device_addr); 184 tf->device = readw(ioaddr->device_addr);
183 feature = readw((void __iomem *) ioaddr->error_addr); 185 feature = readw(ioaddr->error_addr);
184 nsect = readw((void __iomem *) ioaddr->nsect_addr); 186 nsect = readw(ioaddr->nsect_addr);
185 lbal = readw((void __iomem *) ioaddr->lbal_addr); 187 lbal = readw(ioaddr->lbal_addr);
186 lbam = readw((void __iomem *) ioaddr->lbam_addr); 188 lbam = readw(ioaddr->lbam_addr);
187 lbah = readw((void __iomem *) ioaddr->lbah_addr); 189 lbah = readw(ioaddr->lbah_addr);
188 190
189 tf->feature = feature; 191 tf->feature = feature;
190 tf->nsect = nsect; 192 tf->nsect = nsect;
@@ -216,7 +218,8 @@ static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
216 218
217 spin_lock(&host->lock); 219 spin_lock(&host->lock);
218 220
219 int_status = readl(host->mmio_base + VSC_SATA_INT_STAT_OFFSET); 221 int_status = readl(host->iomap[VSC_MMIO_BAR] +
222 VSC_SATA_INT_STAT_OFFSET);
220 223
221 for (i = 0; i < host->n_ports; i++) { 224 for (i = 0; i < host->n_ports; i++) {
222 if (int_status & ((u32) 0xFF << (8 * i))) { 225 if (int_status & ((u32) 0xFF << (8 * i))) {
@@ -300,7 +303,7 @@ static const struct ata_port_operations vsc_sata_ops = {
300 .bmdma_status = ata_bmdma_status, 303 .bmdma_status = ata_bmdma_status,
301 .qc_prep = ata_qc_prep, 304 .qc_prep = ata_qc_prep,
302 .qc_issue = ata_qc_issue_prot, 305 .qc_issue = ata_qc_issue_prot,
303 .data_xfer = ata_mmio_data_xfer, 306 .data_xfer = ata_data_xfer,
304 .freeze = ata_bmdma_freeze, 307 .freeze = ata_bmdma_freeze,
305 .thaw = ata_bmdma_thaw, 308 .thaw = ata_bmdma_thaw,
306 .error_handler = ata_bmdma_error_handler, 309 .error_handler = ata_bmdma_error_handler,
@@ -312,7 +315,8 @@ static const struct ata_port_operations vsc_sata_ops = {
312 .port_start = ata_port_start, 315 .port_start = ata_port_start,
313}; 316};
314 317
315static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base) 318static void __devinit vsc_sata_setup_port(struct ata_ioports *port,
319 void __iomem *base)
316{ 320{
317 port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET; 321 port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
318 port->data_addr = base + VSC_SATA_TF_DATA_OFFSET; 322 port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
@@ -329,16 +333,15 @@ static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned lon
329 port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET; 333 port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
330 port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET; 334 port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
331 port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET; 335 port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
332 writel(0, (void __iomem *) base + VSC_SATA_UP_DESCRIPTOR_OFFSET); 336 writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
333 writel(0, (void __iomem *) base + VSC_SATA_UP_DATA_BUFFER_OFFSET); 337 writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
334} 338}
335 339
336 340
337static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 341static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
338{ 342{
339 static int printed_version; 343 static int printed_version;
340 struct ata_probe_ent *probe_ent = NULL; 344 struct ata_probe_ent *probe_ent;
341 unsigned long base;
342 void __iomem *mmio_base; 345 void __iomem *mmio_base;
343 int rc; 346 int rc;
344 347
@@ -355,11 +358,11 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d
355 if (pci_resource_len(pdev, 0) == 0) 358 if (pci_resource_len(pdev, 0) == 0)
356 return -ENODEV; 359 return -ENODEV;
357 360
358 rc = pci_request_regions(pdev, DRV_NAME); 361 rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
359 if (rc) { 362 if (rc == -EBUSY)
360 pcim_pin_device(pdev); 363 pcim_pin_device(pdev);
364 if (rc)
361 return rc; 365 return rc;
362 }
363 366
364 /* 367 /*
365 * Use 32 bit DMA mask, because 64 bit address support is poor. 368 * Use 32 bit DMA mask, because 64 bit address support is poor.
@@ -377,11 +380,6 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d
377 probe_ent->dev = pci_dev_to_dev(pdev); 380 probe_ent->dev = pci_dev_to_dev(pdev);
378 INIT_LIST_HEAD(&probe_ent->node); 381 INIT_LIST_HEAD(&probe_ent->node);
379 382
380 mmio_base = pcim_iomap(pdev, 0, 0);
381 if (mmio_base == NULL)
382 return -ENOMEM;
383 base = (unsigned long) mmio_base;
384
385 /* 383 /*
386 * Due to a bug in the chip, the default cache line size can't be used 384 * Due to a bug in the chip, the default cache line size can't be used
387 */ 385 */
@@ -398,7 +396,7 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d
398 probe_ent->port_ops = &vsc_sata_ops; 396 probe_ent->port_ops = &vsc_sata_ops;
399 probe_ent->n_ports = 4; 397 probe_ent->n_ports = 4;
400 probe_ent->irq = pdev->irq; 398 probe_ent->irq = pdev->irq;
401 probe_ent->mmio_base = mmio_base; 399 probe_ent->iomap = pcim_iomap_table(pdev);
402 400
403 /* We don't care much about the PIO/UDMA masks, but the core won't like us 401 /* We don't care much about the PIO/UDMA masks, but the core won't like us
404 * if we don't fill these 402 * if we don't fill these
@@ -407,11 +405,13 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d
407 probe_ent->mwdma_mask = 0x07; 405 probe_ent->mwdma_mask = 0x07;
408 probe_ent->udma_mask = 0x7f; 406 probe_ent->udma_mask = 0x7f;
409 407
408 mmio_base = probe_ent->iomap[VSC_MMIO_BAR];
409
410 /* We have 4 ports per PCI function */ 410 /* We have 4 ports per PCI function */
411 vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET); 411 vsc_sata_setup_port(&probe_ent->port[0], mmio_base + 1 * VSC_SATA_PORT_OFFSET);
412 vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET); 412 vsc_sata_setup_port(&probe_ent->port[1], mmio_base + 2 * VSC_SATA_PORT_OFFSET);
413 vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET); 413 vsc_sata_setup_port(&probe_ent->port[2], mmio_base + 3 * VSC_SATA_PORT_OFFSET);
414 vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET); 414 vsc_sata_setup_port(&probe_ent->port[3], mmio_base + 4 * VSC_SATA_PORT_OFFSET);
415 415
416 pci_set_master(pdev); 416 pci_set_master(pdev);
417 417