diff options
author | Tejun Heo <htejun@gmail.com> | 2007-02-01 01:06:36 -0500 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2007-02-09 17:39:38 -0500 |
commit | 0d5ff566779f894ca9937231a181eb31e4adff0e (patch) | |
tree | d1c7495c932581c1d41aa7f0fdb303348da49106 /drivers/ata/sata_sil.c | |
parent | 1a68ff13c8a9b517de3fd4187dc525412a6eba1b (diff) |
libata: convert to iomap
Convert libata core layer and LLDs to use iomap.
* managed iomap is used. Pointer to pcim_iomap_table() is cached at
host->iomap and used through out LLDs. This basically replaces
host->mmio_base.
* if possible, pcim_iomap_regions() is used
Most iomap operation conversions are taken from Jeff Garzik
<jgarzik@pobox.com>'s iomap branch.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/sata_sil.c')
-rw-r--r-- | drivers/ata/sata_sil.c | 46 |
1 files changed, 22 insertions, 24 deletions
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c index 00f2465dcdce..4a25093b2dda 100644 --- a/drivers/ata/sata_sil.c +++ b/drivers/ata/sata_sil.c | |||
@@ -49,6 +49,8 @@ | |||
49 | #define DRV_VERSION "2.0" | 49 | #define DRV_VERSION "2.0" |
50 | 50 | ||
51 | enum { | 51 | enum { |
52 | SIL_MMIO_BAR = 5, | ||
53 | |||
52 | /* | 54 | /* |
53 | * host flags | 55 | * host flags |
54 | */ | 56 | */ |
@@ -200,7 +202,7 @@ static const struct ata_port_operations sil_ops = { | |||
200 | .bmdma_status = ata_bmdma_status, | 202 | .bmdma_status = ata_bmdma_status, |
201 | .qc_prep = ata_qc_prep, | 203 | .qc_prep = ata_qc_prep, |
202 | .qc_issue = ata_qc_issue_prot, | 204 | .qc_issue = ata_qc_issue_prot, |
203 | .data_xfer = ata_mmio_data_xfer, | 205 | .data_xfer = ata_data_xfer, |
204 | .freeze = sil_freeze, | 206 | .freeze = sil_freeze, |
205 | .thaw = sil_thaw, | 207 | .thaw = sil_thaw, |
206 | .error_handler = ata_bmdma_error_handler, | 208 | .error_handler = ata_bmdma_error_handler, |
@@ -295,7 +297,8 @@ static void sil_post_set_mode (struct ata_port *ap) | |||
295 | { | 297 | { |
296 | struct ata_host *host = ap->host; | 298 | struct ata_host *host = ap->host; |
297 | struct ata_device *dev; | 299 | struct ata_device *dev; |
298 | void __iomem *addr = host->mmio_base + sil_port[ap->port_no].xfer_mode; | 300 | void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; |
301 | void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; | ||
299 | u32 tmp, dev_mode[2]; | 302 | u32 tmp, dev_mode[2]; |
300 | unsigned int i; | 303 | unsigned int i; |
301 | 304 | ||
@@ -318,9 +321,9 @@ static void sil_post_set_mode (struct ata_port *ap) | |||
318 | readl(addr); /* flush */ | 321 | readl(addr); /* flush */ |
319 | } | 322 | } |
320 | 323 | ||
321 | static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg) | 324 | static inline void __iomem *sil_scr_addr(struct ata_port *ap, unsigned int sc_reg) |
322 | { | 325 | { |
323 | unsigned long offset = ap->ioaddr.scr_addr; | 326 | void __iomem *offset = ap->ioaddr.scr_addr; |
324 | 327 | ||
325 | switch (sc_reg) { | 328 | switch (sc_reg) { |
326 | case SCR_STATUS: | 329 | case SCR_STATUS: |
@@ -339,7 +342,7 @@ static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_re | |||
339 | 342 | ||
340 | static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg) | 343 | static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg) |
341 | { | 344 | { |
342 | void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); | 345 | void __iomem *mmio = sil_scr_addr(ap, sc_reg); |
343 | if (mmio) | 346 | if (mmio) |
344 | return readl(mmio); | 347 | return readl(mmio); |
345 | return 0xffffffffU; | 348 | return 0xffffffffU; |
@@ -347,7 +350,7 @@ static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg) | |||
347 | 350 | ||
348 | static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | 351 | static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) |
349 | { | 352 | { |
350 | void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); | 353 | void __iomem *mmio = sil_scr_addr(ap, sc_reg); |
351 | if (mmio) | 354 | if (mmio) |
352 | writel(val, mmio); | 355 | writel(val, mmio); |
353 | } | 356 | } |
@@ -442,7 +445,7 @@ static void sil_host_intr(struct ata_port *ap, u32 bmdma2) | |||
442 | static irqreturn_t sil_interrupt(int irq, void *dev_instance) | 445 | static irqreturn_t sil_interrupt(int irq, void *dev_instance) |
443 | { | 446 | { |
444 | struct ata_host *host = dev_instance; | 447 | struct ata_host *host = dev_instance; |
445 | void __iomem *mmio_base = host->mmio_base; | 448 | void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; |
446 | int handled = 0; | 449 | int handled = 0; |
447 | int i; | 450 | int i; |
448 | 451 | ||
@@ -474,7 +477,7 @@ static irqreturn_t sil_interrupt(int irq, void *dev_instance) | |||
474 | 477 | ||
475 | static void sil_freeze(struct ata_port *ap) | 478 | static void sil_freeze(struct ata_port *ap) |
476 | { | 479 | { |
477 | void __iomem *mmio_base = ap->host->mmio_base; | 480 | void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; |
478 | u32 tmp; | 481 | u32 tmp; |
479 | 482 | ||
480 | /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ | 483 | /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ |
@@ -489,7 +492,7 @@ static void sil_freeze(struct ata_port *ap) | |||
489 | 492 | ||
490 | static void sil_thaw(struct ata_port *ap) | 493 | static void sil_thaw(struct ata_port *ap) |
491 | { | 494 | { |
492 | void __iomem *mmio_base = ap->host->mmio_base; | 495 | void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; |
493 | u32 tmp; | 496 | u32 tmp; |
494 | 497 | ||
495 | /* clear IRQ */ | 498 | /* clear IRQ */ |
@@ -621,7 +624,6 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |||
621 | static int printed_version; | 624 | static int printed_version; |
622 | struct device *dev = &pdev->dev; | 625 | struct device *dev = &pdev->dev; |
623 | struct ata_probe_ent *probe_ent; | 626 | struct ata_probe_ent *probe_ent; |
624 | unsigned long base; | ||
625 | void __iomem *mmio_base; | 627 | void __iomem *mmio_base; |
626 | int rc; | 628 | int rc; |
627 | unsigned int i; | 629 | unsigned int i; |
@@ -633,11 +635,11 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |||
633 | if (rc) | 635 | if (rc) |
634 | return rc; | 636 | return rc; |
635 | 637 | ||
636 | rc = pci_request_regions(pdev, DRV_NAME); | 638 | rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME); |
637 | if (rc) { | 639 | if (rc == -EBUSY) |
638 | pcim_pin_device(pdev); | 640 | pcim_pin_device(pdev); |
641 | if (rc) | ||
639 | return rc; | 642 | return rc; |
640 | } | ||
641 | 643 | ||
642 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | 644 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
643 | if (rc) | 645 | if (rc) |
@@ -662,20 +664,16 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |||
662 | probe_ent->irq_flags = IRQF_SHARED; | 664 | probe_ent->irq_flags = IRQF_SHARED; |
663 | probe_ent->port_flags = sil_port_info[ent->driver_data].flags; | 665 | probe_ent->port_flags = sil_port_info[ent->driver_data].flags; |
664 | 666 | ||
665 | mmio_base = pcim_iomap(pdev, 5, 0); | 667 | probe_ent->iomap = pcim_iomap_table(pdev); |
666 | if (mmio_base == NULL) | ||
667 | return -ENOMEM; | ||
668 | |||
669 | probe_ent->mmio_base = mmio_base; | ||
670 | 668 | ||
671 | base = (unsigned long) mmio_base; | 669 | mmio_base = probe_ent->iomap[SIL_MMIO_BAR]; |
672 | 670 | ||
673 | for (i = 0; i < probe_ent->n_ports; i++) { | 671 | for (i = 0; i < probe_ent->n_ports; i++) { |
674 | probe_ent->port[i].cmd_addr = base + sil_port[i].tf; | 672 | probe_ent->port[i].cmd_addr = mmio_base + sil_port[i].tf; |
675 | probe_ent->port[i].altstatus_addr = | 673 | probe_ent->port[i].altstatus_addr = |
676 | probe_ent->port[i].ctl_addr = base + sil_port[i].ctl; | 674 | probe_ent->port[i].ctl_addr = mmio_base + sil_port[i].ctl; |
677 | probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma; | 675 | probe_ent->port[i].bmdma_addr = mmio_base + sil_port[i].bmdma; |
678 | probe_ent->port[i].scr_addr = base + sil_port[i].scr; | 676 | probe_ent->port[i].scr_addr = mmio_base + sil_port[i].scr; |
679 | ata_std_ports(&probe_ent->port[i]); | 677 | ata_std_ports(&probe_ent->port[i]); |
680 | } | 678 | } |
681 | 679 | ||
@@ -702,7 +700,7 @@ static int sil_pci_device_resume(struct pci_dev *pdev) | |||
702 | return rc; | 700 | return rc; |
703 | 701 | ||
704 | sil_init_controller(pdev, host->n_ports, host->ports[0]->flags, | 702 | sil_init_controller(pdev, host->n_ports, host->ports[0]->flags, |
705 | host->mmio_base); | 703 | host->iomap[SIL_MMIO_BAR]); |
706 | ata_host_resume(host); | 704 | ata_host_resume(host); |
707 | 705 | ||
708 | return 0; | 706 | return 0; |