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authorTejun Heo <htejun@gmail.com>2007-04-17 10:44:08 -0400
committerJeff Garzik <jeff@garzik.org>2007-04-28 14:16:03 -0400
commit9a829ccfc833269bdb85751f5048288ab93678ac (patch)
tree89732ae0da2ce1b1076d6ce8e80ac6aad8d9deb0 /drivers/ata/sata_nv.c
parenteca25dca17630ae354f4b1df559ed90578b794fe (diff)
libata: convert ata_pci_init_native_mode() users to new init model
Convert drivers which use ata_pci_init_native_mode() to new init model. ata_pci_init_native_host() is used instead. sata_nv, sata_uli and sata_sis are in this category. Tested on nVidia Corporation CK804 Serial ATA Controller [10de:0054] in both BMDMA and ADMA mode. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/sata_nv.c')
-rw-r--r--drivers/ata/sata_nv.c97
1 files changed, 40 insertions, 57 deletions
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c
index 8a9473b16ec3..02169740ed24 100644
--- a/drivers/ata/sata_nv.c
+++ b/drivers/ata/sata_nv.c
@@ -369,7 +369,6 @@ static const struct ata_port_operations nv_generic_ops = {
369 .error_handler = nv_error_handler, 369 .error_handler = nv_error_handler,
370 .post_internal_cmd = ata_bmdma_post_internal_cmd, 370 .post_internal_cmd = ata_bmdma_post_internal_cmd,
371 .data_xfer = ata_data_xfer, 371 .data_xfer = ata_data_xfer,
372 .irq_handler = nv_generic_interrupt,
373 .irq_clear = ata_bmdma_irq_clear, 372 .irq_clear = ata_bmdma_irq_clear,
374 .irq_on = ata_irq_on, 373 .irq_on = ata_irq_on,
375 .irq_ack = ata_irq_ack, 374 .irq_ack = ata_irq_ack,
@@ -396,7 +395,6 @@ static const struct ata_port_operations nv_nf2_ops = {
396 .error_handler = nv_error_handler, 395 .error_handler = nv_error_handler,
397 .post_internal_cmd = ata_bmdma_post_internal_cmd, 396 .post_internal_cmd = ata_bmdma_post_internal_cmd,
398 .data_xfer = ata_data_xfer, 397 .data_xfer = ata_data_xfer,
399 .irq_handler = nv_nf2_interrupt,
400 .irq_clear = ata_bmdma_irq_clear, 398 .irq_clear = ata_bmdma_irq_clear,
401 .irq_on = ata_irq_on, 399 .irq_on = ata_irq_on,
402 .irq_ack = ata_irq_ack, 400 .irq_ack = ata_irq_ack,
@@ -423,7 +421,6 @@ static const struct ata_port_operations nv_ck804_ops = {
423 .error_handler = nv_error_handler, 421 .error_handler = nv_error_handler,
424 .post_internal_cmd = ata_bmdma_post_internal_cmd, 422 .post_internal_cmd = ata_bmdma_post_internal_cmd,
425 .data_xfer = ata_data_xfer, 423 .data_xfer = ata_data_xfer,
426 .irq_handler = nv_ck804_interrupt,
427 .irq_clear = ata_bmdma_irq_clear, 424 .irq_clear = ata_bmdma_irq_clear,
428 .irq_on = ata_irq_on, 425 .irq_on = ata_irq_on,
429 .irq_ack = ata_irq_ack, 426 .irq_ack = ata_irq_ack,
@@ -452,7 +449,6 @@ static const struct ata_port_operations nv_adma_ops = {
452 .error_handler = nv_adma_error_handler, 449 .error_handler = nv_adma_error_handler,
453 .post_internal_cmd = nv_adma_post_internal_cmd, 450 .post_internal_cmd = nv_adma_post_internal_cmd,
454 .data_xfer = ata_data_xfer, 451 .data_xfer = ata_data_xfer,
455 .irq_handler = nv_adma_interrupt,
456 .irq_clear = nv_adma_irq_clear, 452 .irq_clear = nv_adma_irq_clear,
457 .irq_on = ata_irq_on, 453 .irq_on = ata_irq_on,
458 .irq_ack = ata_irq_ack, 454 .irq_ack = ata_irq_ack,
@@ -477,6 +473,7 @@ static struct ata_port_info nv_port_info[] = {
477 .mwdma_mask = NV_MWDMA_MASK, 473 .mwdma_mask = NV_MWDMA_MASK,
478 .udma_mask = NV_UDMA_MASK, 474 .udma_mask = NV_UDMA_MASK,
479 .port_ops = &nv_generic_ops, 475 .port_ops = &nv_generic_ops,
476 .irq_handler = nv_generic_interrupt,
480 }, 477 },
481 /* nforce2/3 */ 478 /* nforce2/3 */
482 { 479 {
@@ -487,6 +484,7 @@ static struct ata_port_info nv_port_info[] = {
487 .mwdma_mask = NV_MWDMA_MASK, 484 .mwdma_mask = NV_MWDMA_MASK,
488 .udma_mask = NV_UDMA_MASK, 485 .udma_mask = NV_UDMA_MASK,
489 .port_ops = &nv_nf2_ops, 486 .port_ops = &nv_nf2_ops,
487 .irq_handler = nv_nf2_interrupt,
490 }, 488 },
491 /* ck804 */ 489 /* ck804 */
492 { 490 {
@@ -497,6 +495,7 @@ static struct ata_port_info nv_port_info[] = {
497 .mwdma_mask = NV_MWDMA_MASK, 495 .mwdma_mask = NV_MWDMA_MASK,
498 .udma_mask = NV_UDMA_MASK, 496 .udma_mask = NV_UDMA_MASK,
499 .port_ops = &nv_ck804_ops, 497 .port_ops = &nv_ck804_ops,
498 .irq_handler = nv_ck804_interrupt,
500 }, 499 },
501 /* ADMA */ 500 /* ADMA */
502 { 501 {
@@ -508,6 +507,7 @@ static struct ata_port_info nv_port_info[] = {
508 .mwdma_mask = NV_MWDMA_MASK, 507 .mwdma_mask = NV_MWDMA_MASK,
509 .udma_mask = NV_UDMA_MASK, 508 .udma_mask = NV_UDMA_MASK,
510 .port_ops = &nv_adma_ops, 509 .port_ops = &nv_adma_ops,
510 .irq_handler = nv_adma_interrupt,
511 }, 511 },
512}; 512};
513 513
@@ -1079,14 +1079,14 @@ static int nv_adma_port_resume(struct ata_port *ap)
1079} 1079}
1080#endif 1080#endif
1081 1081
1082static void nv_adma_setup_port(struct ata_probe_ent *probe_ent, unsigned int port) 1082static void nv_adma_setup_port(struct ata_port *ap)
1083{ 1083{
1084 void __iomem *mmio = probe_ent->iomap[NV_MMIO_BAR]; 1084 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1085 struct ata_ioports *ioport = &probe_ent->port[port]; 1085 struct ata_ioports *ioport = &ap->ioaddr;
1086 1086
1087 VPRINTK("ENTER\n"); 1087 VPRINTK("ENTER\n");
1088 1088
1089 mmio += NV_ADMA_PORT + port * NV_ADMA_PORT_SIZE; 1089 mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE;
1090 1090
1091 ioport->cmd_addr = mmio; 1091 ioport->cmd_addr = mmio;
1092 ioport->data_addr = mmio + (ATA_REG_DATA * 4); 1092 ioport->data_addr = mmio + (ATA_REG_DATA * 4);
@@ -1103,9 +1103,9 @@ static void nv_adma_setup_port(struct ata_probe_ent *probe_ent, unsigned int por
1103 ioport->ctl_addr = mmio + 0x20; 1103 ioport->ctl_addr = mmio + 0x20;
1104} 1104}
1105 1105
1106static int nv_adma_host_init(struct ata_probe_ent *probe_ent) 1106static int nv_adma_host_init(struct ata_host *host)
1107{ 1107{
1108 struct pci_dev *pdev = to_pci_dev(probe_ent->dev); 1108 struct pci_dev *pdev = to_pci_dev(host->dev);
1109 unsigned int i; 1109 unsigned int i;
1110 u32 tmp32; 1110 u32 tmp32;
1111 1111
@@ -1120,8 +1120,8 @@ static int nv_adma_host_init(struct ata_probe_ent *probe_ent)
1120 1120
1121 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32); 1121 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1122 1122
1123 for (i = 0; i < probe_ent->n_ports; i++) 1123 for (i = 0; i < host->n_ports; i++)
1124 nv_adma_setup_port(probe_ent, i); 1124 nv_adma_setup_port(host->ports[i]);
1125 1125
1126 return 0; 1126 return 0;
1127} 1127}
@@ -1480,14 +1480,13 @@ static void nv_adma_error_handler(struct ata_port *ap)
1480static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 1480static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1481{ 1481{
1482 static int printed_version = 0; 1482 static int printed_version = 0;
1483 struct ata_port_info *ppi[2]; 1483 const struct ata_port_info *ppi[2];
1484 struct ata_probe_ent *probe_ent; 1484 struct ata_host *host;
1485 struct nv_host_priv *hpriv; 1485 struct nv_host_priv *hpriv;
1486 int rc; 1486 int rc;
1487 u32 bar; 1487 u32 bar;
1488 void __iomem *base; 1488 void __iomem *base;
1489 unsigned long type = ent->driver_data; 1489 unsigned long type = ent->driver_data;
1490 int mask_set = 0;
1491 1490
1492 // Make sure this is a SATA controller by counting the number of bars 1491 // Make sure this is a SATA controller by counting the number of bars
1493 // (NVIDIA SATA controllers will always have six bars). Otherwise, 1492 // (NVIDIA SATA controllers will always have six bars). Otherwise,
@@ -1503,50 +1502,38 @@ static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1503 if (rc) 1502 if (rc)
1504 return rc; 1503 return rc;
1505 1504
1506 rc = pci_request_regions(pdev, DRV_NAME); 1505 /* determine type and allocate host */
1507 if (rc) { 1506 if (type >= CK804 && adma_enabled) {
1508 pcim_pin_device(pdev);
1509 return rc;
1510 }
1511
1512 if(type >= CK804 && adma_enabled) {
1513 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n"); 1507 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
1514 type = ADMA; 1508 type = ADMA;
1515 if(!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
1516 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1517 mask_set = 1;
1518 }
1519
1520 if(!mask_set) {
1521 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1522 if (rc)
1523 return rc;
1524 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1525 if (rc)
1526 return rc;
1527 } 1509 }
1528 1510
1529 rc = -ENOMEM; 1511 ppi[0] = ppi[1] = &nv_port_info[type];
1512 rc = ata_pci_prepare_native_host(pdev, ppi, 2, &host);
1513 if (rc)
1514 return rc;
1530 1515
1531 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 1516 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1532 if (!hpriv) 1517 if (!hpriv)
1533 return -ENOMEM; 1518 return -ENOMEM;
1519 hpriv->type = type;
1520 host->private_data = hpriv;
1534 1521
1535 ppi[0] = ppi[1] = &nv_port_info[type]; 1522 /* set 64bit dma masks, may fail */
1536 probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); 1523 if (type == ADMA) {
1537 if (!probe_ent) 1524 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0)
1538 return -ENOMEM; 1525 pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1539 1526 }
1540 if (!pcim_iomap(pdev, NV_MMIO_BAR, 0))
1541 return -EIO;
1542 probe_ent->iomap = pcim_iomap_table(pdev);
1543 1527
1544 probe_ent->private_data = hpriv; 1528 /* request and iomap NV_MMIO_BAR */
1545 hpriv->type = type; 1529 rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME);
1530 if (rc)
1531 return rc;
1546 1532
1547 base = probe_ent->iomap[NV_MMIO_BAR]; 1533 /* configure SCR access */
1548 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET; 1534 base = host->iomap[NV_MMIO_BAR];
1549 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET; 1535 host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
1536 host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
1550 1537
1551 /* enable SATA space for CK804 */ 1538 /* enable SATA space for CK804 */
1552 if (type >= CK804) { 1539 if (type >= CK804) {
@@ -1557,20 +1544,16 @@ static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1557 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); 1544 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1558 } 1545 }
1559 1546
1560 pci_set_master(pdev); 1547 /* init ADMA */
1561
1562 if (type == ADMA) { 1548 if (type == ADMA) {
1563 rc = nv_adma_host_init(probe_ent); 1549 rc = nv_adma_host_init(host);
1564 if (rc) 1550 if (rc)
1565 return rc; 1551 return rc;
1566 } 1552 }
1567 1553
1568 rc = ata_device_add(probe_ent); 1554 pci_set_master(pdev);
1569 if (rc != NV_PORTS) 1555 return ata_host_activate(host, pdev->irq, ppi[0]->irq_handler,
1570 return -ENODEV; 1556 IRQF_SHARED, ppi[0]->sht);
1571
1572 devm_kfree(&pdev->dev, probe_ent);
1573 return 0;
1574} 1557}
1575 1558
1576static void nv_remove_one (struct pci_dev *pdev) 1559static void nv_remove_one (struct pci_dev *pdev)