diff options
author | Jeff Garzik <jeff@garzik.org> | 2007-10-25 20:47:30 -0400 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2007-10-29 06:15:27 -0400 |
commit | b447916e2b8c80f37aa88512ea39a05d5d11507d (patch) | |
tree | 4c608cd83ddd3434257dac450b52d8b52438dd12 /drivers/ata/sata_nv.c | |
parent | 88ff6eafbb2a1c55f0f0e2e16d72e7b10d8ae8a5 (diff) |
[libata] fix 'if(' and similar areas that lack whitespace
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/ata/sata_nv.c')
-rw-r--r-- | drivers/ata/sata_nv.c | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c index f1b422f7c749..8d55f7fb50af 100644 --- a/drivers/ata/sata_nv.c +++ b/drivers/ata/sata_nv.c | |||
@@ -1012,7 +1012,7 @@ static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance) | |||
1012 | u32 check_commands; | 1012 | u32 check_commands; |
1013 | int pos, error = 0; | 1013 | int pos, error = 0; |
1014 | 1014 | ||
1015 | if(ata_tag_valid(ap->link.active_tag)) | 1015 | if (ata_tag_valid(ap->link.active_tag)) |
1016 | check_commands = 1 << ap->link.active_tag; | 1016 | check_commands = 1 << ap->link.active_tag; |
1017 | else | 1017 | else |
1018 | check_commands = ap->link.sactive; | 1018 | check_commands = ap->link.sactive; |
@@ -1028,7 +1028,7 @@ static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance) | |||
1028 | } | 1028 | } |
1029 | } | 1029 | } |
1030 | 1030 | ||
1031 | if(notifier_clears[0] || notifier_clears[1]) { | 1031 | if (notifier_clears[0] || notifier_clears[1]) { |
1032 | /* Note: Both notifier clear registers must be written | 1032 | /* Note: Both notifier clear registers must be written |
1033 | if either is set, even if one is zero, according to NVIDIA. */ | 1033 | if either is set, even if one is zero, according to NVIDIA. */ |
1034 | struct nv_adma_port_priv *pp = host->ports[0]->private_data; | 1034 | struct nv_adma_port_priv *pp = host->ports[0]->private_data; |
@@ -1119,7 +1119,7 @@ static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc) | |||
1119 | { | 1119 | { |
1120 | struct nv_adma_port_priv *pp = qc->ap->private_data; | 1120 | struct nv_adma_port_priv *pp = qc->ap->private_data; |
1121 | 1121 | ||
1122 | if(pp->flags & NV_ADMA_PORT_REGISTER_MODE) | 1122 | if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) |
1123 | ata_bmdma_post_internal_cmd(qc); | 1123 | ata_bmdma_post_internal_cmd(qc); |
1124 | } | 1124 | } |
1125 | 1125 | ||
@@ -1194,10 +1194,10 @@ static int nv_adma_port_start(struct ata_port *ap) | |||
1194 | 1194 | ||
1195 | tmp = readw(mmio + NV_ADMA_CTL); | 1195 | tmp = readw(mmio + NV_ADMA_CTL); |
1196 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | 1196 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
1197 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ | 1197 | readw(mmio + NV_ADMA_CTL ); /* flush posted write */ |
1198 | udelay(1); | 1198 | udelay(1); |
1199 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | 1199 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
1200 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ | 1200 | readw(mmio + NV_ADMA_CTL ); /* flush posted write */ |
1201 | 1201 | ||
1202 | return 0; | 1202 | return 0; |
1203 | } | 1203 | } |
@@ -1255,10 +1255,10 @@ static int nv_adma_port_resume(struct ata_port *ap) | |||
1255 | 1255 | ||
1256 | tmp = readw(mmio + NV_ADMA_CTL); | 1256 | tmp = readw(mmio + NV_ADMA_CTL); |
1257 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | 1257 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
1258 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ | 1258 | readw(mmio + NV_ADMA_CTL ); /* flush posted write */ |
1259 | udelay(1); | 1259 | udelay(1); |
1260 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | 1260 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
1261 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ | 1261 | readw(mmio + NV_ADMA_CTL ); /* flush posted write */ |
1262 | 1262 | ||
1263 | return 0; | 1263 | return 0; |
1264 | } | 1264 | } |
@@ -1359,12 +1359,12 @@ static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc) | |||
1359 | /* ADMA engine can only be used for non-ATAPI DMA commands, | 1359 | /* ADMA engine can only be used for non-ATAPI DMA commands, |
1360 | or interrupt-driven no-data commands, where a result taskfile | 1360 | or interrupt-driven no-data commands, where a result taskfile |
1361 | is not required. */ | 1361 | is not required. */ |
1362 | if((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) || | 1362 | if ((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) || |
1363 | (qc->tf.flags & ATA_TFLAG_POLLING) || | 1363 | (qc->tf.flags & ATA_TFLAG_POLLING) || |
1364 | (qc->flags & ATA_QCFLAG_RESULT_TF)) | 1364 | (qc->flags & ATA_QCFLAG_RESULT_TF)) |
1365 | return 1; | 1365 | return 1; |
1366 | 1366 | ||
1367 | if((qc->flags & ATA_QCFLAG_DMAMAP) || | 1367 | if ((qc->flags & ATA_QCFLAG_DMAMAP) || |
1368 | (qc->tf.protocol == ATA_PROT_NODATA)) | 1368 | (qc->tf.protocol == ATA_PROT_NODATA)) |
1369 | return 0; | 1369 | return 0; |
1370 | 1370 | ||
@@ -1401,7 +1401,7 @@ static void nv_adma_qc_prep(struct ata_queued_cmd *qc) | |||
1401 | 1401 | ||
1402 | nv_adma_tf_to_cpb(&qc->tf, cpb->tf); | 1402 | nv_adma_tf_to_cpb(&qc->tf, cpb->tf); |
1403 | 1403 | ||
1404 | if(qc->flags & ATA_QCFLAG_DMAMAP) { | 1404 | if (qc->flags & ATA_QCFLAG_DMAMAP) { |
1405 | nv_adma_fill_sg(qc, cpb); | 1405 | nv_adma_fill_sg(qc, cpb); |
1406 | ctl_flags |= NV_CPB_CTL_APRD_VALID; | 1406 | ctl_flags |= NV_CPB_CTL_APRD_VALID; |
1407 | } else | 1407 | } else |
@@ -1435,7 +1435,7 @@ static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc) | |||
1435 | and (number of cpbs to append -1) in top 8 bits */ | 1435 | and (number of cpbs to append -1) in top 8 bits */ |
1436 | wmb(); | 1436 | wmb(); |
1437 | 1437 | ||
1438 | if(curr_ncq != pp->last_issue_ncq) { | 1438 | if (curr_ncq != pp->last_issue_ncq) { |
1439 | /* Seems to need some delay before switching between NCQ and non-NCQ | 1439 | /* Seems to need some delay before switching between NCQ and non-NCQ |
1440 | commands, else we get command timeouts and such. */ | 1440 | commands, else we get command timeouts and such. */ |
1441 | udelay(20); | 1441 | udelay(20); |
@@ -1641,12 +1641,12 @@ static void nv_error_handler(struct ata_port *ap) | |||
1641 | static void nv_adma_error_handler(struct ata_port *ap) | 1641 | static void nv_adma_error_handler(struct ata_port *ap) |
1642 | { | 1642 | { |
1643 | struct nv_adma_port_priv *pp = ap->private_data; | 1643 | struct nv_adma_port_priv *pp = ap->private_data; |
1644 | if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) { | 1644 | if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) { |
1645 | void __iomem *mmio = pp->ctl_block; | 1645 | void __iomem *mmio = pp->ctl_block; |
1646 | int i; | 1646 | int i; |
1647 | u16 tmp; | 1647 | u16 tmp; |
1648 | 1648 | ||
1649 | if(ata_tag_valid(ap->link.active_tag) || ap->link.sactive) { | 1649 | if (ata_tag_valid(ap->link.active_tag) || ap->link.sactive) { |
1650 | u32 notifier = readl(mmio + NV_ADMA_NOTIFIER); | 1650 | u32 notifier = readl(mmio + NV_ADMA_NOTIFIER); |
1651 | u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR); | 1651 | u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR); |
1652 | u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL); | 1652 | u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL); |
@@ -1660,9 +1660,9 @@ static void nv_adma_error_handler(struct ata_port *ap) | |||
1660 | notifier, notifier_error, gen_ctl, status, | 1660 | notifier, notifier_error, gen_ctl, status, |
1661 | cpb_count, next_cpb_idx); | 1661 | cpb_count, next_cpb_idx); |
1662 | 1662 | ||
1663 | for( i=0;i<NV_ADMA_MAX_CPBS;i++) { | 1663 | for (i = 0; i < NV_ADMA_MAX_CPBS; i++) { |
1664 | struct nv_adma_cpb *cpb = &pp->cpb[i]; | 1664 | struct nv_adma_cpb *cpb = &pp->cpb[i]; |
1665 | if( (ata_tag_valid(ap->link.active_tag) && i == ap->link.active_tag) || | 1665 | if ((ata_tag_valid(ap->link.active_tag) && i == ap->link.active_tag) || |
1666 | ap->link.sactive & (1 << i) ) | 1666 | ap->link.sactive & (1 << i) ) |
1667 | ata_port_printk(ap, KERN_ERR, | 1667 | ata_port_printk(ap, KERN_ERR, |
1668 | "CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n", | 1668 | "CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n", |
@@ -1674,7 +1674,7 @@ static void nv_adma_error_handler(struct ata_port *ap) | |||
1674 | nv_adma_register_mode(ap); | 1674 | nv_adma_register_mode(ap); |
1675 | 1675 | ||
1676 | /* Mark all of the CPBs as invalid to prevent them from being executed */ | 1676 | /* Mark all of the CPBs as invalid to prevent them from being executed */ |
1677 | for( i=0;i<NV_ADMA_MAX_CPBS;i++) | 1677 | for (i = 0; i < NV_ADMA_MAX_CPBS; i++) |
1678 | pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID; | 1678 | pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID; |
1679 | 1679 | ||
1680 | /* clear CPB fetch count */ | 1680 | /* clear CPB fetch count */ |
@@ -1683,10 +1683,10 @@ static void nv_adma_error_handler(struct ata_port *ap) | |||
1683 | /* Reset channel */ | 1683 | /* Reset channel */ |
1684 | tmp = readw(mmio + NV_ADMA_CTL); | 1684 | tmp = readw(mmio + NV_ADMA_CTL); |
1685 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | 1685 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
1686 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ | 1686 | readw(mmio + NV_ADMA_CTL); /* flush posted write */ |
1687 | udelay(1); | 1687 | udelay(1); |
1688 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | 1688 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
1689 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ | 1689 | readw(mmio + NV_ADMA_CTL); /* flush posted write */ |
1690 | } | 1690 | } |
1691 | 1691 | ||
1692 | ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, | 1692 | ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, |
@@ -2440,32 +2440,32 @@ static int nv_pci_device_resume(struct pci_dev *pdev) | |||
2440 | int rc; | 2440 | int rc; |
2441 | 2441 | ||
2442 | rc = ata_pci_device_do_resume(pdev); | 2442 | rc = ata_pci_device_do_resume(pdev); |
2443 | if(rc) | 2443 | if (rc) |
2444 | return rc; | 2444 | return rc; |
2445 | 2445 | ||
2446 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | 2446 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
2447 | if(hpriv->type >= CK804) { | 2447 | if (hpriv->type >= CK804) { |
2448 | u8 regval; | 2448 | u8 regval; |
2449 | 2449 | ||
2450 | pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); | 2450 | pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); |
2451 | regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; | 2451 | regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; |
2452 | pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); | 2452 | pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); |
2453 | } | 2453 | } |
2454 | if(hpriv->type == ADMA) { | 2454 | if (hpriv->type == ADMA) { |
2455 | u32 tmp32; | 2455 | u32 tmp32; |
2456 | struct nv_adma_port_priv *pp; | 2456 | struct nv_adma_port_priv *pp; |
2457 | /* enable/disable ADMA on the ports appropriately */ | 2457 | /* enable/disable ADMA on the ports appropriately */ |
2458 | pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32); | 2458 | pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32); |
2459 | 2459 | ||
2460 | pp = host->ports[0]->private_data; | 2460 | pp = host->ports[0]->private_data; |
2461 | if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) | 2461 | if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) |
2462 | tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN | | 2462 | tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN | |
2463 | NV_MCP_SATA_CFG_20_PORT0_PWB_EN); | 2463 | NV_MCP_SATA_CFG_20_PORT0_PWB_EN); |
2464 | else | 2464 | else |
2465 | tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN | | 2465 | tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN | |
2466 | NV_MCP_SATA_CFG_20_PORT0_PWB_EN); | 2466 | NV_MCP_SATA_CFG_20_PORT0_PWB_EN); |
2467 | pp = host->ports[1]->private_data; | 2467 | pp = host->ports[1]->private_data; |
2468 | if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) | 2468 | if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) |
2469 | tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN | | 2469 | tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN | |
2470 | NV_MCP_SATA_CFG_20_PORT1_PWB_EN); | 2470 | NV_MCP_SATA_CFG_20_PORT1_PWB_EN); |
2471 | else | 2471 | else |