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authorMark Lord <liml@rtr.ca>2008-05-27 17:54:48 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-05-30 12:37:20 -0400
commit1f39847255a02c69190ae30c33b8ccf4c10840df (patch)
tree72bc7993a8c1591481972bde316519cafd945907 /drivers/ata/sata_mv.c
parent1beee8dc8cf58e3f605bd7b34d7a39939be7d8d2 (diff)
sata_mv: move SOC_FLAG to hpriv
Convert the System-on-Chip flag from a host flag to an hpriv flag, for better consistency with other chip-rev flags, and for easier use in errata fixes etc. Also change the related "HAS_PCI()" into "!IS_SOC()" for better consistency of naming/use (everything else SOC-related already uses "SOC"). There are no functionality changes in this patch. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/ata/sata_mv.c')
-rw-r--r--drivers/ata/sata_mv.c27
1 files changed, 13 insertions, 14 deletions
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index fb81f0c7a8c2..f6a716ef5a16 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -122,8 +122,6 @@ enum {
122 /* Host Flags */ 122 /* Host Flags */
123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
125 /* SoC integrated controllers, no PCI interface */
126 MV_FLAG_SOC = (1 << 28),
127 125
128 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 126 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
129 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 127 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
@@ -362,6 +360,7 @@ enum {
362 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 360 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
363 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 361 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
364 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 362 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
363 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
365 364
366 /* Port private flags (pp_flags) */ 365 /* Port private flags (pp_flags) */
367 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 366 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
@@ -374,7 +373,7 @@ enum {
374#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 373#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
375#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 374#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
376#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 375#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
377#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) 376#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
378 377
379#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 378#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
380#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 379#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
@@ -652,7 +651,7 @@ static const struct ata_port_info mv_port_info[] = {
652 .port_ops = &mv_iie_ops, 651 .port_ops = &mv_iie_ops,
653 }, 652 },
654 { /* chip_soc */ 653 { /* chip_soc */
655 .flags = MV_GENIIE_FLAGS | MV_FLAG_SOC, 654 .flags = MV_GENIIE_FLAGS,
656 .pio_mask = 0x1f, /* pio0-4 */ 655 .pio_mask = 0x1f, /* pio0-4 */
657 .udma_mask = ATA_UDMA6, 656 .udma_mask = ATA_UDMA6,
658 .port_ops = &mv_iie_ops, 657 .port_ops = &mv_iie_ops,
@@ -1254,7 +1253,7 @@ static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
1254 1253
1255 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1254 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1256 cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1255 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1257 if (HAS_PCI(ap->host)) 1256 if (!IS_SOC(hpriv))
1258 cfg |= (1 << 18); /* enab early completion */ 1257 cfg |= (1 << 18); /* enab early completion */
1259 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1258 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1260 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1259 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
@@ -2225,7 +2224,7 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2225 * a bogus register value which can indicate HW removal or PCI fault. 2224 * a bogus register value which can indicate HW removal or PCI fault.
2226 */ 2225 */
2227 if (pending_irqs && main_irq_cause != 0xffffffffU) { 2226 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2228 if (unlikely((pending_irqs & PCI_ERR) && HAS_PCI(host))) 2227 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2229 handled = mv_pci_error(host, hpriv->base); 2228 handled = mv_pci_error(host, hpriv->base);
2230 else 2229 else
2231 handled = mv_host_intr(host, pending_irqs); 2230 handled = mv_host_intr(host, pending_irqs);
@@ -2876,7 +2875,7 @@ static unsigned int mv_in_pcix_mode(struct ata_host *host)
2876 void __iomem *mmio = hpriv->base; 2875 void __iomem *mmio = hpriv->base;
2877 u32 reg; 2876 u32 reg;
2878 2877
2879 if (!HAS_PCI(host) || !IS_PCIE(hpriv)) 2878 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
2880 return 0; /* not PCI-X capable */ 2879 return 0; /* not PCI-X capable */
2881 reg = readl(mmio + MV_PCI_MODE_OFS); 2880 reg = readl(mmio + MV_PCI_MODE_OFS);
2882 if ((reg & MV_PCI_MODE_MASK) == 0) 2881 if ((reg & MV_PCI_MODE_MASK) == 0)
@@ -3018,7 +3017,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3018 break; 3017 break;
3019 case chip_soc: 3018 case chip_soc:
3020 hpriv->ops = &mv_soc_ops; 3019 hpriv->ops = &mv_soc_ops;
3021 hp_flags |= MV_HP_ERRATA_60X1C0; 3020 hp_flags |= MV_HP_FLAG_SOC | MV_HP_ERRATA_60X1C0;
3022 break; 3021 break;
3023 3022
3024 default: 3023 default:
@@ -3062,12 +3061,12 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3062 if (rc) 3061 if (rc)
3063 goto done; 3062 goto done;
3064 3063
3065 if (HAS_PCI(host)) { 3064 if (IS_SOC(hpriv)) {
3066 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3067 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3068 } else {
3069 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS; 3065 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3070 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS; 3066 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3067 } else {
3068 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3069 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3071 } 3070 }
3072 3071
3073 /* global interrupt mask: 0 == mask everything */ 3072 /* global interrupt mask: 0 == mask everything */
@@ -3093,7 +3092,7 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3093 mv_port_init(&ap->ioaddr, port_mmio); 3092 mv_port_init(&ap->ioaddr, port_mmio);
3094 3093
3095#ifdef CONFIG_PCI 3094#ifdef CONFIG_PCI
3096 if (HAS_PCI(host)) { 3095 if (!IS_SOC(hpriv)) {
3097 unsigned int offset = port_mmio - mmio; 3096 unsigned int offset = port_mmio - mmio;
3098 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 3097 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3099 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 3098 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
@@ -3113,7 +3112,7 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3113 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 3112 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3114 } 3113 }
3115 3114
3116 if (HAS_PCI(host)) { 3115 if (!IS_SOC(hpriv)) {
3117 /* Clear any currently outstanding host interrupt conditions */ 3116 /* Clear any currently outstanding host interrupt conditions */
3118 writelfl(0, mmio + hpriv->irq_cause_ofs); 3117 writelfl(0, mmio + hpriv->irq_cause_ofs);
3119 3118