diff options
author | Tejun Heo <htejun@gmail.com> | 2007-07-16 01:29:40 -0400 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2007-07-20 08:02:11 -0400 |
commit | da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9d (patch) | |
tree | 289239e1eb60168321e905c545aa2e2f3a2b5475 /drivers/ata/sata_mv.c | |
parent | 5335b729064e03319cd2d5219770451dbb1d7f67 (diff) |
libata: make ->scr_read/write callbacks return error code
Convert ->scr_read/write callbacks to return error code to better
indicate failure. This will help handling of SCR_NOTIFICATION.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/sata_mv.c')
-rw-r--r-- | drivers/ata/sata_mv.c | 72 |
1 files changed, 48 insertions, 24 deletions
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index b4b737e081e8..8ec520885b95 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c | |||
@@ -404,10 +404,10 @@ struct mv_host_priv { | |||
404 | }; | 404 | }; |
405 | 405 | ||
406 | static void mv_irq_clear(struct ata_port *ap); | 406 | static void mv_irq_clear(struct ata_port *ap); |
407 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in); | 407 | static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); |
408 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); | 408 | static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); |
409 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in); | 409 | static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); |
410 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); | 410 | static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); |
411 | static int mv_port_start(struct ata_port *ap); | 411 | static int mv_port_start(struct ata_port *ap); |
412 | static void mv_port_stop(struct ata_port *ap); | 412 | static void mv_port_stop(struct ata_port *ap); |
413 | static void mv_qc_prep(struct ata_queued_cmd *qc); | 413 | static void mv_qc_prep(struct ata_queued_cmd *qc); |
@@ -974,22 +974,26 @@ static unsigned int mv_scr_offset(unsigned int sc_reg_in) | |||
974 | return ofs; | 974 | return ofs; |
975 | } | 975 | } |
976 | 976 | ||
977 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in) | 977 | static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) |
978 | { | 978 | { |
979 | unsigned int ofs = mv_scr_offset(sc_reg_in); | 979 | unsigned int ofs = mv_scr_offset(sc_reg_in); |
980 | 980 | ||
981 | if (ofs != 0xffffffffU) | 981 | if (ofs != 0xffffffffU) { |
982 | return readl(mv_ap_base(ap) + ofs); | 982 | *val = readl(mv_ap_base(ap) + ofs); |
983 | else | 983 | return 0; |
984 | return (u32) ofs; | 984 | } else |
985 | return -EINVAL; | ||
985 | } | 986 | } |
986 | 987 | ||
987 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) | 988 | static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) |
988 | { | 989 | { |
989 | unsigned int ofs = mv_scr_offset(sc_reg_in); | 990 | unsigned int ofs = mv_scr_offset(sc_reg_in); |
990 | 991 | ||
991 | if (ofs != 0xffffffffU) | 992 | if (ofs != 0xffffffffU) { |
992 | writelfl(val, mv_ap_base(ap) + ofs); | 993 | writelfl(val, mv_ap_base(ap) + ofs); |
994 | return 0; | ||
995 | } else | ||
996 | return -EINVAL; | ||
993 | } | 997 | } |
994 | 998 | ||
995 | static void mv_edma_cfg(struct ata_port *ap, struct mv_host_priv *hpriv, | 999 | static void mv_edma_cfg(struct ata_port *ap, struct mv_host_priv *hpriv, |
@@ -1752,26 +1756,30 @@ static unsigned int mv5_scr_offset(unsigned int sc_reg_in) | |||
1752 | return ofs; | 1756 | return ofs; |
1753 | } | 1757 | } |
1754 | 1758 | ||
1755 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in) | 1759 | static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) |
1756 | { | 1760 | { |
1757 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; | 1761 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; |
1758 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); | 1762 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); |
1759 | unsigned int ofs = mv5_scr_offset(sc_reg_in); | 1763 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
1760 | 1764 | ||
1761 | if (ofs != 0xffffffffU) | 1765 | if (ofs != 0xffffffffU) { |
1762 | return readl(addr + ofs); | 1766 | *val = readl(addr + ofs); |
1763 | else | 1767 | return 0; |
1764 | return (u32) ofs; | 1768 | } else |
1769 | return -EINVAL; | ||
1765 | } | 1770 | } |
1766 | 1771 | ||
1767 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) | 1772 | static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) |
1768 | { | 1773 | { |
1769 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; | 1774 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; |
1770 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); | 1775 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); |
1771 | unsigned int ofs = mv5_scr_offset(sc_reg_in); | 1776 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
1772 | 1777 | ||
1773 | if (ofs != 0xffffffffU) | 1778 | if (ofs != 0xffffffffU) { |
1774 | writelfl(val, addr + ofs); | 1779 | writelfl(val, addr + ofs); |
1780 | return 0; | ||
1781 | } else | ||
1782 | return -EINVAL; | ||
1775 | } | 1783 | } |
1776 | 1784 | ||
1777 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio) | 1785 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio) |
@@ -2149,9 +2157,17 @@ static void mv_phy_reset(struct ata_port *ap, unsigned int *class, | |||
2149 | 2157 | ||
2150 | VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio); | 2158 | VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio); |
2151 | 2159 | ||
2152 | DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " | 2160 | #ifdef DEBUG |
2153 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), | 2161 | { |
2154 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); | 2162 | u32 sstatus, serror, scontrol; |
2163 | |||
2164 | mv_scr_read(ap, SCR_STATUS, &sstatus); | ||
2165 | mv_scr_read(ap, SCR_ERROR, &serror); | ||
2166 | mv_scr_read(ap, SCR_CONTROL, &scontrol); | ||
2167 | DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " | ||
2168 | "SCtrl 0x%08x\n", status, serror, scontrol); | ||
2169 | } | ||
2170 | #endif | ||
2155 | 2171 | ||
2156 | /* Issue COMRESET via SControl */ | 2172 | /* Issue COMRESET via SControl */ |
2157 | comreset_retry: | 2173 | comreset_retry: |
@@ -2175,9 +2191,17 @@ comreset_retry: | |||
2175 | (retry-- > 0)) | 2191 | (retry-- > 0)) |
2176 | goto comreset_retry; | 2192 | goto comreset_retry; |
2177 | 2193 | ||
2178 | DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " | 2194 | #ifdef DEBUG |
2179 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), | 2195 | { |
2180 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); | 2196 | u32 sstatus, serror, scontrol; |
2197 | |||
2198 | mv_scr_read(ap, SCR_STATUS, &sstatus); | ||
2199 | mv_scr_read(ap, SCR_ERROR, &serror); | ||
2200 | mv_scr_read(ap, SCR_CONTROL, &scontrol); | ||
2201 | DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " | ||
2202 | "SCtrl 0x%08x\n", sstatus, serror, scontrol); | ||
2203 | } | ||
2204 | #endif | ||
2181 | 2205 | ||
2182 | if (ata_port_offline(ap)) { | 2206 | if (ata_port_offline(ap)) { |
2183 | *class = ATA_DEV_NONE; | 2207 | *class = ATA_DEV_NONE; |