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authorLi Yang <leoli@freescale.com>2007-10-16 08:58:38 -0400
committerJeff Garzik <jeff@garzik.org>2007-10-17 20:49:02 -0400
commitfaf0b2e5afe7dae072d2715763c7f992b612b628 (patch)
tree547accc48efc5c63f9b3c9a7a67a77ffffc06ee9 /drivers/ata/sata_fsl.c
parent8e2840e06d7da7ae17b1fbc416155a40b22e00ad (diff)
drivers/ata: add support to Freescale 3.0Gbps SATA Controller
This patch adds support for Freescale 3.0Gbps SATA Controller supporting Native Command Queueing(NCQ), device hotplug, and ATAPI. This controller can be found on MPC8315 and MPC8378. Signed-off-by: Ashish Kalra <ashish.kalra@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/sata_fsl.c')
-rw-r--r--drivers/ata/sata_fsl.c1490
1 files changed, 1490 insertions, 0 deletions
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
new file mode 100644
index 000000000000..b4c37b9e413c
--- /dev/null
+++ b/drivers/ata/sata_fsl.c
@@ -0,0 +1,1490 @@
1/*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21
22#include <scsi/scsi_host.h>
23#include <scsi/scsi_cmnd.h>
24#include <linux/libata.h>
25#include <asm/io.h>
26#include <linux/of_platform.h>
27
28/* Controller information */
29enum {
30 SATA_FSL_QUEUE_DEPTH = 16,
31 SATA_FSL_MAX_PRD = 63,
32 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
33 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
34
35 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
36 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
37 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY),
38
39 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
40 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
41 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
42
43 /*
44 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
45 * chained indirect PRDEs upto a max count of 63.
46 * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will
47 * be setup as an indirect descriptor, pointing to it's next
48 * (contigious) PRDE. Though chained indirect PRDE arrays are
49 * supported,it will be more efficient to use a direct PRDT and
50 * a single chain/link to indirect PRDE array/PRDT.
51 */
52
53 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
54 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
55 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
56 SATA_FSL_CMD_DESC_RSRVD = 16,
57
58 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
59 SATA_FSL_CMD_DESC_SFIS_SZ +
60 SATA_FSL_CMD_DESC_ACMD_SZ +
61 SATA_FSL_CMD_DESC_RSRVD +
62 SATA_FSL_MAX_PRD * 16),
63
64 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
65 (SATA_FSL_CMD_DESC_CFIS_SZ +
66 SATA_FSL_CMD_DESC_SFIS_SZ +
67 SATA_FSL_CMD_DESC_ACMD_SZ +
68 SATA_FSL_CMD_DESC_RSRVD),
69
70 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
71 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
72 SATA_FSL_CMD_DESC_AR_SZ),
73
74 /*
75 * MPC8315 has two SATA controllers, SATA1 & SATA2
76 * (one port per controller)
77 * MPC837x has 2/4 controllers, one port per controller
78 */
79
80 SATA_FSL_MAX_PORTS = 1,
81
82 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
83};
84
85/*
86* Host Controller command register set - per port
87*/
88enum {
89 CQ = 0,
90 CA = 8,
91 CC = 0x10,
92 CE = 0x18,
93 DE = 0x20,
94 CHBA = 0x24,
95 HSTATUS = 0x28,
96 HCONTROL = 0x2C,
97 CQPMP = 0x30,
98 SIGNATURE = 0x34,
99 ICC = 0x38,
100
101 /*
102 * Host Status Register (HStatus) bitdefs
103 */
104 ONLINE = (1 << 31),
105 GOING_OFFLINE = (1 << 30),
106 BIST_ERR = (1 << 29),
107
108 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
109 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
110 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
111 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
112 FATAL_ERR_DATA_OVERRUN = (1 << 12),
113 FATAL_ERR_CRC_ERR_TX = (1 << 11),
114 FATAL_ERR_CRC_ERR_RX = (1 << 10),
115 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
116 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
117
118 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
119 FATAL_ERR_PARITY_ERR_TX |
120 FATAL_ERR_PARITY_ERR_RX |
121 FATAL_ERR_DATA_UNDERRUN |
122 FATAL_ERR_DATA_OVERRUN |
123 FATAL_ERR_CRC_ERR_TX |
124 FATAL_ERR_CRC_ERR_RX |
125 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
126
127 INT_ON_FATAL_ERR = (1 << 5),
128 INT_ON_PHYRDY_CHG = (1 << 4),
129
130 INT_ON_SIGNATURE_UPDATE = (1 << 3),
131 INT_ON_SNOTIFY_UPDATE = (1 << 2),
132 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
133 INT_ON_CMD_COMPLETE = 1,
134
135 INT_ON_ERROR = INT_ON_FATAL_ERR |
136 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
137
138 /*
139 * Host Control Register (HControl) bitdefs
140 */
141 HCONTROL_ONLINE_PHY_RST = (1 << 31),
142 HCONTROL_FORCE_OFFLINE = (1 << 30),
143 HCONTROL_PARITY_PROT_MOD = (1 << 14),
144 HCONTROL_DPATH_PARITY = (1 << 12),
145 HCONTROL_SNOOP_ENABLE = (1 << 10),
146 HCONTROL_PMP_ATTACHED = (1 << 9),
147 HCONTROL_COPYOUT_STATFIS = (1 << 8),
148 IE_ON_FATAL_ERR = (1 << 5),
149 IE_ON_PHYRDY_CHG = (1 << 4),
150 IE_ON_SIGNATURE_UPDATE = (1 << 3),
151 IE_ON_SNOTIFY_UPDATE = (1 << 2),
152 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
153 IE_ON_CMD_COMPLETE = 1,
154
155 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
156 IE_ON_SIGNATURE_UPDATE |
157 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
158
159 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
160 DATA_SNOOP_ENABLE = (1 << 22),
161};
162
163/*
164 * SATA Superset Registers
165 */
166enum {
167 SSTATUS = 0,
168 SERROR = 4,
169 SCONTROL = 8,
170 SNOTIFY = 0xC,
171};
172
173/*
174 * Control Status Register Set
175 */
176enum {
177 TRANSCFG = 0,
178 TRANSSTATUS = 4,
179 LINKCFG = 8,
180 LINKCFG1 = 0xC,
181 LINKCFG2 = 0x10,
182 LINKSTATUS = 0x14,
183 LINKSTATUS1 = 0x18,
184 PHYCTRLCFG = 0x1C,
185 COMMANDSTAT = 0x20,
186};
187
188/* PHY (link-layer) configuration control */
189enum {
190 PHY_BIST_ENABLE = 0x01,
191};
192
193/*
194 * Command Header Table entry, i.e, command slot
195 * 4 Dwords per command slot, command header size == 64 Dwords.
196 */
197struct cmdhdr_tbl_entry {
198 u32 cda;
199 u32 prde_fis_len;
200 u32 ttl;
201 u32 desc_info;
202};
203
204/*
205 * Description information bitdefs
206 */
207enum {
208 VENDOR_SPECIFIC_BIST = (1 << 10),
209 CMD_DESC_SNOOP_ENABLE = (1 << 9),
210 FPDMA_QUEUED_CMD = (1 << 8),
211 SRST_CMD = (1 << 7),
212 BIST = (1 << 6),
213 ATAPI_CMD = (1 << 5),
214};
215
216/*
217 * Command Descriptor
218 */
219struct command_desc {
220 u8 cfis[8 * 4];
221 u8 sfis[8 * 4];
222 u8 acmd[4 * 4];
223 u8 fill[4 * 4];
224 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
225 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
226};
227
228/*
229 * Physical region table descriptor(PRD)
230 */
231
232struct prde {
233 u32 dba;
234 u8 fill[2 * 4];
235 u32 ddc_and_ext;
236};
237
238/*
239 * ata_port private data
240 * This is our per-port instance data.
241 */
242struct sata_fsl_port_priv {
243 struct cmdhdr_tbl_entry *cmdslot;
244 dma_addr_t cmdslot_paddr;
245 struct command_desc *cmdentry;
246 dma_addr_t cmdentry_paddr;
247
248 /*
249 * SATA FSL controller has a Status FIS which should contain the
250 * received D2H FIS & taskfile registers. This SFIS is present in
251 * the command descriptor, and to have a ready reference to it,
252 * we are caching it here, quite similar to what is done in H/W on
253 * AHCI compliant devices by copying taskfile fields to a 32-bit
254 * register.
255 */
256
257 struct ata_taskfile tf;
258};
259
260/*
261 * ata_port->host_set private data
262 */
263struct sata_fsl_host_priv {
264 void __iomem *hcr_base;
265 void __iomem *ssr_base;
266 void __iomem *csr_base;
267};
268
269static inline unsigned int sata_fsl_tag(unsigned int tag,
270 void __iomem * hcr_base)
271{
272 /* We let libATA core do actual (queue) tag allocation */
273
274 /* all non NCQ/queued commands should have tag#0 */
275 if (ata_tag_internal(tag)) {
276 DPRINTK("mapping internal cmds to tag#0\n");
277 return 0;
278 }
279
280 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
281 DPRINTK("tag %d invalid : out of range\n", tag);
282 return 0;
283 }
284
285 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
286 DPRINTK("tag %d invalid : in use!!\n", tag);
287 return 0;
288 }
289
290 return tag;
291}
292
293static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
294 unsigned int tag, u32 desc_info,
295 u32 data_xfer_len, u8 num_prde,
296 u8 fis_len)
297{
298 dma_addr_t cmd_descriptor_address;
299
300 cmd_descriptor_address = pp->cmdentry_paddr +
301 tag * SATA_FSL_CMD_DESC_SIZE;
302
303 /* NOTE: both data_xfer_len & fis_len are Dword counts */
304
305 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
306 pp->cmdslot[tag].prde_fis_len =
307 cpu_to_le32((num_prde << 16) | (fis_len << 2));
308 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
309 pp->cmdslot[tag].desc_info = cpu_to_le32((desc_info | (tag & 0x1F)));
310
311 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
312 pp->cmdslot[tag].cda,
313 pp->cmdslot[tag].prde_fis_len,
314 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
315
316}
317
318static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
319 u32 * ttl, dma_addr_t cmd_desc_paddr)
320{
321 struct scatterlist *sg;
322 unsigned int num_prde = 0;
323 u32 ttl_dwords = 0;
324
325 /*
326 * NOTE : direct & indirect prdt's are contigiously allocated
327 */
328 struct prde *prd = (struct prde *)&((struct command_desc *)
329 cmd_desc)->prdt;
330
331 struct prde *prd_ptr_to_indirect_ext = NULL;
332 unsigned indirect_ext_segment_sz = 0;
333 dma_addr_t indirect_ext_segment_paddr;
334
335 VPRINTK("SATA FSL : cd = 0x%x, prd = 0x%x\n", cmd_desc, prd);
336
337 indirect_ext_segment_paddr = cmd_desc_paddr +
338 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
339
340 ata_for_each_sg(sg, qc) {
341 dma_addr_t sg_addr = sg_dma_address(sg);
342 u32 sg_len = sg_dma_len(sg);
343
344 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n",
345 sg_addr, sg_len);
346
347 /* warn if each s/g element is not dword aligned */
348 if (sg_addr & 0x03)
349 ata_port_printk(qc->ap, KERN_ERR,
350 "s/g addr unaligned : 0x%x\n", sg_addr);
351 if (sg_len & 0x03)
352 ata_port_printk(qc->ap, KERN_ERR,
353 "s/g len unaligned : 0x%x\n", sg_len);
354
355 if ((num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1)) &&
356 !ata_sg_is_last(sg, qc)) {
357 VPRINTK("setting indirect prde\n");
358 prd_ptr_to_indirect_ext = prd;
359 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
360 indirect_ext_segment_sz = 0;
361 ++prd;
362 ++num_prde;
363 }
364
365 ttl_dwords += sg_len;
366 prd->dba = cpu_to_le32(sg_addr);
367 prd->ddc_and_ext =
368 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03));
369
370 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
371 ttl_dwords, prd->dba, prd->ddc_and_ext);
372
373 ++num_prde;
374 ++prd;
375 if (prd_ptr_to_indirect_ext)
376 indirect_ext_segment_sz += sg_len;
377 }
378
379 if (prd_ptr_to_indirect_ext) {
380 /* set indirect extension flag along with indirect ext. size */
381 prd_ptr_to_indirect_ext->ddc_and_ext =
382 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
383 DATA_SNOOP_ENABLE |
384 (indirect_ext_segment_sz & ~0x03)));
385 }
386
387 *ttl = ttl_dwords;
388 return num_prde;
389}
390
391static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
392{
393 struct ata_port *ap = qc->ap;
394 struct sata_fsl_port_priv *pp = ap->private_data;
395 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
396 void __iomem *hcr_base = host_priv->hcr_base;
397 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
398 struct command_desc *cd;
399 u32 desc_info = CMD_DESC_SNOOP_ENABLE;
400 u32 num_prde = 0;
401 u32 ttl_dwords = 0;
402 dma_addr_t cd_paddr;
403
404 cd = (struct command_desc *)pp->cmdentry + tag;
405 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
406
407 ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) & cd->cfis);
408
409 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
410 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
411
412 if (qc->tf.protocol == ATA_PROT_NCQ) {
413 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
414 cd->cfis[3], cd->cfis[11]);
415 }
416
417 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
418 if (is_atapi_taskfile(&qc->tf)) {
419 desc_info |= ATAPI_CMD;
420 memset((void *)&cd->acmd, 0, 32);
421 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
422 }
423
424 if (qc->flags & ATA_QCFLAG_DMAMAP)
425 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
426 &ttl_dwords, cd_paddr);
427
428 if (qc->tf.protocol == ATA_PROT_NCQ)
429 desc_info |= FPDMA_QUEUED_CMD;
430
431 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
432 num_prde, 5);
433
434 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
435 desc_info, ttl_dwords, num_prde);
436}
437
438static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
439{
440 struct ata_port *ap = qc->ap;
441 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
442 void __iomem *hcr_base = host_priv->hcr_base;
443 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
444
445 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
446 ioread32(CQ + hcr_base),
447 ioread32(CA + hcr_base),
448 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
449
450 /* Simply queue command to the controller/device */
451 iowrite32(1 << tag, CQ + hcr_base);
452
453 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
454 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
455
456 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
457 ioread32(CE + hcr_base),
458 ioread32(DE + hcr_base),
459 ioread32(CC + hcr_base), ioread32(COMMANDSTAT + csr_base));
460
461 return 0;
462}
463
464static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in,
465 u32 val)
466{
467 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
468 void __iomem *ssr_base = host_priv->ssr_base;
469 unsigned int sc_reg;
470
471 switch (sc_reg_in) {
472 case SCR_STATUS:
473 sc_reg = 0;
474 break;
475 case SCR_ERROR:
476 sc_reg = 1;
477 break;
478 case SCR_CONTROL:
479 sc_reg = 2;
480 break;
481 case SCR_ACTIVE:
482 sc_reg = 3;
483 break;
484 default:
485 return -EINVAL;
486 }
487
488 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
489
490 iowrite32(val, (void __iomem *)ssr_base + (sc_reg * 4));
491 return 0;
492}
493
494static int sata_fsl_scr_read(struct ata_port *ap, unsigned int sc_reg_in,
495 u32 *val)
496{
497 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
498 void __iomem *ssr_base = host_priv->ssr_base;
499 unsigned int sc_reg;
500
501 switch (sc_reg_in) {
502 case SCR_STATUS:
503 sc_reg = 0;
504 break;
505 case SCR_ERROR:
506 sc_reg = 1;
507 break;
508 case SCR_CONTROL:
509 sc_reg = 2;
510 break;
511 case SCR_ACTIVE:
512 sc_reg = 3;
513 break;
514 default:
515 return -EINVAL;
516 }
517
518 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
519
520 *val = ioread32((void __iomem *)ssr_base + (sc_reg * 4));
521 return 0;
522}
523
524static void sata_fsl_freeze(struct ata_port *ap)
525{
526 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
527 void __iomem *hcr_base = host_priv->hcr_base;
528 u32 temp;
529
530 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
531 ioread32(CQ + hcr_base),
532 ioread32(CA + hcr_base),
533 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
534 VPRINTK("CmdStat = 0x%x\n", ioread32(csr_base + COMMANDSTAT));
535
536 /* disable interrupts on the controller/port */
537 temp = ioread32(hcr_base + HCONTROL);
538 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
539
540 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
541 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
542}
543
544static void sata_fsl_thaw(struct ata_port *ap)
545{
546 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
547 void __iomem *hcr_base = host_priv->hcr_base;
548 u32 temp;
549
550 /* ack. any pending IRQs for this controller/port */
551 temp = ioread32(hcr_base + HSTATUS);
552
553 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
554
555 if (temp & 0x3F)
556 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
557
558 /* enable interrupts on the controller/port */
559 temp = ioread32(hcr_base + HCONTROL);
560 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
561
562 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
563 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
564}
565
566/*
567 * NOTE : 1st D2H FIS from device does not update sfis in command descriptor.
568 */
569static inline void sata_fsl_cache_taskfile_from_d2h_fis(struct ata_queued_cmd
570 *qc,
571 struct ata_port *ap)
572{
573 struct sata_fsl_port_priv *pp = ap->private_data;
574 u8 fis[6 * 4];
575 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
576 void __iomem *hcr_base = host_priv->hcr_base;
577 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
578 struct command_desc *cd;
579
580 cd = pp->cmdentry + tag;
581
582 memcpy(fis, &cd->sfis, 6 * 4); /* should we use memcpy_from_io() */
583 ata_tf_from_fis(fis, &pp->tf);
584}
585
586static u8 sata_fsl_check_status(struct ata_port *ap)
587{
588 struct sata_fsl_port_priv *pp = ap->private_data;
589
590 return pp->tf.command;
591}
592
593static void sata_fsl_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
594{
595 struct sata_fsl_port_priv *pp = ap->private_data;
596
597 *tf = pp->tf;
598}
599
600static int sata_fsl_port_start(struct ata_port *ap)
601{
602 struct device *dev = ap->host->dev;
603 struct sata_fsl_port_priv *pp;
604 int retval;
605 void *mem;
606 dma_addr_t mem_dma;
607 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
608 void __iomem *hcr_base = host_priv->hcr_base;
609 u32 temp;
610
611 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
612 if (!pp)
613 return -ENOMEM;
614
615 /*
616 * allocate per command dma alignment pad buffer, which is used
617 * internally by libATA to ensure that all transfers ending on
618 * unaligned boundaries are padded, to align on Dword boundaries
619 */
620 retval = ata_pad_alloc(ap, dev);
621 if (retval) {
622 kfree(pp);
623 return retval;
624 }
625
626 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
627 GFP_KERNEL);
628 if (!mem) {
629 ata_pad_free(ap, dev);
630 kfree(pp);
631 return -ENOMEM;
632 }
633 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
634
635 pp->cmdslot = mem;
636 pp->cmdslot_paddr = mem_dma;
637
638 mem += SATA_FSL_CMD_SLOT_SIZE;
639 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
640
641 pp->cmdentry = mem;
642 pp->cmdentry_paddr = mem_dma;
643
644 ap->private_data = pp;
645
646 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
647 pp->cmdslot_paddr, pp->cmdentry_paddr);
648
649 /* Now, update the CHBA register in host controller cmd register set */
650 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
651
652 /*
653 * Now, we can bring the controller on-line & also initiate
654 * the COMINIT sequence, we simply return here and the boot-probing
655 * & device discovery process is re-initiated by libATA using a
656 * Softreset EH (dummy) session. Hence, boot probing and device
657 * discovey will be part of sata_fsl_softreset() callback.
658 */
659
660 temp = ioread32(hcr_base + HCONTROL);
661 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
662
663 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
664 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
665 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
666
667 /*
668 * Workaround for 8315DS board 3gbps link-up issue,
669 * currently limit SATA port to GEN1 speed
670 */
671 sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
672 temp &= ~(0xF << 4);
673 temp |= (0x1 << 4);
674 sata_fsl_scr_write(ap, SCR_CONTROL, temp);
675
676 sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
677 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n",
678 temp);
679
680 return 0;
681}
682
683static void sata_fsl_port_stop(struct ata_port *ap)
684{
685 struct device *dev = ap->host->dev;
686 struct sata_fsl_port_priv *pp = ap->private_data;
687 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
688 void __iomem *hcr_base = host_priv->hcr_base;
689 u32 temp;
690
691 /*
692 * Force host controller to go off-line, aborting current operations
693 */
694 temp = ioread32(hcr_base + HCONTROL);
695 temp &= ~HCONTROL_ONLINE_PHY_RST;
696 temp |= HCONTROL_FORCE_OFFLINE;
697 iowrite32(temp, hcr_base + HCONTROL);
698
699 /* Poll for controller to go offline - should happen immediately */
700 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
701
702 ap->private_data = NULL;
703 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
704 pp->cmdslot, pp->cmdslot_paddr);
705
706 ata_pad_free(ap, dev);
707 kfree(pp);
708}
709
710static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
711{
712 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
713 void __iomem *hcr_base = host_priv->hcr_base;
714 struct ata_taskfile tf;
715 u32 temp;
716
717 temp = ioread32(hcr_base + SIGNATURE);
718
719 VPRINTK("raw sig = 0x%x\n", temp);
720 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
721 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
722
723 tf.lbah = (temp >> 24) & 0xff;
724 tf.lbam = (temp >> 16) & 0xff;
725 tf.lbal = (temp >> 8) & 0xff;
726 tf.nsect = temp & 0xff;
727
728 return ata_dev_classify(&tf);
729}
730
731static int sata_fsl_softreset(struct ata_port *ap, unsigned int *class,
732 unsigned long deadline)
733{
734 struct sata_fsl_port_priv *pp = ap->private_data;
735 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
736 void __iomem *hcr_base = host_priv->hcr_base;
737 u32 temp;
738 struct ata_taskfile tf;
739 u8 *cfis;
740 u32 Serror;
741 int i = 0;
742 struct ata_queued_cmd qc;
743 u8 *buf;
744 dma_addr_t dma_address;
745 struct scatterlist *sg;
746 unsigned long start_jiffies;
747
748 DPRINTK("in xx_softreset\n");
749
750try_offline_again:
751 /*
752 * Force host controller to go off-line, aborting current operations
753 */
754 temp = ioread32(hcr_base + HCONTROL);
755 temp &= ~HCONTROL_ONLINE_PHY_RST;
756 iowrite32(temp, hcr_base + HCONTROL);
757
758 /* Poll for controller to go offline */
759 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500);
760
761 if (temp & ONLINE) {
762 ata_port_printk(ap, KERN_ERR,
763 "Softreset failed, not off-lined %d\n", i);
764
765 /*
766 * Try to offline controller atleast twice
767 */
768 i++;
769 if (i == 2)
770 goto err;
771 else
772 goto try_offline_again;
773 }
774
775 DPRINTK("softreset, controller off-lined\n");
776 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
777 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
778
779 /*
780 * PHY reset should remain asserted for atleast 1ms
781 */
782 msleep(1);
783
784 /*
785 * Now, bring the host controller online again, this can take time
786 * as PHY reset and communication establishment, 1st D2H FIS and
787 * device signature update is done, on safe side assume 500ms
788 * NOTE : Host online status may be indicated immediately!!
789 */
790
791 temp = ioread32(hcr_base + HCONTROL);
792 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
793 iowrite32(temp, hcr_base + HCONTROL);
794
795 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500);
796
797 if (!(temp & ONLINE)) {
798 ata_port_printk(ap, KERN_ERR,
799 "Softreset failed, not on-lined\n");
800 goto err;
801 }
802
803 DPRINTK("softreset, controller off-lined & on-lined\n");
804 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
805 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
806
807 /*
808 * First, wait for the PHYRDY change to occur before waiting for
809 * the signature, and also verify if SStatus indicates device
810 * presence
811 */
812
813 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500);
814 if ((!(temp & 0x10)) || ata_port_offline(ap)) {
815 ata_port_printk(ap, KERN_WARNING,
816 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
817 ioread32(hcr_base + HSTATUS));
818 goto err;
819 }
820
821 /*
822 * Wait for the first D2H from device,i.e,signature update notification
823 */
824 start_jiffies = jiffies;
825 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10,
826 500, jiffies_to_msecs(deadline - start_jiffies));
827
828 if ((temp & 0xFF) != 0x18) {
829 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
830 goto err;
831 } else {
832 ata_port_printk(ap, KERN_INFO,
833 "Signature Update detected @ %d msecs\n",
834 jiffies_to_msecs(jiffies - start_jiffies));
835 }
836
837 /*
838 * Send a device reset (SRST) explicitly on command slot #0
839 * Check : will the command queue (reg) be cleared during offlining ??
840 * Also we will be online only if Phy commn. has been established
841 * and device presence has been detected, therefore if we have
842 * reached here, we can send a command to the target device
843 */
844
845 if (ap->sactive)
846 goto skip_srst_do_ncq_error_handling;
847
848 DPRINTK("Sending SRST/device reset\n");
849
850 ata_tf_init(ap->device, &tf);
851 cfis = (u8 *) & pp->cmdentry->cfis;
852
853 /* device reset/SRST is a control register update FIS, uses tag0 */
854 sata_fsl_setup_cmd_hdr_entry(pp, 0,
855 SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
856
857 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
858 ata_tf_to_fis(&tf, 0, 0, cfis);
859
860 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
861 cfis[0], cfis[1], cfis[2], cfis[3]);
862
863 /*
864 * Queue SRST command to the controller/device, ensure that no
865 * other commands are active on the controller/device
866 */
867
868 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
869 ioread32(CQ + hcr_base),
870 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
871
872 iowrite32(0xFFFF, CC + hcr_base);
873 iowrite32(1, CQ + hcr_base);
874
875 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
876 if (temp & 0x1) {
877 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
878
879 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
880 ioread32(CQ + hcr_base),
881 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
882
883 sata_fsl_scr_read(ap, SCR_ERROR, &Serror);
884
885 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
886 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
887 DPRINTK("Serror = 0x%x\n", Serror);
888 goto err;
889 }
890
891 msleep(1);
892
893 /*
894 * SATA device enters reset state after receving a Control register
895 * FIS with SRST bit asserted and it awaits another H2D Control reg.
896 * FIS with SRST bit cleared, then the device does internal diags &
897 * initialization, followed by indicating it's initialization status
898 * using ATA signature D2H register FIS to the host controller.
899 */
900
901 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
902
903 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
904 ata_tf_to_fis(&tf, 0, 0, cfis);
905
906 iowrite32(1, CQ + hcr_base);
907 msleep(150); /* ?? */
908
909 /*
910 * The above command would have signalled an interrupt on command
911 * complete, which needs special handling, by clearing the Nth
912 * command bit of the CCreg
913 */
914 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
915 goto check_device_signature;
916
917skip_srst_do_ncq_error_handling:
918
919 VPRINTK("Sending read log ext(10h) command\n");
920
921 memset(&qc, 0, sizeof(struct ata_queued_cmd));
922 ata_tf_init(ap->device, &tf);
923
924 tf.command = ATA_CMD_READ_LOG_EXT;
925 tf.lbal = ATA_LOG_SATA_NCQ;
926 tf.nsect = 1;
927 tf.hob_nsect = 0;
928 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_LBA48 | ATA_TFLAG_DEVICE;
929 tf.protocol = ATA_PROT_PIO;
930
931 qc.tag = ATA_TAG_INTERNAL;
932 qc.scsicmd = NULL;
933 qc.ap = ap;
934 qc.dev = ap->device;
935
936 qc.tf = tf;
937 qc.flags |= ATA_QCFLAG_RESULT_TF;
938 qc.dma_dir = DMA_FROM_DEVICE;
939
940 buf = ap->sector_buf;
941 ata_sg_init_one(&qc, buf, 1 * ATA_SECT_SIZE);
942
943 /*
944 * Need to DMA-map the memory buffer associated with the command
945 */
946
947 sg = qc.__sg;
948 dma_address = dma_map_single(ap->dev, qc.buf_virt,
949 sg->length, DMA_FROM_DEVICE);
950
951 sg_dma_address(sg) = dma_address;
952 sg_dma_len(sg) = sg->length;
953
954 VPRINTK("EH, addr = 0x%x, len = 0x%x\n", dma_address, sg->length);
955
956 sata_fsl_qc_prep(&qc);
957 sata_fsl_qc_issue(&qc);
958
959 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
960 if (temp & 0x1) {
961 VPRINTK("READ_LOG_EXT_10H issue failed\n");
962
963 VPRINTK("READ_LOG@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
964 ioread32(CQ + hcr_base),
965 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
966
967 sata_fsl_scr_read(ap, SCR_ERROR, &Serror);
968
969 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
970 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
971 VPRINTK("Serror = 0x%x\n", Serror);
972 goto err;
973 }
974
975 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
976
977 check_device_signature:
978
979 DPRINTK("SATA FSL : Now checking device signature\n");
980
981 *class = ATA_DEV_NONE;
982
983 /* Verify if SStatus indicates device presence */
984 if (ata_port_online(ap)) {
985 /*
986 * if we are here, device presence has been detected,
987 * 1st D2H FIS would have been received, but sfis in
988 * command desc. is not updated, but signature register
989 * would have been updated
990 */
991
992 *class = sata_fsl_dev_classify(ap);
993
994 DPRINTK("class = %d\n", *class);
995 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
996 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
997 }
998
999 return 0;
1000
1001err:
1002 return -EIO;
1003}
1004
1005static int sata_fsl_hardreset(struct ata_port *ap, unsigned int *class,
1006 unsigned long deadline)
1007{
1008 int retval;
1009
1010 retval = sata_std_hardreset(ap, class, deadline);
1011
1012 DPRINTK("SATA FSL : in xx_hardreset, retval = 0x%d\n", retval);
1013
1014 return retval;
1015}
1016
1017static void sata_fsl_error_handler(struct ata_port *ap)
1018{
1019
1020 DPRINTK("in xx_error_handler\n");
1021
1022 /* perform recovery */
1023 ata_do_eh(ap, ata_std_prereset, sata_fsl_softreset, sata_fsl_hardreset,
1024 ata_std_postreset);
1025}
1026
1027static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1028{
1029 if (qc->flags & ATA_QCFLAG_FAILED)
1030 qc->err_mask |= AC_ERR_OTHER;
1031
1032 if (qc->err_mask) {
1033 /* make DMA engine forget about the failed command */
1034
1035 }
1036}
1037
1038static void sata_fsl_irq_clear(struct ata_port *ap)
1039{
1040 /* unused */
1041}
1042
1043static void sata_fsl_error_intr(struct ata_port *ap)
1044{
1045 struct ata_eh_info *ehi = &ap->eh_info;
1046 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1047 void __iomem *hcr_base = host_priv->hcr_base;
1048 u32 hstatus, dereg, cereg = 0, SError = 0;
1049 unsigned int err_mask = 0, action = 0;
1050 struct ata_queued_cmd *qc;
1051 int freeze = 0;
1052
1053 hstatus = ioread32(hcr_base + HSTATUS);
1054 cereg = ioread32(hcr_base + CE);
1055
1056 ata_ehi_clear_desc(ehi);
1057
1058 /*
1059 * Handle & Clear SError
1060 */
1061
1062 sata_fsl_scr_read(ap, SCR_ERROR, &SError);
1063 if (unlikely(SError & 0xFFFF0000)) {
1064 sata_fsl_scr_write(ap, SCR_ERROR, SError);
1065 err_mask |= AC_ERR_ATA_BUS;
1066 }
1067
1068 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1069 hstatus, cereg, ioread32(hcr_base + DE), SError);
1070
1071 /* handle single device errors */
1072 if (cereg) {
1073 /*
1074 * clear the command error, also clears queue to the device
1075 * in error, and we can (re)issue commands to this device.
1076 * When a device is in error all commands queued into the
1077 * host controller and at the device are considered aborted
1078 * and the queue for that device is stopped. Now, after
1079 * clearing the device error, we can issue commands to the
1080 * device to interrogate it to find the source of the error.
1081 */
1082 dereg = ioread32(hcr_base + DE);
1083 iowrite32(dereg, hcr_base + DE);
1084 iowrite32(cereg, hcr_base + CE);
1085
1086 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1087 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1088 /*
1089 * We should consider this as non fatal error, and TF must
1090 * be updated as done below.
1091 */
1092
1093 err_mask |= AC_ERR_DEV;
1094 }
1095
1096 /* handle fatal errors */
1097 if (hstatus & FATAL_ERROR_DECODE) {
1098 err_mask |= AC_ERR_ATA_BUS;
1099 action |= ATA_EH_SOFTRESET;
1100 /* how will fatal error interrupts be completed ?? */
1101 freeze = 1;
1102 }
1103
1104 /* Handle PHYRDY change notification */
1105 if (hstatus & INT_ON_PHYRDY_CHG) {
1106 DPRINTK("SATA FSL: PHYRDY change indication\n");
1107
1108 /* Setup a soft-reset EH action */
1109 ata_ehi_hotplugged(ehi);
1110 freeze = 1;
1111 }
1112
1113 /* record error info */
1114 qc = ata_qc_from_tag(ap, ap->active_tag);
1115
1116 if (qc) {
1117 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap);
1118 qc->err_mask |= err_mask;
1119 } else
1120 ehi->err_mask |= err_mask;
1121
1122 ehi->action |= action;
1123 ehi->serror |= SError;
1124
1125 /* freeze or abort */
1126 if (freeze)
1127 ata_port_freeze(ap);
1128 else
1129 ata_port_abort(ap);
1130}
1131
1132static void sata_fsl_qc_complete(struct ata_queued_cmd *qc)
1133{
1134 if (qc->flags & ATA_QCFLAG_RESULT_TF) {
1135 DPRINTK("xx_qc_complete called\n");
1136 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap);
1137 }
1138}
1139
1140static void sata_fsl_host_intr(struct ata_port *ap)
1141{
1142 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1143 void __iomem *hcr_base = host_priv->hcr_base;
1144 u32 hstatus, qc_active = 0;
1145 struct ata_queued_cmd *qc;
1146 u32 SError;
1147
1148 hstatus = ioread32(hcr_base + HSTATUS);
1149
1150 sata_fsl_scr_read(ap, SCR_ERROR, &SError);
1151
1152 if (unlikely(SError & 0xFFFF0000)) {
1153 DPRINTK("serror @host_intr : 0x%x\n", SError);
1154 sata_fsl_error_intr(ap);
1155
1156 }
1157
1158 if (unlikely(hstatus & INT_ON_ERROR)) {
1159 DPRINTK("error interrupt!!\n");
1160 sata_fsl_error_intr(ap);
1161 return;
1162 }
1163
1164 if (ap->sactive) { /* only true for NCQ commands */
1165 int i;
1166 /* Read command completed register */
1167 qc_active = ioread32(hcr_base + CC);
1168 /* clear CC bit, this will also complete the interrupt */
1169 iowrite32(qc_active, hcr_base + CC);
1170
1171 DPRINTK("Status of all queues :\n");
1172 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1173 qc_active, ioread32(hcr_base + CA),
1174 ioread32(hcr_base + CE));
1175
1176 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1177 if (qc_active & (1 << i)) {
1178 qc = ata_qc_from_tag(ap, i);
1179 if (qc) {
1180 sata_fsl_qc_complete(qc);
1181 ata_qc_complete(qc);
1182 }
1183 DPRINTK
1184 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1185 i, ioread32(hcr_base + CC),
1186 ioread32(hcr_base + CA));
1187 }
1188 }
1189 return;
1190
1191 } else if (ap->qc_active) {
1192 iowrite32(1, hcr_base + CC);
1193 qc = ata_qc_from_tag(ap, ap->active_tag);
1194
1195 DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n",
1196 ap->active_tag, ioread32(hcr_base + CC));
1197
1198 if (qc) {
1199 sata_fsl_qc_complete(qc);
1200 ata_qc_complete(qc);
1201 }
1202 } else {
1203 /* Spurious Interrupt!! */
1204 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1205 ioread32(hcr_base + CC));
1206 return;
1207 }
1208}
1209
1210static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1211{
1212 struct ata_host *host = dev_instance;
1213 struct sata_fsl_host_priv *host_priv = host->private_data;
1214 void __iomem *hcr_base = host_priv->hcr_base;
1215 u32 interrupt_enables;
1216 unsigned handled = 0;
1217 struct ata_port *ap;
1218
1219 /* ack. any pending IRQs for this controller/port */
1220 interrupt_enables = ioread32(hcr_base + HSTATUS);
1221 interrupt_enables &= 0x3F;
1222
1223 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1224
1225 if (!interrupt_enables)
1226 return IRQ_NONE;
1227
1228 spin_lock(&host->lock);
1229
1230 /* Assuming one port per host controller */
1231
1232 ap = host->ports[0];
1233 if (ap) {
1234 sata_fsl_host_intr(ap);
1235 } else {
1236 dev_printk(KERN_WARNING, host->dev,
1237 "interrupt on disabled port 0\n");
1238 }
1239
1240 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1241 handled = 1;
1242
1243 spin_unlock(&host->lock);
1244
1245 return IRQ_RETVAL(handled);
1246}
1247
1248/*
1249 * Multiple ports are represented by multiple SATA controllers with
1250 * one port per controller
1251 */
1252static int sata_fsl_init_controller(struct ata_host *host)
1253{
1254 struct sata_fsl_host_priv *host_priv = host->private_data;
1255 void __iomem *hcr_base = host_priv->hcr_base;
1256 u32 temp;
1257
1258 /*
1259 * NOTE : We cannot bring the controller online before setting
1260 * the CHBA, hence main controller initialization is done as
1261 * part of the port_start() callback
1262 */
1263
1264 /* ack. any pending IRQs for this controller/port */
1265 temp = ioread32(hcr_base + HSTATUS);
1266 if (temp & 0x3F)
1267 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1268
1269 /* Keep interrupts disabled on the controller */
1270 temp = ioread32(hcr_base + HCONTROL);
1271 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1272
1273 /* Disable interrupt coalescing control(icc), for the moment */
1274 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1275 iowrite32(0x01000000, hcr_base + ICC);
1276
1277 /* clear error registers, SError is cleared by libATA */
1278 iowrite32(0x00000FFFF, hcr_base + CE);
1279 iowrite32(0x00000FFFF, hcr_base + DE);
1280
1281 /* initially assuming no Port multiplier, set CQPMP to 0 */
1282 iowrite32(0x0, hcr_base + CQPMP);
1283
1284 /*
1285 * host controller will be brought on-line, during xx_port_start()
1286 * callback, that should also initiate the OOB, COMINIT sequence
1287 */
1288
1289 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1290 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1291
1292 return 0;
1293}
1294
1295/*
1296 * scsi mid-layer and libata interface structures
1297 */
1298static struct scsi_host_template sata_fsl_sht = {
1299 .module = THIS_MODULE,
1300 .name = "sata_fsl",
1301 .ioctl = ata_scsi_ioctl,
1302 .queuecommand = ata_scsi_queuecmd,
1303 .change_queue_depth = ata_scsi_change_queue_depth,
1304 .can_queue = SATA_FSL_QUEUE_DEPTH,
1305 .this_id = ATA_SHT_THIS_ID,
1306 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1307 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
1308 .emulated = ATA_SHT_EMULATED,
1309 .use_clustering = ATA_SHT_USE_CLUSTERING,
1310 .proc_name = "sata_fsl",
1311 .dma_boundary = ATA_DMA_BOUNDARY,
1312 .slave_configure = ata_scsi_slave_config,
1313 .slave_destroy = ata_scsi_slave_destroy,
1314 .bios_param = ata_std_bios_param,
1315#ifdef CONFIG_PM
1316 .suspend = ata_scsi_device_suspend,
1317 .resume = ata_scsi_device_resume,
1318#endif
1319};
1320
1321static const struct ata_port_operations sata_fsl_ops = {
1322 .port_disable = ata_port_disable,
1323
1324 .check_status = sata_fsl_check_status,
1325 .check_altstatus = sata_fsl_check_status,
1326 .dev_select = ata_noop_dev_select,
1327
1328 .tf_read = sata_fsl_tf_read,
1329
1330 .qc_prep = sata_fsl_qc_prep,
1331 .qc_issue = sata_fsl_qc_issue,
1332 .irq_clear = sata_fsl_irq_clear,
1333 .irq_on = ata_dummy_irq_on,
1334 .irq_ack = ata_dummy_irq_ack,
1335
1336 .scr_read = sata_fsl_scr_read,
1337 .scr_write = sata_fsl_scr_write,
1338
1339 .freeze = sata_fsl_freeze,
1340 .thaw = sata_fsl_thaw,
1341 .error_handler = sata_fsl_error_handler,
1342 .post_internal_cmd = sata_fsl_post_internal_cmd,
1343
1344 .port_start = sata_fsl_port_start,
1345 .port_stop = sata_fsl_port_stop,
1346};
1347
1348static const struct ata_port_info sata_fsl_port_info[] = {
1349 {
1350 .flags = SATA_FSL_HOST_FLAGS,
1351 .pio_mask = 0x1f, /* pio 0-4 */
1352 .udma_mask = 0x7f, /* udma 0-6 */
1353 .port_ops = &sata_fsl_ops,
1354 },
1355};
1356
1357static int sata_fsl_probe(struct of_device *ofdev,
1358 const struct of_device_id *match)
1359{
1360 int retval = 0;
1361 void __iomem *hcr_base = NULL;
1362 void __iomem *ssr_base = NULL;
1363 void __iomem *csr_base = NULL;
1364 struct sata_fsl_host_priv *host_priv = NULL;
1365 struct resource *r;
1366 int irq;
1367 struct ata_host *host;
1368
1369 struct ata_port_info pi = sata_fsl_port_info[0];
1370 const struct ata_port_info *ppi[] = { &pi, NULL };
1371
1372 dev_printk(KERN_INFO, &ofdev->dev,
1373 "Sata FSL Platform/CSB Driver init\n");
1374
1375 r = kmalloc(sizeof(struct resource), GFP_KERNEL);
1376
1377 hcr_base = of_iomap(ofdev->node, 0);
1378 if (!hcr_base)
1379 goto error_exit_with_cleanup;
1380
1381 ssr_base = hcr_base + 0x100;
1382 csr_base = hcr_base + 0x140;
1383
1384 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1385 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1386 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1387
1388 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1389 if (!host_priv)
1390 goto error_exit_with_cleanup;
1391
1392 host_priv->hcr_base = hcr_base;
1393 host_priv->ssr_base = ssr_base;
1394 host_priv->csr_base = csr_base;
1395
1396 irq = irq_of_parse_and_map(ofdev->node, 0);
1397 if (irq < 0) {
1398 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n");
1399 goto error_exit_with_cleanup;
1400 }
1401
1402 /* allocate host structure */
1403 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1404
1405 /* host->iomap is not used currently */
1406 host->private_data = host_priv;
1407
1408 /* setup port(s) */
1409
1410 host->ports[0]->ioaddr.cmd_addr = host_priv->hcr_base;
1411 host->ports[0]->ioaddr.scr_addr = host_priv->ssr_base;
1412
1413 /* initialize host controller */
1414 sata_fsl_init_controller(host);
1415
1416 /*
1417 * Now, register with libATA core, this will also initiate the
1418 * device discovery process, invoking our port_start() handler &
1419 * error_handler() to execute a dummy Softreset EH session
1420 */
1421 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1422 &sata_fsl_sht);
1423
1424 dev_set_drvdata(&ofdev->dev, host);
1425
1426 return 0;
1427
1428error_exit_with_cleanup:
1429
1430 if (hcr_base)
1431 iounmap(hcr_base);
1432 if (host_priv)
1433 kfree(host_priv);
1434
1435 return retval;
1436}
1437
1438static int sata_fsl_remove(struct of_device *ofdev)
1439{
1440 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
1441 struct sata_fsl_host_priv *host_priv = host->private_data;
1442
1443 ata_host_detach(host);
1444
1445 dev_set_drvdata(&ofdev->dev, NULL);
1446
1447 irq_dispose_mapping(host->irq);
1448 iounmap(host_priv->hcr_base);
1449 kfree(host_priv);
1450
1451 return 0;
1452}
1453
1454static struct of_device_id fsl_sata_match[] = {
1455 {
1456 .compatible = "fsl,mpc8315-sata",
1457 },
1458 {
1459 .compatible = "fsl,mpc8379-sata",
1460 },
1461 {},
1462};
1463
1464MODULE_DEVICE_TABLE(of, fsl_sata_match);
1465
1466static struct of_platform_driver fsl_sata_driver = {
1467 .name = "fsl-sata",
1468 .match_table = fsl_sata_match,
1469 .probe = sata_fsl_probe,
1470 .remove = sata_fsl_remove,
1471};
1472
1473static int __init sata_fsl_init(void)
1474{
1475 of_register_platform_driver(&fsl_sata_driver);
1476 return 0;
1477}
1478
1479static void __exit sata_fsl_exit(void)
1480{
1481 of_unregister_platform_driver(&fsl_sata_driver);
1482}
1483
1484MODULE_LICENSE("GPL");
1485MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1486MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1487MODULE_VERSION("1.10");
1488
1489module_init(sata_fsl_init);
1490module_exit(sata_fsl_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 21:57:23 -0500