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authorJeff Garzik <jeff@garzik.org>2006-08-29 18:12:40 -0400
committerJeff Garzik <jeff@garzik.org>2006-08-29 18:12:40 -0400
commit669a5db411d85a14f86cd92bc16bf7ab5b8aa235 (patch)
tree8d4f9d63e18185695a4d97e1a3fa4e18b61c7345 /drivers/ata/pata_sl82c105.c
parentb01e86fee6c821e4e003fd4e9f65453ac478a58e (diff)
[libata] Add a bunch of PATA drivers.
The vast majority of drivers and changes are from Alan Cox. Albert Lee contributed and maintains pata_pdc2027x. Adrian Bunk, Andrew Morton, and Tejun Heo contributed various minor fixes and updates. Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/pata_sl82c105.c')
-rw-r--r--drivers/ata/pata_sl82c105.c388
1 files changed, 388 insertions, 0 deletions
diff --git a/drivers/ata/pata_sl82c105.c b/drivers/ata/pata_sl82c105.c
new file mode 100644
index 000000000000..47b290b5604a
--- /dev/null
+++ b/drivers/ata/pata_sl82c105.c
@@ -0,0 +1,388 @@
1/*
2 * pata_sl82c105.c - SL82C105 PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based in part on linux/drivers/ide/pci/sl82c105.c
7 * SL82C105/Winbond 553 IDE driver
8 *
9 * and in part on the documentation and errata sheet
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/pci.h>
15#include <linux/init.h>
16#include <linux/blkdev.h>
17#include <linux/delay.h>
18#include <scsi/scsi_host.h>
19#include <linux/libata.h>
20
21#define DRV_NAME "pata_sl82c105"
22#define DRV_VERSION "0.2.2"
23
24enum {
25 /*
26 * SL82C105 PCI config register 0x40 bits.
27 */
28 CTRL_IDE_IRQB = (1 << 30),
29 CTRL_IDE_IRQA = (1 << 28),
30 CTRL_LEGIRQ = (1 << 11),
31 CTRL_P1F16 = (1 << 5),
32 CTRL_P1EN = (1 << 4),
33 CTRL_P0F16 = (1 << 1),
34 CTRL_P0EN = (1 << 0)
35};
36
37/**
38 * sl82c105_pre_reset - probe begin
39 * @ap: ATA port
40 *
41 * Set up cable type and use generic probe init
42 */
43
44static int sl82c105_pre_reset(struct ata_port *ap)
45{
46 static const struct pci_bits sl82c105_enable_bits[] = {
47 { 0x40, 1, 0x01, 0x01 },
48 { 0x40, 1, 0x10, 0x10 }
49 };
50 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
51
52 if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no])) {
53 ata_port_disable(ap);
54 dev_printk(KERN_INFO, &pdev->dev, "port disabled. ignoring.\n");
55 return 0;
56 }
57 ap->cbl = ATA_CBL_PATA40;
58 return ata_std_prereset(ap);
59}
60
61
62static void sl82c105_error_handler(struct ata_port *ap)
63{
64 ata_bmdma_drive_eh(ap, sl82c105_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
65}
66
67
68/**
69 * sl82c105_configure_piomode - set chip PIO timing
70 * @ap: ATA interface
71 * @adev: ATA device
72 * @pio: PIO mode
73 *
74 * Called to do the PIO mode setup. Our timing registers are shared
75 * so a configure_dmamode call will undo any work we do here and vice
76 * versa
77 */
78
79static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
80{
81 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
82 static u16 pio_timing[5] = {
83 0x50D, 0x407, 0x304, 0x242, 0x240
84 };
85 u16 dummy;
86 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
87
88 pci_write_config_word(pdev, timing, pio_timing[pio]);
89 /* Can we lose this oddity of the old driver */
90 pci_read_config_word(pdev, timing, &dummy);
91}
92
93/**
94 * sl82c105_set_piomode - set initial PIO mode data
95 * @ap: ATA interface
96 * @adev: ATA device
97 *
98 * Called to do the PIO mode setup. Our timing registers are shared
99 * but we want to set the PIO timing by default.
100 */
101
102static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev)
103{
104 sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
105}
106
107/**
108 * sl82c105_configure_dmamode - set DMA mode in chip
109 * @ap: ATA interface
110 * @adev: ATA device
111 *
112 * Load DMA cycle times into the chip ready for a DMA transfer
113 * to occur.
114 */
115
116static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev)
117{
118 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
119 static u16 dma_timing[3] = {
120 0x707, 0x201, 0x200
121 };
122 u16 dummy;
123 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
124 int dma = adev->dma_mode - XFER_MW_DMA_0;
125
126 pci_write_config_word(pdev, timing, dma_timing[dma]);
127 /* Can we lose this oddity of the old driver */
128 pci_read_config_word(pdev, timing, &dummy);
129}
130
131/**
132 * sl82c105_set_dmamode - set initial DMA mode data
133 * @ap: ATA interface
134 * @adev: ATA device
135 *
136 * Called to do the DMA mode setup. This replaces the PIO timings
137 * for the device in question. Set appropriate PIO timings not DMA
138 * timings at this point.
139 */
140
141static void sl82c105_set_dmamode(struct ata_port *ap, struct ata_device *adev)
142{
143 switch(adev->dma_mode) {
144 case XFER_MW_DMA_0:
145 sl82c105_configure_piomode(ap, adev, 1);
146 break;
147 case XFER_MW_DMA_1:
148 sl82c105_configure_piomode(ap, adev, 3);
149 break;
150 case XFER_MW_DMA_2:
151 sl82c105_configure_piomode(ap, adev, 3);
152 break;
153 default:
154 BUG();
155 }
156}
157
158/**
159 * sl82c105_reset_engine - Reset the DMA engine
160 * @ap: ATA interface
161 *
162 * The sl82c105 has some serious problems with the DMA engine
163 * when transfers don't run as expected or ATAPI is used. The
164 * recommended fix is to reset the engine each use using a chip
165 * test register.
166 */
167
168static void sl82c105_reset_engine(struct ata_port *ap)
169{
170 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
171 u16 val;
172
173 pci_read_config_word(pdev, 0x7E, &val);
174 pci_write_config_word(pdev, 0x7E, val | 4);
175 pci_write_config_word(pdev, 0x7E, val & ~4);
176}
177
178/**
179 * sl82c105_bmdma_start - DMA engine begin
180 * @qc: ATA command
181 *
182 * Reset the DMA engine each use as recommended by the errata
183 * document.
184 *
185 * FIXME: if we switch clock at BMDMA start/end we might get better
186 * PIO performance on DMA capable devices.
187 */
188
189static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
190{
191 struct ata_port *ap = qc->ap;
192
193 sl82c105_reset_engine(ap);
194
195 /* Set the clocks for DMA */
196 sl82c105_configure_dmamode(ap, qc->dev);
197 /* Activate DMA */
198 ata_bmdma_start(qc);
199}
200
201/**
202 * sl82c105_bmdma_end - DMA engine stop
203 * @qc: ATA command
204 *
205 * Reset the DMA engine each use as recommended by the errata
206 * document.
207 *
208 * This function is also called to turn off DMA when a timeout occurs
209 * during DMA operation. In both cases we need to reset the engine,
210 * so no actual eng_timeout handler is required.
211 *
212 * We assume bmdma_stop is always called if bmdma_start as called. If
213 * not then we may need to wrap qc_issue.
214 */
215
216static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
217{
218 struct ata_port *ap = qc->ap;
219
220 ata_bmdma_stop(qc);
221 sl82c105_reset_engine(ap);
222
223 /* This will redo the initial setup of the DMA device to matching
224 PIO timings */
225 sl82c105_set_dmamode(ap, qc->dev);
226}
227
228static struct scsi_host_template sl82c105_sht = {
229 .module = THIS_MODULE,
230 .name = DRV_NAME,
231 .ioctl = ata_scsi_ioctl,
232 .queuecommand = ata_scsi_queuecmd,
233 .can_queue = ATA_DEF_QUEUE,
234 .this_id = ATA_SHT_THIS_ID,
235 .sg_tablesize = LIBATA_MAX_PRD,
236 .max_sectors = ATA_MAX_SECTORS,
237 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
238 .emulated = ATA_SHT_EMULATED,
239 .use_clustering = ATA_SHT_USE_CLUSTERING,
240 .proc_name = DRV_NAME,
241 .dma_boundary = ATA_DMA_BOUNDARY,
242 .slave_configure = ata_scsi_slave_config,
243 .bios_param = ata_std_bios_param,
244};
245
246static struct ata_port_operations sl82c105_port_ops = {
247 .port_disable = ata_port_disable,
248 .set_piomode = sl82c105_set_piomode,
249 .set_dmamode = sl82c105_set_dmamode,
250 .mode_filter = ata_pci_default_filter,
251
252 .tf_load = ata_tf_load,
253 .tf_read = ata_tf_read,
254 .check_status = ata_check_status,
255 .exec_command = ata_exec_command,
256 .dev_select = ata_std_dev_select,
257
258 .error_handler = sl82c105_error_handler,
259
260 .bmdma_setup = ata_bmdma_setup,
261 .bmdma_start = sl82c105_bmdma_start,
262 .bmdma_stop = sl82c105_bmdma_stop,
263 .bmdma_status = ata_bmdma_status,
264
265 .qc_prep = ata_qc_prep,
266 .qc_issue = ata_qc_issue_prot,
267 .eng_timeout = ata_eng_timeout,
268 .data_xfer = ata_pio_data_xfer,
269
270 .irq_handler = ata_interrupt,
271 .irq_clear = ata_bmdma_irq_clear,
272
273 .port_start = ata_port_start,
274 .port_stop = ata_port_stop,
275 .host_stop = ata_host_stop
276};
277
278/**
279 * sl82c105_bridge_revision - find bridge version
280 * @pdev: PCI device for the ATA function
281 *
282 * Locates the PCI bridge associated with the ATA function and
283 * providing it is a Winbond 553 reports the revision. If it cannot
284 * find a revision or the right device it returns -1
285 */
286
287static int sl82c105_bridge_revision(struct pci_dev *pdev)
288{
289 struct pci_dev *bridge;
290 u8 rev;
291
292 /*
293 * The bridge should be part of the same device, but function 0.
294 */
295 bridge = pci_get_slot(pdev->bus,
296 PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
297 if (!bridge)
298 return -1;
299
300 /*
301 * Make sure it is a Winbond 553 and is an ISA bridge.
302 */
303 if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
304 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
305 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
306 pci_dev_put(bridge);
307 return -1;
308 }
309 /*
310 * We need to find function 0's revision, not function 1
311 */
312 pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
313
314 pci_dev_put(bridge);
315 return rev;
316}
317
318
319static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
320{
321 static struct ata_port_info info_dma = {
322 .sht = &sl82c105_sht,
323 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
324 .pio_mask = 0x1f,
325 .mwdma_mask = 0x07,
326 .port_ops = &sl82c105_port_ops
327 };
328 static struct ata_port_info info_early = {
329 .sht = &sl82c105_sht,
330 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
331 .pio_mask = 0x1f,
332 .port_ops = &sl82c105_port_ops
333 };
334 static struct ata_port_info *port_info[2] = { &info_early, &info_early };
335 u32 val;
336 int rev;
337
338 rev = sl82c105_bridge_revision(dev);
339
340 if (rev == -1)
341 dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n");
342 else if (rev <= 5)
343 dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n");
344 else {
345 port_info[0] = &info_dma;
346 port_info[1] = &info_dma;
347 }
348
349 pci_read_config_dword(dev, 0x40, &val);
350 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
351 pci_write_config_dword(dev, 0x40, val);
352
353
354 return ata_pci_init_one(dev, port_info, 1); /* For now */
355}
356
357static struct pci_device_id sl82c105[] = {
358 { PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },
359 { 0, },
360};
361
362static struct pci_driver sl82c105_pci_driver = {
363 .name = DRV_NAME,
364 .id_table = sl82c105,
365 .probe = sl82c105_init_one,
366 .remove = ata_pci_remove_one
367};
368
369static int __init sl82c105_init(void)
370{
371 return pci_register_driver(&sl82c105_pci_driver);
372}
373
374
375static void __exit sl82c105_exit(void)
376{
377 pci_unregister_driver(&sl82c105_pci_driver);
378}
379
380
381MODULE_AUTHOR("Alan Cox");
382MODULE_DESCRIPTION("low-level driver for Sl82c105");
383MODULE_LICENSE("GPL");
384MODULE_DEVICE_TABLE(pci, sl82c105);
385MODULE_VERSION(DRV_VERSION);
386
387module_init(sl82c105_init);
388module_exit(sl82c105_exit);