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authorAlbert Lee <albertcc@tw.ibm.com>2007-08-20 04:56:29 -0400
committerJeff Garzik <jeff@garzik.org>2007-10-12 14:55:37 -0400
commite923090ddd9fef1d4e06dc6c5295e29baced19f3 (patch)
tree907852433d5eb6504ca3766c5df868013e85c926 /drivers/ata/pata_pdc2027x.c
parentc7293870a93a99e9ce0f4d98f3a271539c7c6ad6 (diff)
libata: pata_pdc2027x PLL detection minor cleanup
Minor cleanup to remove the unneeded rmb()s per Jeff's advice. Also removed the pll_clock < 0 check since pll_clock now guaranteed to be >= 0 after Mikael's patch. Signed-off-by: Albert Lee <albertcc@tw.ibm.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/pata_pdc2027x.c')
-rw-r--r--drivers/ata/pata_pdc2027x.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c
index 40b070ea85a1..2141a99e4da1 100644
--- a/drivers/ata/pata_pdc2027x.c
+++ b/drivers/ata/pata_pdc2027x.c
@@ -561,12 +561,10 @@ static long pdc_read_counter(struct ata_host *host)
561retry: 561retry:
562 bccrl = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff; 562 bccrl = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
563 bccrh = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; 563 bccrh = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
564 rmb();
565 564
566 /* Read the counter values again for verification */ 565 /* Read the counter values again for verification */
567 bccrlv = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff; 566 bccrlv = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
568 bccrhv = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; 567 bccrhv = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
569 rmb();
570 568
571 counter = (bccrh << 15) | bccrl; 569 counter = (bccrh << 15) | bccrl;
572 570
@@ -741,9 +739,6 @@ static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
741 */ 739 */
742 pll_clock = pdc_detect_pll_input_clock(host); 740 pll_clock = pdc_detect_pll_input_clock(host);
743 741
744 if (pll_clock < 0) /* counter overflow? Try again. */
745 pll_clock = pdc_detect_pll_input_clock(host);
746
747 dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n", pll_clock/1000); 742 dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
748 743
749 /* Adjust PLL control register */ 744 /* Adjust PLL control register */