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authorJeff Garzik <jeff@garzik.org>2006-08-29 18:12:40 -0400
committerJeff Garzik <jeff@garzik.org>2006-08-29 18:12:40 -0400
commit669a5db411d85a14f86cd92bc16bf7ab5b8aa235 (patch)
tree8d4f9d63e18185695a4d97e1a3fa4e18b61c7345 /drivers/ata/pata_optidma.c
parentb01e86fee6c821e4e003fd4e9f65453ac478a58e (diff)
[libata] Add a bunch of PATA drivers.
The vast majority of drivers and changes are from Alan Cox. Albert Lee contributed and maintains pata_pdc2027x. Adrian Bunk, Andrew Morton, and Tejun Heo contributed various minor fixes and updates. Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/pata_optidma.c')
-rw-r--r--drivers/ata/pata_optidma.c547
1 files changed, 547 insertions, 0 deletions
diff --git a/drivers/ata/pata_optidma.c b/drivers/ata/pata_optidma.c
new file mode 100644
index 000000000000..800aea7b9444
--- /dev/null
+++ b/drivers/ata/pata_optidma.c
@@ -0,0 +1,547 @@
1/*
2 * pata_optidma.c - Opti DMA PATA for new ATA layer
3 * (C) 2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * The Opti DMA controllers are related to the older PIO PCI controllers
7 * and indeed the VLB ones. The main differences are that the timing
8 * numbers are now based off PCI clocks not VLB and differ, and that
9 * MWDMA is supported.
10 *
11 * This driver should support Viper-N+, FireStar, FireStar Plus.
12 *
13 * These devices support virtual DMA for read (aka the CS5520). Later
14 * chips support UDMA33, but only if the rest of the board logic does,
15 * so you have to get this right. We don't support the virtual DMA
16 * but we do handle UDMA.
17 *
18 * Bits that are worth knowing
19 * Most control registers are shadowed into I/O registers
20 * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
21 * Virtual DMA registers *move* between rev 0x02 and rev 0x10
22 * UDMA requires a 66MHz FSB
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/blkdev.h>
31#include <linux/delay.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34
35#define DRV_NAME "pata_optidma"
36#define DRV_VERSION "0.2.1"
37
38enum {
39 READ_REG = 0, /* index of Read cycle timing register */
40 WRITE_REG = 1, /* index of Write cycle timing register */
41 CNTRL_REG = 3, /* index of Control register */
42 STRAP_REG = 5, /* index of Strap register */
43 MISC_REG = 6 /* index of Miscellaneous register */
44};
45
46static int pci_clock; /* 0 = 33 1 = 25 */
47
48/**
49 * optidma_pre_reset - probe begin
50 * @ap: ATA port
51 *
52 * Set up cable type and use generic probe init
53 */
54
55static int optidma_pre_reset(struct ata_port *ap)
56{
57 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
58 static const struct pci_bits optidma_enable_bits = {
59 0x40, 1, 0x08, 0x00
60 };
61
62 if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits)) {
63 ata_port_disable(ap);
64 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
65 return 0;
66 }
67 ap->cbl = ATA_CBL_PATA40;
68 return ata_std_prereset(ap);
69}
70
71/**
72 * optidma_probe_reset - probe reset
73 * @ap: ATA port
74 *
75 * Perform the ATA probe and bus reset sequence plus specific handling
76 * for this hardware. The Opti needs little handling - we have no UDMA66
77 * capability that needs cable detection. All we must do is check the port
78 * is enabled.
79 */
80
81static void optidma_error_handler(struct ata_port *ap)
82{
83 ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
84}
85
86/**
87 * optidma_unlock - unlock control registers
88 * @ap: ATA port
89 *
90 * Unlock the control register block for this adapter. Registers must not
91 * be unlocked in a situation where libata might look at them.
92 */
93
94static void optidma_unlock(struct ata_port *ap)
95{
96 unsigned long regio = ap->ioaddr.cmd_addr;
97
98 /* These 3 unlock the control register access */
99 inw(regio + 1);
100 inw(regio + 1);
101 outb(3, regio + 2);
102}
103
104/**
105 * optidma_lock - issue temporary relock
106 * @ap: ATA port
107 *
108 * Re-lock the configuration register settings.
109 */
110
111static void optidma_lock(struct ata_port *ap)
112{
113 unsigned long regio = ap->ioaddr.cmd_addr;
114
115 /* Relock */
116 outb(0x83, regio + 2);
117}
118
119/**
120 * optidma_set_mode - set mode data
121 * @ap: ATA interface
122 * @adev: ATA device
123 * @mode: Mode to set
124 *
125 * Called to do the DMA or PIO mode setup. Timing numbers are all
126 * pre computed to keep the code clean. There are two tables depending
127 * on the hardware clock speed.
128 *
129 * WARNING: While we do this the IDE registers vanish. If we take an
130 * IRQ here we depend on the host set locking to avoid catastrophe.
131 */
132
133static void optidma_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode)
134{
135 struct ata_device *pair = ata_dev_pair(adev);
136 int pio = adev->pio_mode - XFER_PIO_0;
137 int dma = adev->dma_mode - XFER_MW_DMA_0;
138 unsigned long regio = ap->ioaddr.cmd_addr;
139 u8 addr;
140
141 /* Address table precomputed with a DCLK of 2 */
142 static const u8 addr_timing[2][5] = {
143 { 0x30, 0x20, 0x20, 0x10, 0x10 },
144 { 0x20, 0x20, 0x10, 0x10, 0x10 }
145 };
146 static const u8 data_rec_timing[2][5] = {
147 { 0x59, 0x46, 0x30, 0x20, 0x20 },
148 { 0x46, 0x32, 0x20, 0x20, 0x10 }
149 };
150 static const u8 dma_data_rec_timing[2][3] = {
151 { 0x76, 0x20, 0x20 },
152 { 0x54, 0x20, 0x10 }
153 };
154
155 /* Switch from IDE to control mode */
156 optidma_unlock(ap);
157
158
159 /*
160 * As with many controllers the address setup time is shared
161 * and must suit both devices if present. FIXME: Check if we
162 * need to look at slowest of PIO/DMA mode of either device
163 */
164
165 if (mode >= XFER_MW_DMA_0)
166 addr = 0;
167 else
168 addr = addr_timing[pci_clock][pio];
169
170 if (pair) {
171 u8 pair_addr;
172 /* Hardware constraint */
173 if (pair->dma_mode)
174 pair_addr = 0;
175 else
176 pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
177 if (pair_addr > addr)
178 addr = pair_addr;
179 }
180
181 /* Commence primary programming sequence */
182 /* First we load the device number into the timing select */
183 outb(adev->devno, regio + MISC_REG);
184 /* Now we load the data timings into read data/write data */
185 if (mode < XFER_MW_DMA_0) {
186 outb(data_rec_timing[pci_clock][pio], regio + READ_REG);
187 outb(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
188 } else if (mode < XFER_UDMA_0) {
189 outb(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
190 outb(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
191 }
192 /* Finally we load the address setup into the misc register */
193 outb(addr | adev->devno, regio + MISC_REG);
194
195 /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
196 outb(0x85, regio + CNTRL_REG);
197
198 /* Switch back to IDE mode */
199 optidma_lock(ap);
200
201 /* Note: at this point our programming is incomplete. We are
202 not supposed to program PCI 0x43 "things we hacked onto the chip"
203 until we've done both sets of PIO/DMA timings */
204}
205
206/**
207 * optiplus_set_mode - DMA setup for Firestar Plus
208 * @ap: ATA port
209 * @adev: device
210 * @mode: desired mode
211 *
212 * The Firestar plus has additional UDMA functionality for UDMA0-2 and
213 * requires we do some additional work. Because the base work we must do
214 * is mostly shared we wrap the Firestar setup functionality in this
215 * one
216 */
217
218static void optiplus_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode)
219{
220 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
221 u8 udcfg;
222 u8 udslave;
223 int dev2 = 2 * adev->devno;
224 int unit = 2 * ap->port_no + adev->devno;
225 int udma = mode - XFER_UDMA_0;
226
227 pci_read_config_byte(pdev, 0x44, &udcfg);
228 if (mode <= XFER_UDMA_0) {
229 udcfg &= ~(1 << unit);
230 optidma_set_mode(ap, adev, adev->dma_mode);
231 } else {
232 udcfg |= (1 << unit);
233 if (ap->port_no) {
234 pci_read_config_byte(pdev, 0x45, &udslave);
235 udslave &= ~(0x03 << dev2);
236 udslave |= (udma << dev2);
237 pci_write_config_byte(pdev, 0x45, udslave);
238 } else {
239 udcfg &= ~(0x30 << dev2);
240 udcfg |= (udma << dev2);
241 }
242 }
243 pci_write_config_byte(pdev, 0x44, udcfg);
244}
245
246/**
247 * optidma_set_pio_mode - PIO setup callback
248 * @ap: ATA port
249 * @adev: Device
250 *
251 * The libata core provides separate functions for handling PIO and
252 * DMA programming. The architecture of the Firestar makes it easier
253 * for us to have a common function so we provide wrappers
254 */
255
256static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
257{
258 optidma_set_mode(ap, adev, adev->pio_mode);
259}
260
261/**
262 * optidma_set_dma_mode - DMA setup callback
263 * @ap: ATA port
264 * @adev: Device
265 *
266 * The libata core provides separate functions for handling PIO and
267 * DMA programming. The architecture of the Firestar makes it easier
268 * for us to have a common function so we provide wrappers
269 */
270
271static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
272{
273 optidma_set_mode(ap, adev, adev->dma_mode);
274}
275
276/**
277 * optiplus_set_pio_mode - PIO setup callback
278 * @ap: ATA port
279 * @adev: Device
280 *
281 * The libata core provides separate functions for handling PIO and
282 * DMA programming. The architecture of the Firestar makes it easier
283 * for us to have a common function so we provide wrappers
284 */
285
286static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
287{
288 optiplus_set_mode(ap, adev, adev->pio_mode);
289}
290
291/**
292 * optiplus_set_dma_mode - DMA setup callback
293 * @ap: ATA port
294 * @adev: Device
295 *
296 * The libata core provides separate functions for handling PIO and
297 * DMA programming. The architecture of the Firestar makes it easier
298 * for us to have a common function so we provide wrappers
299 */
300
301static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
302{
303 optiplus_set_mode(ap, adev, adev->dma_mode);
304}
305
306/**
307 * optidma_make_bits - PCI setup helper
308 * @adev: ATA device
309 *
310 * Turn the ATA device setup into PCI configuration bits
311 * for register 0x43 and return the two bits needed.
312 */
313
314static u8 optidma_make_bits43(struct ata_device *adev)
315{
316 static const u8 bits43[5] = {
317 0, 0, 0, 1, 2
318 };
319 if (!ata_dev_enabled(adev))
320 return 0;
321 if (adev->dma_mode)
322 return adev->dma_mode - XFER_MW_DMA_0;
323 return bits43[adev->pio_mode - XFER_PIO_0];
324}
325
326/**
327 * optidma_post_set_mode - finalize PCI setup
328 * @ap: port to set up
329 *
330 * Finalise the configuration by writing the nibble of extra bits
331 * of data into the chip.
332 */
333
334static void optidma_post_set_mode(struct ata_port *ap)
335{
336 u8 r;
337 int nybble = 4 * ap->port_no;
338 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
339
340 pci_read_config_byte(pdev, 0x43, &r);
341
342 r &= (0x0F << nybble);
343 r |= (optidma_make_bits43(&ap->device[0]) +
344 (optidma_make_bits43(&ap->device[0]) << 2)) << nybble;
345
346 pci_write_config_byte(pdev, 0x43, r);
347}
348
349static struct scsi_host_template optidma_sht = {
350 .module = THIS_MODULE,
351 .name = DRV_NAME,
352 .ioctl = ata_scsi_ioctl,
353 .queuecommand = ata_scsi_queuecmd,
354 .can_queue = ATA_DEF_QUEUE,
355 .this_id = ATA_SHT_THIS_ID,
356 .sg_tablesize = LIBATA_MAX_PRD,
357 .max_sectors = ATA_MAX_SECTORS,
358 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
359 .emulated = ATA_SHT_EMULATED,
360 .use_clustering = ATA_SHT_USE_CLUSTERING,
361 .proc_name = DRV_NAME,
362 .dma_boundary = ATA_DMA_BOUNDARY,
363 .slave_configure = ata_scsi_slave_config,
364 .bios_param = ata_std_bios_param,
365};
366
367static struct ata_port_operations optidma_port_ops = {
368 .port_disable = ata_port_disable,
369 .set_piomode = optidma_set_pio_mode,
370 .set_dmamode = optidma_set_dma_mode,
371
372 .tf_load = ata_tf_load,
373 .tf_read = ata_tf_read,
374 .check_status = ata_check_status,
375 .exec_command = ata_exec_command,
376 .dev_select = ata_std_dev_select,
377
378 .freeze = ata_bmdma_freeze,
379 .thaw = ata_bmdma_thaw,
380 .post_internal_cmd = ata_bmdma_post_internal_cmd,
381 .error_handler = optidma_error_handler,
382 .post_set_mode = optidma_post_set_mode,
383
384 .bmdma_setup = ata_bmdma_setup,
385 .bmdma_start = ata_bmdma_start,
386 .bmdma_stop = ata_bmdma_stop,
387 .bmdma_status = ata_bmdma_status,
388
389 .qc_prep = ata_qc_prep,
390 .qc_issue = ata_qc_issue_prot,
391 .eng_timeout = ata_eng_timeout,
392 .data_xfer = ata_pio_data_xfer,
393
394 .irq_handler = ata_interrupt,
395 .irq_clear = ata_bmdma_irq_clear,
396
397 .port_start = ata_port_start,
398 .port_stop = ata_port_stop,
399 .host_stop = ata_host_stop
400};
401
402static struct ata_port_operations optiplus_port_ops = {
403 .port_disable = ata_port_disable,
404 .set_piomode = optiplus_set_pio_mode,
405 .set_dmamode = optiplus_set_dma_mode,
406
407 .tf_load = ata_tf_load,
408 .tf_read = ata_tf_read,
409 .check_status = ata_check_status,
410 .exec_command = ata_exec_command,
411 .dev_select = ata_std_dev_select,
412
413 .freeze = ata_bmdma_freeze,
414 .thaw = ata_bmdma_thaw,
415 .post_internal_cmd = ata_bmdma_post_internal_cmd,
416 .error_handler = optidma_error_handler,
417 .post_set_mode = optidma_post_set_mode,
418
419 .bmdma_setup = ata_bmdma_setup,
420 .bmdma_start = ata_bmdma_start,
421 .bmdma_stop = ata_bmdma_stop,
422 .bmdma_status = ata_bmdma_status,
423
424 .qc_prep = ata_qc_prep,
425 .qc_issue = ata_qc_issue_prot,
426 .eng_timeout = ata_eng_timeout,
427 .data_xfer = ata_pio_data_xfer,
428
429 .irq_handler = ata_interrupt,
430 .irq_clear = ata_bmdma_irq_clear,
431
432 .port_start = ata_port_start,
433 .port_stop = ata_port_stop,
434 .host_stop = ata_host_stop
435};
436
437/**
438 * optiplus_with_udma - Look for UDMA capable setup
439 * @pdev; ATA controller
440 */
441
442static int optiplus_with_udma(struct pci_dev *pdev)
443{
444 u8 r;
445 int ret = 0;
446 int ioport = 0x22;
447 struct pci_dev *dev1;
448
449 /* Find function 1 */
450 dev1 = pci_get_device(0x1045, 0xC701, NULL);
451 if(dev1 == NULL)
452 return 0;
453
454 /* Rev must be >= 0x10 */
455 pci_read_config_byte(dev1, 0x08, &r);
456 if (r < 0x10)
457 goto done_nomsg;
458 /* Read the chipset system configuration to check our mode */
459 pci_read_config_byte(dev1, 0x5F, &r);
460 ioport |= (r << 8);
461 outb(0x10, ioport);
462 /* Must be 66Mhz sync */
463 if ((inb(ioport + 2) & 1) == 0)
464 goto done;
465
466 /* Check the ATA arbitration/timing is suitable */
467 pci_read_config_byte(pdev, 0x42, &r);
468 if ((r & 0x36) != 0x36)
469 goto done;
470 pci_read_config_byte(dev1, 0x52, &r);
471 if (r & 0x80) /* IDEDIR disabled */
472 ret = 1;
473done:
474 printk(KERN_WARNING "UDMA not supported in this configuration.\n");
475done_nomsg: /* Wrong chip revision */
476 pci_dev_put(dev1);
477 return ret;
478}
479
480static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
481{
482 static struct ata_port_info info_82c700 = {
483 .sht = &optidma_sht,
484 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
485 .pio_mask = 0x1f,
486 .mwdma_mask = 0x07,
487 .port_ops = &optidma_port_ops
488 };
489 static struct ata_port_info info_82c700_udma = {
490 .sht = &optidma_sht,
491 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
492 .pio_mask = 0x1f,
493 .mwdma_mask = 0x07,
494 .udma_mask = 0x07,
495 .port_ops = &optiplus_port_ops
496 };
497 static struct ata_port_info *port_info[2];
498 struct ata_port_info *info = &info_82c700;
499 static int printed_version;
500
501 if (!printed_version++)
502 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
503
504 /* Fixed location chipset magic */
505 inw(0x1F1);
506 inw(0x1F1);
507 pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */
508
509 if (optiplus_with_udma(dev))
510 info = &info_82c700_udma;
511
512 port_info[0] = port_info[1] = info;
513 return ata_pci_init_one(dev, port_info, 2);
514}
515
516static const struct pci_device_id optidma[] = {
517 { PCI_DEVICE(0x1045, 0xD568), }, /* Opti 82C700 */
518 { 0, },
519};
520
521static struct pci_driver optidma_pci_driver = {
522 .name = DRV_NAME,
523 .id_table = optidma,
524 .probe = optidma_init_one,
525 .remove = ata_pci_remove_one
526};
527
528static int __init optidma_init(void)
529{
530 return pci_register_driver(&optidma_pci_driver);
531}
532
533
534static void __exit optidma_exit(void)
535{
536 pci_unregister_driver(&optidma_pci_driver);
537}
538
539
540MODULE_AUTHOR("Alan Cox");
541MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
542MODULE_LICENSE("GPL");
543MODULE_DEVICE_TABLE(pci, optidma);
544MODULE_VERSION(DRV_VERSION);
545
546module_init(optidma_init);
547module_exit(optidma_exit);