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authorSylvain Munaut <tnt@246tNt.com>2006-12-07 18:14:16 -0500
committerJeff Garzik <jeff@garzik.org>2007-02-09 17:39:29 -0500
commit155d2916d9474f81178f501664499f40833c59b2 (patch)
tree46973693fae80deb0138ea7f801baeab152dbbbd /drivers/ata/pata_mpc52xx.c
parent9b13b682a68d5bcf09c75da73d4e61d92eba4c84 (diff)
[PATCH] libata: Add support for the MPC52xx ATA controller
This patch adds initial libata support for the Freescale MPC5200 integrated IDE controller. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/pata_mpc52xx.c')
-rw-r--r--drivers/ata/pata_mpc52xx.c563
1 files changed, 563 insertions, 0 deletions
diff --git a/drivers/ata/pata_mpc52xx.c b/drivers/ata/pata_mpc52xx.c
new file mode 100644
index 000000000000..8b7019a2f190
--- /dev/null
+++ b/drivers/ata/pata_mpc52xx.c
@@ -0,0 +1,563 @@
1/*
2 * drivers/ata/pata_mpc52xx.c
3 *
4 * libata driver for the Freescale MPC52xx on-chip IDE interface
5 *
6 * Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
7 * Copyright (C) 2003 Mipsys - Benjamin Herrenschmidt
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/slab.h>
17#include <linux/delay.h>
18#include <linux/libata.h>
19
20#include <asm/io.h>
21#include <asm/types.h>
22#include <asm/prom.h>
23#include <asm/of_platform.h>
24#include <asm/mpc52xx.h>
25
26
27#define DRV_NAME "mpc52xx_ata"
28#define DRV_VERSION "0.1.0"
29
30
31/* Private structures used by the driver */
32struct mpc52xx_ata_timings {
33 u32 pio1;
34 u32 pio2;
35};
36
37struct mpc52xx_ata_priv {
38 unsigned int ipb_period;
39 struct mpc52xx_ata __iomem * ata_regs;
40 int ata_irq;
41 struct mpc52xx_ata_timings timings[2];
42 int csel;
43};
44
45
46/* ATAPI-4 PIO specs (in ns) */
47static const int ataspec_t0[5] = {600, 383, 240, 180, 120};
48static const int ataspec_t1[5] = { 70, 50, 30, 30, 25};
49static const int ataspec_t2_8[5] = {290, 290, 290, 80, 70};
50static const int ataspec_t2_16[5] = {165, 125, 100, 80, 70};
51static const int ataspec_t2i[5] = { 0, 0, 0, 70, 25};
52static const int ataspec_t4[5] = { 30, 20, 15, 10, 10};
53static const int ataspec_ta[5] = { 35, 35, 35, 35, 35};
54
55#define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c)))
56
57
58/* Bit definitions inside the registers */
59#define MPC52xx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine reset */
60#define MPC52xx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
61#define MPC52xx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt in PIO */
62#define MPC52xx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports IORDY protocol */
63
64#define MPC52xx_ATA_HOSTSTAT_TIP 0x80000000UL /* Transaction in progress */
65#define MPC52xx_ATA_HOSTSTAT_UREP 0x40000000UL /* UDMA Read Extended Pause */
66#define MPC52xx_ATA_HOSTSTAT_RERR 0x02000000UL /* Read Error */
67#define MPC52xx_ATA_HOSTSTAT_WERR 0x01000000UL /* Write Error */
68
69#define MPC52xx_ATA_FIFOSTAT_EMPTY 0x01 /* FIFO Empty */
70
71#define MPC52xx_ATA_DMAMODE_WRITE 0x01 /* Write DMA */
72#define MPC52xx_ATA_DMAMODE_READ 0x02 /* Read DMA */
73#define MPC52xx_ATA_DMAMODE_UDMA 0x04 /* UDMA enabled */
74#define MPC52xx_ATA_DMAMODE_IE 0x08 /* Enable drive interrupt to CPU in DMA mode */
75#define MPC52xx_ATA_DMAMODE_FE 0x10 /* FIFO Flush enable in Rx mode */
76#define MPC52xx_ATA_DMAMODE_FR 0x20 /* FIFO Reset */
77#define MPC52xx_ATA_DMAMODE_HUT 0x40 /* Host UDMA burst terminate */
78
79
80/* Structure of the hardware registers */
81struct mpc52xx_ata {
82
83 /* Host interface registers */
84 u32 config; /* ATA + 0x00 Host configuration */
85 u32 host_status; /* ATA + 0x04 Host controller status */
86 u32 pio1; /* ATA + 0x08 PIO Timing 1 */
87 u32 pio2; /* ATA + 0x0c PIO Timing 2 */
88 u32 mdma1; /* ATA + 0x10 MDMA Timing 1 */
89 u32 mdma2; /* ATA + 0x14 MDMA Timing 2 */
90 u32 udma1; /* ATA + 0x18 UDMA Timing 1 */
91 u32 udma2; /* ATA + 0x1c UDMA Timing 2 */
92 u32 udma3; /* ATA + 0x20 UDMA Timing 3 */
93 u32 udma4; /* ATA + 0x24 UDMA Timing 4 */
94 u32 udma5; /* ATA + 0x28 UDMA Timing 5 */
95 u32 share_cnt; /* ATA + 0x2c ATA share counter */
96 u32 reserved0[3];
97
98 /* FIFO registers */
99 u32 fifo_data; /* ATA + 0x3c */
100 u8 fifo_status_frame; /* ATA + 0x40 */
101 u8 fifo_status; /* ATA + 0x41 */
102 u16 reserved7[1];
103 u8 fifo_control; /* ATA + 0x44 */
104 u8 reserved8[5];
105 u16 fifo_alarm; /* ATA + 0x4a */
106 u16 reserved9;
107 u16 fifo_rdp; /* ATA + 0x4e */
108 u16 reserved10;
109 u16 fifo_wrp; /* ATA + 0x52 */
110 u16 reserved11;
111 u16 fifo_lfrdp; /* ATA + 0x56 */
112 u16 reserved12;
113 u16 fifo_lfwrp; /* ATA + 0x5a */
114
115 /* Drive TaskFile registers */
116 u8 tf_control; /* ATA + 0x5c TASKFILE Control/Alt Status */
117 u8 reserved13[3];
118 u16 tf_data; /* ATA + 0x60 TASKFILE Data */
119 u16 reserved14;
120 u8 tf_features; /* ATA + 0x64 TASKFILE Features/Error */
121 u8 reserved15[3];
122 u8 tf_sec_count; /* ATA + 0x68 TASKFILE Sector Count */
123 u8 reserved16[3];
124 u8 tf_sec_num; /* ATA + 0x6c TASKFILE Sector Number */
125 u8 reserved17[3];
126 u8 tf_cyl_low; /* ATA + 0x70 TASKFILE Cylinder Low */
127 u8 reserved18[3];
128 u8 tf_cyl_high; /* ATA + 0x74 TASKFILE Cylinder High */
129 u8 reserved19[3];
130 u8 tf_dev_head; /* ATA + 0x78 TASKFILE Device/Head */
131 u8 reserved20[3];
132 u8 tf_command; /* ATA + 0x7c TASKFILE Command/Status */
133 u8 dma_mode; /* ATA + 0x7d ATA Host DMA Mode configuration */
134 u8 reserved21[2];
135};
136
137
138/* ======================================================================== */
139/* Aux fns */
140/* ======================================================================== */
141
142
143/* MPC52xx low level hw control */
144
145static int
146mpc52xx_ata_compute_pio_timings(struct mpc52xx_ata_priv *priv, int dev, int pio)
147{
148 struct mpc52xx_ata_timings *timing = &priv->timings[dev];
149 unsigned int ipb_period = priv->ipb_period;
150 unsigned int t0, t1, t2_8, t2_16, t2i, t4, ta;
151
152 if ((pio<0) || (pio>4))
153 return -EINVAL;
154
155 t0 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t0[pio]);
156 t1 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t1[pio]);
157 t2_8 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_8[pio]);
158 t2_16 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_16[pio]);
159 t2i = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2i[pio]);
160 t4 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t4[pio]);
161 ta = CALC_CLKCYC(ipb_period, 1000 * ataspec_ta[pio]);
162
163 timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i);
164 timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8);
165
166 return 0;
167}
168
169static void
170mpc52xx_ata_apply_timings(struct mpc52xx_ata_priv *priv, int device)
171{
172 struct mpc52xx_ata __iomem *regs = priv->ata_regs;
173 struct mpc52xx_ata_timings *timing = &priv->timings[device];
174
175 out_be32(&regs->pio1, timing->pio1);
176 out_be32(&regs->pio2, timing->pio2);
177 out_be32(&regs->mdma1, 0);
178 out_be32(&regs->mdma2, 0);
179 out_be32(&regs->udma1, 0);
180 out_be32(&regs->udma2, 0);
181 out_be32(&regs->udma3, 0);
182 out_be32(&regs->udma4, 0);
183 out_be32(&regs->udma5, 0);
184
185 priv->csel = device;
186}
187
188static int
189mpc52xx_ata_hw_init(struct mpc52xx_ata_priv *priv)
190{
191 struct mpc52xx_ata __iomem *regs = priv->ata_regs;
192 int tslot;
193
194 /* Clear share_cnt (all sample code do this ...) */
195 out_be32(&regs->share_cnt, 0);
196
197 /* Configure and reset host */
198 out_be32(&regs->config,
199 MPC52xx_ATA_HOSTCONF_IE |
200 MPC52xx_ATA_HOSTCONF_IORDY |
201 MPC52xx_ATA_HOSTCONF_SMR |
202 MPC52xx_ATA_HOSTCONF_FR);
203
204 udelay(10);
205
206 out_be32(&regs->config,
207 MPC52xx_ATA_HOSTCONF_IE |
208 MPC52xx_ATA_HOSTCONF_IORDY);
209
210 /* Set the time slot to 1us */
211 tslot = CALC_CLKCYC(priv->ipb_period, 1000000);
212 out_be32(&regs->share_cnt, tslot << 16 );
213
214 /* Init timings to PIO0 */
215 memset(priv->timings, 0x00, 2*sizeof(struct mpc52xx_ata_timings));
216
217 mpc52xx_ata_compute_pio_timings(priv, 0, 0);
218 mpc52xx_ata_compute_pio_timings(priv, 1, 0);
219
220 mpc52xx_ata_apply_timings(priv, 0);
221
222 return 0;
223}
224
225
226/* ======================================================================== */
227/* libata driver */
228/* ======================================================================== */
229
230static void
231mpc52xx_ata_set_piomode(struct ata_port *ap, struct ata_device *adev)
232{
233 struct mpc52xx_ata_priv *priv = ap->host->private_data;
234 int pio, rv;
235
236 pio = adev->pio_mode - XFER_PIO_0;
237
238 rv = mpc52xx_ata_compute_pio_timings(priv, adev->devno, pio);
239
240 if (rv) {
241 printk(KERN_ERR DRV_NAME
242 ": Trying to select invalid PIO mode %d\n", pio);
243 return;
244 }
245
246 mpc52xx_ata_apply_timings(priv, adev->devno);
247}
248static void
249mpc52xx_ata_dev_select(struct ata_port *ap, unsigned int device)
250{
251 struct mpc52xx_ata_priv *priv = ap->host->private_data;
252
253 if (device != priv->csel)
254 mpc52xx_ata_apply_timings(priv, device);
255
256 ata_std_dev_select(ap,device);
257}
258
259static void
260mpc52xx_ata_error_handler(struct ata_port *ap)
261{
262 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
263 ata_std_postreset);
264}
265
266
267
268static struct scsi_host_template mpc52xx_ata_sht = {
269 .module = THIS_MODULE,
270 .name = DRV_NAME,
271 .ioctl = ata_scsi_ioctl,
272 .queuecommand = ata_scsi_queuecmd,
273 .can_queue = ATA_DEF_QUEUE,
274 .this_id = ATA_SHT_THIS_ID,
275 .sg_tablesize = LIBATA_MAX_PRD,
276 .max_sectors = ATA_MAX_SECTORS,
277 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
278 .emulated = ATA_SHT_EMULATED,
279 .use_clustering = ATA_SHT_USE_CLUSTERING,
280 .proc_name = DRV_NAME,
281 .dma_boundary = ATA_DMA_BOUNDARY,
282 .slave_configure = ata_scsi_slave_config,
283 .bios_param = ata_std_bios_param,
284};
285
286static struct ata_port_operations mpc52xx_ata_port_ops = {
287 .port_disable = ata_port_disable,
288 .set_piomode = mpc52xx_ata_set_piomode,
289 .dev_select = mpc52xx_ata_dev_select,
290 .tf_load = ata_tf_load,
291 .tf_read = ata_tf_read,
292 .check_status = ata_check_status,
293 .exec_command = ata_exec_command,
294 .freeze = ata_bmdma_freeze,
295 .thaw = ata_bmdma_thaw,
296 .error_handler = mpc52xx_ata_error_handler,
297 .qc_prep = ata_qc_prep,
298 .qc_issue = ata_qc_issue_prot,
299 .data_xfer = ata_mmio_data_xfer,
300 .irq_handler = ata_interrupt,
301 .irq_clear = ata_bmdma_irq_clear,
302 .port_start = ata_port_start,
303 .port_stop = ata_port_stop,
304 .host_stop = ata_host_stop,
305};
306
307static struct ata_probe_ent mpc52xx_ata_probe_ent = {
308 .port_ops = &mpc52xx_ata_port_ops,
309 .sht = &mpc52xx_ata_sht,
310 .n_ports = 1,
311 .pio_mask = 0x1f, /* Up to PIO4 */
312 .mwdma_mask = 0x00, /* No MWDMA */
313 .udma_mask = 0x00, /* No UDMA */
314 .port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_MMIO,
315 .irq_flags = 0,
316};
317
318static int __devinit
319mpc52xx_ata_init_one(struct device *dev, struct mpc52xx_ata_priv *priv)
320{
321 struct ata_probe_ent *ae = &mpc52xx_ata_probe_ent;
322 struct ata_ioports *aio = &ae->port[0];
323 int rv;
324
325 INIT_LIST_HEAD(&ae->node);
326 ae->dev = dev;
327 ae->irq = priv->ata_irq;
328
329 aio->cmd_addr = 0; /* Don't have a classic reg block */
330 aio->altstatus_addr = (unsigned long)&priv->ata_regs->tf_control;
331 aio->ctl_addr = (unsigned long)&priv->ata_regs->tf_control;
332 aio->data_addr = (unsigned long)&priv->ata_regs->tf_data;
333 aio->error_addr = (unsigned long)&priv->ata_regs->tf_features;
334 aio->feature_addr = (unsigned long)&priv->ata_regs->tf_features;
335 aio->nsect_addr = (unsigned long)&priv->ata_regs->tf_sec_count;
336 aio->lbal_addr = (unsigned long)&priv->ata_regs->tf_sec_num;
337 aio->lbam_addr = (unsigned long)&priv->ata_regs->tf_cyl_low;
338 aio->lbah_addr = (unsigned long)&priv->ata_regs->tf_cyl_high;
339 aio->device_addr = (unsigned long)&priv->ata_regs->tf_dev_head;
340 aio->status_addr = (unsigned long)&priv->ata_regs->tf_command;
341 aio->command_addr = (unsigned long)&priv->ata_regs->tf_command;
342
343 ae->private_data = priv;
344
345 rv = ata_device_add(ae);
346
347 return rv ? 0 : -EINVAL;
348}
349
350static struct mpc52xx_ata_priv *
351mpc52xx_ata_remove_one(struct device *dev)
352{
353 struct ata_host *host = dev_get_drvdata(dev);
354 struct mpc52xx_ata_priv *priv = host->private_data;
355
356 ata_host_remove(host);
357
358 return priv;
359}
360
361
362/* ======================================================================== */
363/* OF Platform driver */
364/* ======================================================================== */
365
366static int __devinit
367mpc52xx_ata_probe(struct of_device *op, const struct of_device_id *match)
368{
369 unsigned int ipb_freq;
370 struct resource res_mem;
371 int ata_irq = NO_IRQ;
372 struct mpc52xx_ata __iomem *ata_regs = NULL;
373 struct mpc52xx_ata_priv *priv = NULL;
374 int rv;
375
376 /* Get ipb frequency */
377 ipb_freq = mpc52xx_find_ipb_freq(op->node);
378 if (!ipb_freq) {
379 printk(KERN_ERR DRV_NAME ": "
380 "Unable to find IPB Bus frequency\n" );
381 return -ENODEV;
382 }
383
384 /* Get IRQ and register */
385 rv = of_address_to_resource(op->node, 0, &res_mem);
386 if (rv) {
387 printk(KERN_ERR DRV_NAME ": "
388 "Error while parsing device node resource\n" );
389 return rv;
390 }
391
392 ata_irq = irq_of_parse_and_map(op->node, 0);
393 if (ata_irq == NO_IRQ) {
394 printk(KERN_ERR DRV_NAME ": "
395 "Error while mapping the irq\n");
396 return -EINVAL;
397 }
398
399 /* Request mem region */
400 if (!request_mem_region(res_mem.start,
401 sizeof(struct mpc52xx_ata), DRV_NAME)) {
402 printk(KERN_ERR DRV_NAME ": "
403 "Error while requesting mem region\n");
404 irq_dispose_mapping(ata_irq);
405 return -EBUSY;
406 }
407
408 /* Remap registers */
409 ata_regs = ioremap(res_mem.start, sizeof(struct mpc52xx_ata));
410 if (!ata_regs) {
411 printk(KERN_ERR DRV_NAME ": "
412 "Error while mapping register set\n");
413 rv = -ENOMEM;
414 goto err;
415 }
416
417 /* Prepare our private structure */
418 priv = kmalloc(sizeof(struct mpc52xx_ata_priv), GFP_ATOMIC);
419 if (!priv) {
420 printk(KERN_ERR DRV_NAME ": "
421 "Error while allocating private structure\n");
422 rv = -ENOMEM;
423 goto err;
424 }
425
426 priv->ipb_period = 1000000000 / (ipb_freq / 1000);
427 priv->ata_regs = ata_regs;
428 priv->ata_irq = ata_irq;
429 priv->csel = -1;
430
431 /* Init the hw */
432 rv = mpc52xx_ata_hw_init(priv);
433 if (rv) {
434 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
435 goto err;
436 }
437
438 /* Register ourselves to libata */
439 rv = mpc52xx_ata_init_one(&op->dev, priv);
440 if (rv) {
441 printk(KERN_ERR DRV_NAME ": "
442 "Error while registering to ATA layer\n");
443 return rv;
444 }
445
446 /* Done */
447 return 0;
448
449 /* Error path */
450err:
451 kfree(priv);
452
453 if (ata_regs)
454 iounmap(ata_regs);
455
456 release_mem_region(res_mem.start, sizeof(struct mpc52xx_ata));
457
458 irq_dispose_mapping(ata_irq);
459
460 return rv;
461}
462
463static int
464mpc52xx_ata_remove(struct of_device *op)
465{
466 struct mpc52xx_ata_priv *priv;
467 struct resource res_mem;
468 int rv;
469
470 /* Unregister */
471 priv = mpc52xx_ata_remove_one(&op->dev);
472
473 /* Free everything */
474 iounmap(priv->ata_regs);
475
476 rv = of_address_to_resource(op->node, 0, &res_mem);
477 if (rv) {
478 printk(KERN_ERR DRV_NAME ": "
479 "Error while parsing device node resource\n");
480 printk(KERN_ERR DRV_NAME ": "
481 "Zone may not be properly released\n");
482 } else
483 release_mem_region(res_mem.start, sizeof(struct mpc52xx_ata));
484
485 irq_dispose_mapping(priv->ata_irq);
486
487 kfree(priv);
488
489 return 0;
490}
491
492
493#ifdef CONFIG_PM
494
495static int
496mpc52xx_ata_suspend(struct of_device *op, pm_message_t state)
497{
498 return 0; /* FIXME : What to do here ? */
499}
500
501static int
502mpc52xx_ata_resume(struct of_device *op)
503{
504 return 0; /* FIXME : What to do here ? */
505}
506
507#endif
508
509
510static struct of_device_id mpc52xx_ata_of_match[] = {
511 {
512 .compatible = "mpc5200-ata",
513 },
514 {
515 .compatible = "mpc52xx-ata",
516 },
517 {},
518};
519
520
521static struct of_platform_driver mpc52xx_ata_of_platform_driver = {
522 .owner = THIS_MODULE,
523 .name = DRV_NAME,
524 .match_table = mpc52xx_ata_of_match,
525 .probe = mpc52xx_ata_probe,
526 .remove = mpc52xx_ata_remove,
527#ifdef CONFIG_PM
528 .suspend = mpc52xx_ata_suspend,
529 .resume = mpc52xx_ata_resume,
530#endif
531 .driver = {
532 .name = DRV_NAME,
533 .owner = THIS_MODULE,
534 },
535};
536
537
538/* ======================================================================== */
539/* Module */
540/* ======================================================================== */
541
542static int __init
543mpc52xx_ata_init(void)
544{
545 printk(KERN_INFO "ata: MPC52xx IDE/ATA libata driver\n");
546 return of_register_platform_driver(&mpc52xx_ata_of_platform_driver);
547}
548
549static void __exit
550mpc52xx_ata_exit(void)
551{
552 of_unregister_platform_driver(&mpc52xx_ata_of_platform_driver);
553}
554
555module_init(mpc52xx_ata_init);
556module_exit(mpc52xx_ata_exit);
557
558MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
559MODULE_DESCRIPTION("Freescale MPC52xx IDE/ATA libata driver");
560MODULE_LICENSE("GPL");
561MODULE_DEVICE_TABLE(of, mpc52xx_ata_of_match);
562MODULE_VERSION(DRV_VERSION);
563
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