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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-12-08 14:25:28 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-12-11 09:52:44 -0500
commitf6718653361e8f8a6aac9946822aa2090edf4f37 (patch)
tree884f9ec31d7c6c33ffaa443bb01c03fdff7292f9 /drivers/ata/pata_icside.c
parent9e28d7e8c5422a47db886c4104221ea165595de0 (diff)
[ARM] dma: pata_icside's contiguous sg array is now redundant
Now that the IOMD DMA code walks the scatterlist using sg_next, converting the sg list into a contiguous list is no longer required. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/ata/pata_icside.c')
-rw-r--r--drivers/ata/pata_icside.c13
1 files changed, 1 insertions, 12 deletions
diff --git a/drivers/ata/pata_icside.c b/drivers/ata/pata_icside.c
index cf9e9848f8b5..63121f45ba25 100644
--- a/drivers/ata/pata_icside.c
+++ b/drivers/ata/pata_icside.c
@@ -57,7 +57,6 @@ struct pata_icside_state {
57 u8 disabled; 57 u8 disabled;
58 unsigned int speed[ATA_MAX_DEVICES]; 58 unsigned int speed[ATA_MAX_DEVICES];
59 } port[2]; 59 } port[2];
60 struct scatterlist sg[PATA_ICSIDE_MAX_SG];
61}; 60};
62 61
63struct pata_icside_info { 62struct pata_icside_info {
@@ -222,9 +221,7 @@ static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
222{ 221{
223 struct ata_port *ap = qc->ap; 222 struct ata_port *ap = qc->ap;
224 struct pata_icside_state *state = ap->host->private_data; 223 struct pata_icside_state *state = ap->host->private_data;
225 struct scatterlist *sg, *rsg = state->sg;
226 unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE; 224 unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;
227 unsigned int si;
228 225
229 /* 226 /*
230 * We are simplex; BUG if we try to fiddle with DMA 227 * We are simplex; BUG if we try to fiddle with DMA
@@ -233,20 +230,12 @@ static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
233 BUG_ON(dma_channel_active(state->dma)); 230 BUG_ON(dma_channel_active(state->dma));
234 231
235 /* 232 /*
236 * Copy ATAs scattered sg list into a contiguous array of sg
237 */
238 for_each_sg(qc->sg, sg, qc->n_elem, si) {
239 memcpy(rsg, sg, sizeof(*sg));
240 rsg++;
241 }
242
243 /*
244 * Route the DMA signals to the correct interface 233 * Route the DMA signals to the correct interface
245 */ 234 */
246 writeb(state->port[ap->port_no].port_sel, state->ioc_base); 235 writeb(state->port[ap->port_no].port_sel, state->ioc_base);
247 236
248 set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]); 237 set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
249 set_dma_sg(state->dma, state->sg, rsg - state->sg); 238 set_dma_sg(state->dma, qc->sg, qc->n_elem);
250 set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ); 239 set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);
251 240
252 /* issue r/w command */ 241 /* issue r/w command */