diff options
author | Tejun Heo <htejun@gmail.com> | 2007-02-01 01:06:36 -0500 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2007-02-09 17:39:38 -0500 |
commit | 0d5ff566779f894ca9937231a181eb31e4adff0e (patch) | |
tree | d1c7495c932581c1d41aa7f0fdb303348da49106 /drivers/ata/libata-sff.c | |
parent | 1a68ff13c8a9b517de3fd4187dc525412a6eba1b (diff) |
libata: convert to iomap
Convert libata core layer and LLDs to use iomap.
* managed iomap is used. Pointer to pcim_iomap_table() is cached at
host->iomap and used through out LLDs. This basically replaces
host->mmio_base.
* if possible, pcim_iomap_regions() is used
Most iomap operation conversions are taken from Jeff Garzik
<jgarzik@pobox.com>'s iomap branch.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/libata-sff.c')
-rw-r--r-- | drivers/ata/libata-sff.c | 544 |
1 files changed, 108 insertions, 436 deletions
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c index 21efe92a7135..c561b3be4a97 100644 --- a/drivers/ata/libata-sff.c +++ b/drivers/ata/libata-sff.c | |||
@@ -56,10 +56,7 @@ u8 ata_irq_on(struct ata_port *ap) | |||
56 | ap->ctl &= ~ATA_NIEN; | 56 | ap->ctl &= ~ATA_NIEN; |
57 | ap->last_ctl = ap->ctl; | 57 | ap->last_ctl = ap->ctl; |
58 | 58 | ||
59 | if (ap->flags & ATA_FLAG_MMIO) | 59 | iowrite8(ap->ctl, ioaddr->ctl_addr); |
60 | writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr); | ||
61 | else | ||
62 | outb(ap->ctl, ioaddr->ctl_addr); | ||
63 | tmp = ata_wait_idle(ap); | 60 | tmp = ata_wait_idle(ap); |
64 | 61 | ||
65 | ap->ops->irq_clear(ap); | 62 | ap->ops->irq_clear(ap); |
@@ -68,7 +65,7 @@ u8 ata_irq_on(struct ata_port *ap) | |||
68 | } | 65 | } |
69 | 66 | ||
70 | /** | 67 | /** |
71 | * ata_tf_load_pio - send taskfile registers to host controller | 68 | * ata_tf_load - send taskfile registers to host controller |
72 | * @ap: Port to which output is sent | 69 | * @ap: Port to which output is sent |
73 | * @tf: ATA taskfile register set | 70 | * @tf: ATA taskfile register set |
74 | * | 71 | * |
@@ -78,81 +75,23 @@ u8 ata_irq_on(struct ata_port *ap) | |||
78 | * Inherited from caller. | 75 | * Inherited from caller. |
79 | */ | 76 | */ |
80 | 77 | ||
81 | static void ata_tf_load_pio(struct ata_port *ap, const struct ata_taskfile *tf) | 78 | void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
82 | { | ||
83 | struct ata_ioports *ioaddr = &ap->ioaddr; | ||
84 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | ||
85 | |||
86 | if (tf->ctl != ap->last_ctl) { | ||
87 | outb(tf->ctl, ioaddr->ctl_addr); | ||
88 | ap->last_ctl = tf->ctl; | ||
89 | ata_wait_idle(ap); | ||
90 | } | ||
91 | |||
92 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | ||
93 | outb(tf->hob_feature, ioaddr->feature_addr); | ||
94 | outb(tf->hob_nsect, ioaddr->nsect_addr); | ||
95 | outb(tf->hob_lbal, ioaddr->lbal_addr); | ||
96 | outb(tf->hob_lbam, ioaddr->lbam_addr); | ||
97 | outb(tf->hob_lbah, ioaddr->lbah_addr); | ||
98 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | ||
99 | tf->hob_feature, | ||
100 | tf->hob_nsect, | ||
101 | tf->hob_lbal, | ||
102 | tf->hob_lbam, | ||
103 | tf->hob_lbah); | ||
104 | } | ||
105 | |||
106 | if (is_addr) { | ||
107 | outb(tf->feature, ioaddr->feature_addr); | ||
108 | outb(tf->nsect, ioaddr->nsect_addr); | ||
109 | outb(tf->lbal, ioaddr->lbal_addr); | ||
110 | outb(tf->lbam, ioaddr->lbam_addr); | ||
111 | outb(tf->lbah, ioaddr->lbah_addr); | ||
112 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | ||
113 | tf->feature, | ||
114 | tf->nsect, | ||
115 | tf->lbal, | ||
116 | tf->lbam, | ||
117 | tf->lbah); | ||
118 | } | ||
119 | |||
120 | if (tf->flags & ATA_TFLAG_DEVICE) { | ||
121 | outb(tf->device, ioaddr->device_addr); | ||
122 | VPRINTK("device 0x%X\n", tf->device); | ||
123 | } | ||
124 | |||
125 | ata_wait_idle(ap); | ||
126 | } | ||
127 | |||
128 | /** | ||
129 | * ata_tf_load_mmio - send taskfile registers to host controller | ||
130 | * @ap: Port to which output is sent | ||
131 | * @tf: ATA taskfile register set | ||
132 | * | ||
133 | * Outputs ATA taskfile to standard ATA host controller using MMIO. | ||
134 | * | ||
135 | * LOCKING: | ||
136 | * Inherited from caller. | ||
137 | */ | ||
138 | |||
139 | static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) | ||
140 | { | 79 | { |
141 | struct ata_ioports *ioaddr = &ap->ioaddr; | 80 | struct ata_ioports *ioaddr = &ap->ioaddr; |
142 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | 81 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; |
143 | 82 | ||
144 | if (tf->ctl != ap->last_ctl) { | 83 | if (tf->ctl != ap->last_ctl) { |
145 | writeb(tf->ctl, (void __iomem *) ap->ioaddr.ctl_addr); | 84 | iowrite8(tf->ctl, ioaddr->ctl_addr); |
146 | ap->last_ctl = tf->ctl; | 85 | ap->last_ctl = tf->ctl; |
147 | ata_wait_idle(ap); | 86 | ata_wait_idle(ap); |
148 | } | 87 | } |
149 | 88 | ||
150 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | 89 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { |
151 | writeb(tf->hob_feature, (void __iomem *) ioaddr->feature_addr); | 90 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
152 | writeb(tf->hob_nsect, (void __iomem *) ioaddr->nsect_addr); | 91 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); |
153 | writeb(tf->hob_lbal, (void __iomem *) ioaddr->lbal_addr); | 92 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); |
154 | writeb(tf->hob_lbam, (void __iomem *) ioaddr->lbam_addr); | 93 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); |
155 | writeb(tf->hob_lbah, (void __iomem *) ioaddr->lbah_addr); | 94 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); |
156 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | 95 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", |
157 | tf->hob_feature, | 96 | tf->hob_feature, |
158 | tf->hob_nsect, | 97 | tf->hob_nsect, |
@@ -162,11 +101,11 @@ static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) | |||
162 | } | 101 | } |
163 | 102 | ||
164 | if (is_addr) { | 103 | if (is_addr) { |
165 | writeb(tf->feature, (void __iomem *) ioaddr->feature_addr); | 104 | iowrite8(tf->feature, ioaddr->feature_addr); |
166 | writeb(tf->nsect, (void __iomem *) ioaddr->nsect_addr); | 105 | iowrite8(tf->nsect, ioaddr->nsect_addr); |
167 | writeb(tf->lbal, (void __iomem *) ioaddr->lbal_addr); | 106 | iowrite8(tf->lbal, ioaddr->lbal_addr); |
168 | writeb(tf->lbam, (void __iomem *) ioaddr->lbam_addr); | 107 | iowrite8(tf->lbam, ioaddr->lbam_addr); |
169 | writeb(tf->lbah, (void __iomem *) ioaddr->lbah_addr); | 108 | iowrite8(tf->lbah, ioaddr->lbah_addr); |
170 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | 109 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", |
171 | tf->feature, | 110 | tf->feature, |
172 | tf->nsect, | 111 | tf->nsect, |
@@ -176,108 +115,34 @@ static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) | |||
176 | } | 115 | } |
177 | 116 | ||
178 | if (tf->flags & ATA_TFLAG_DEVICE) { | 117 | if (tf->flags & ATA_TFLAG_DEVICE) { |
179 | writeb(tf->device, (void __iomem *) ioaddr->device_addr); | 118 | iowrite8(tf->device, ioaddr->device_addr); |
180 | VPRINTK("device 0x%X\n", tf->device); | 119 | VPRINTK("device 0x%X\n", tf->device); |
181 | } | 120 | } |
182 | 121 | ||
183 | ata_wait_idle(ap); | 122 | ata_wait_idle(ap); |
184 | } | 123 | } |
185 | 124 | ||
186 | |||
187 | /** | ||
188 | * ata_tf_load - send taskfile registers to host controller | ||
189 | * @ap: Port to which output is sent | ||
190 | * @tf: ATA taskfile register set | ||
191 | * | ||
192 | * Outputs ATA taskfile to standard ATA host controller using MMIO | ||
193 | * or PIO as indicated by the ATA_FLAG_MMIO flag. | ||
194 | * Writes the control, feature, nsect, lbal, lbam, and lbah registers. | ||
195 | * Optionally (ATA_TFLAG_LBA48) writes hob_feature, hob_nsect, | ||
196 | * hob_lbal, hob_lbam, and hob_lbah. | ||
197 | * | ||
198 | * This function waits for idle (!BUSY and !DRQ) after writing | ||
199 | * registers. If the control register has a new value, this | ||
200 | * function also waits for idle after writing control and before | ||
201 | * writing the remaining registers. | ||
202 | * | ||
203 | * May be used as the tf_load() entry in ata_port_operations. | ||
204 | * | ||
205 | * LOCKING: | ||
206 | * Inherited from caller. | ||
207 | */ | ||
208 | void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) | ||
209 | { | ||
210 | if (ap->flags & ATA_FLAG_MMIO) | ||
211 | ata_tf_load_mmio(ap, tf); | ||
212 | else | ||
213 | ata_tf_load_pio(ap, tf); | ||
214 | } | ||
215 | |||
216 | /** | ||
217 | * ata_exec_command_pio - issue ATA command to host controller | ||
218 | * @ap: port to which command is being issued | ||
219 | * @tf: ATA taskfile register set | ||
220 | * | ||
221 | * Issues PIO write to ATA command register, with proper | ||
222 | * synchronization with interrupt handler / other threads. | ||
223 | * | ||
224 | * LOCKING: | ||
225 | * spin_lock_irqsave(host lock) | ||
226 | */ | ||
227 | |||
228 | static void ata_exec_command_pio(struct ata_port *ap, const struct ata_taskfile *tf) | ||
229 | { | ||
230 | DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command); | ||
231 | |||
232 | outb(tf->command, ap->ioaddr.command_addr); | ||
233 | ata_pause(ap); | ||
234 | } | ||
235 | |||
236 | |||
237 | /** | 125 | /** |
238 | * ata_exec_command_mmio - issue ATA command to host controller | 126 | * ata_exec_command - issue ATA command to host controller |
239 | * @ap: port to which command is being issued | 127 | * @ap: port to which command is being issued |
240 | * @tf: ATA taskfile register set | 128 | * @tf: ATA taskfile register set |
241 | * | 129 | * |
242 | * Issues MMIO write to ATA command register, with proper | 130 | * Issues ATA command, with proper synchronization with interrupt |
243 | * synchronization with interrupt handler / other threads. | 131 | * handler / other threads. |
244 | * | ||
245 | * FIXME: missing write posting for 400nS delay enforcement | ||
246 | * | 132 | * |
247 | * LOCKING: | 133 | * LOCKING: |
248 | * spin_lock_irqsave(host lock) | 134 | * spin_lock_irqsave(host lock) |
249 | */ | 135 | */ |
250 | 136 | void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) | |
251 | static void ata_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) | ||
252 | { | 137 | { |
253 | DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command); | 138 | DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command); |
254 | 139 | ||
255 | writeb(tf->command, (void __iomem *) ap->ioaddr.command_addr); | 140 | iowrite8(tf->command, ap->ioaddr.command_addr); |
256 | ata_pause(ap); | 141 | ata_pause(ap); |
257 | } | 142 | } |
258 | 143 | ||
259 | |||
260 | /** | ||
261 | * ata_exec_command - issue ATA command to host controller | ||
262 | * @ap: port to which command is being issued | ||
263 | * @tf: ATA taskfile register set | ||
264 | * | ||
265 | * Issues PIO/MMIO write to ATA command register, with proper | ||
266 | * synchronization with interrupt handler / other threads. | ||
267 | * | ||
268 | * LOCKING: | ||
269 | * spin_lock_irqsave(host lock) | ||
270 | */ | ||
271 | void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) | ||
272 | { | ||
273 | if (ap->flags & ATA_FLAG_MMIO) | ||
274 | ata_exec_command_mmio(ap, tf); | ||
275 | else | ||
276 | ata_exec_command_pio(ap, tf); | ||
277 | } | ||
278 | |||
279 | /** | 144 | /** |
280 | * ata_tf_read_pio - input device's ATA taskfile shadow registers | 145 | * ata_tf_read - input device's ATA taskfile shadow registers |
281 | * @ap: Port from which input is read | 146 | * @ap: Port from which input is read |
282 | * @tf: ATA taskfile register set for storing input | 147 | * @tf: ATA taskfile register set for storing input |
283 | * | 148 | * |
@@ -287,121 +152,28 @@ void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) | |||
287 | * LOCKING: | 152 | * LOCKING: |
288 | * Inherited from caller. | 153 | * Inherited from caller. |
289 | */ | 154 | */ |
290 | 155 | void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |
291 | static void ata_tf_read_pio(struct ata_port *ap, struct ata_taskfile *tf) | ||
292 | { | ||
293 | struct ata_ioports *ioaddr = &ap->ioaddr; | ||
294 | |||
295 | tf->command = ata_check_status(ap); | ||
296 | tf->feature = inb(ioaddr->error_addr); | ||
297 | tf->nsect = inb(ioaddr->nsect_addr); | ||
298 | tf->lbal = inb(ioaddr->lbal_addr); | ||
299 | tf->lbam = inb(ioaddr->lbam_addr); | ||
300 | tf->lbah = inb(ioaddr->lbah_addr); | ||
301 | tf->device = inb(ioaddr->device_addr); | ||
302 | |||
303 | if (tf->flags & ATA_TFLAG_LBA48) { | ||
304 | outb(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | ||
305 | tf->hob_feature = inb(ioaddr->error_addr); | ||
306 | tf->hob_nsect = inb(ioaddr->nsect_addr); | ||
307 | tf->hob_lbal = inb(ioaddr->lbal_addr); | ||
308 | tf->hob_lbam = inb(ioaddr->lbam_addr); | ||
309 | tf->hob_lbah = inb(ioaddr->lbah_addr); | ||
310 | } | ||
311 | } | ||
312 | |||
313 | /** | ||
314 | * ata_tf_read_mmio - input device's ATA taskfile shadow registers | ||
315 | * @ap: Port from which input is read | ||
316 | * @tf: ATA taskfile register set for storing input | ||
317 | * | ||
318 | * Reads ATA taskfile registers for currently-selected device | ||
319 | * into @tf via MMIO. | ||
320 | * | ||
321 | * LOCKING: | ||
322 | * Inherited from caller. | ||
323 | */ | ||
324 | |||
325 | static void ata_tf_read_mmio(struct ata_port *ap, struct ata_taskfile *tf) | ||
326 | { | 156 | { |
327 | struct ata_ioports *ioaddr = &ap->ioaddr; | 157 | struct ata_ioports *ioaddr = &ap->ioaddr; |
328 | 158 | ||
329 | tf->command = ata_check_status(ap); | 159 | tf->command = ata_check_status(ap); |
330 | tf->feature = readb((void __iomem *)ioaddr->error_addr); | 160 | tf->feature = ioread8(ioaddr->error_addr); |
331 | tf->nsect = readb((void __iomem *)ioaddr->nsect_addr); | 161 | tf->nsect = ioread8(ioaddr->nsect_addr); |
332 | tf->lbal = readb((void __iomem *)ioaddr->lbal_addr); | 162 | tf->lbal = ioread8(ioaddr->lbal_addr); |
333 | tf->lbam = readb((void __iomem *)ioaddr->lbam_addr); | 163 | tf->lbam = ioread8(ioaddr->lbam_addr); |
334 | tf->lbah = readb((void __iomem *)ioaddr->lbah_addr); | 164 | tf->lbah = ioread8(ioaddr->lbah_addr); |
335 | tf->device = readb((void __iomem *)ioaddr->device_addr); | 165 | tf->device = ioread8(ioaddr->device_addr); |
336 | 166 | ||
337 | if (tf->flags & ATA_TFLAG_LBA48) { | 167 | if (tf->flags & ATA_TFLAG_LBA48) { |
338 | writeb(tf->ctl | ATA_HOB, (void __iomem *) ap->ioaddr.ctl_addr); | 168 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); |
339 | tf->hob_feature = readb((void __iomem *)ioaddr->error_addr); | 169 | tf->hob_feature = ioread8(ioaddr->error_addr); |
340 | tf->hob_nsect = readb((void __iomem *)ioaddr->nsect_addr); | 170 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); |
341 | tf->hob_lbal = readb((void __iomem *)ioaddr->lbal_addr); | 171 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); |
342 | tf->hob_lbam = readb((void __iomem *)ioaddr->lbam_addr); | 172 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); |
343 | tf->hob_lbah = readb((void __iomem *)ioaddr->lbah_addr); | 173 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); |
344 | } | 174 | } |
345 | } | 175 | } |
346 | 176 | ||
347 | |||
348 | /** | ||
349 | * ata_tf_read - input device's ATA taskfile shadow registers | ||
350 | * @ap: Port from which input is read | ||
351 | * @tf: ATA taskfile register set for storing input | ||
352 | * | ||
353 | * Reads ATA taskfile registers for currently-selected device | ||
354 | * into @tf. | ||
355 | * | ||
356 | * Reads nsect, lbal, lbam, lbah, and device. If ATA_TFLAG_LBA48 | ||
357 | * is set, also reads the hob registers. | ||
358 | * | ||
359 | * May be used as the tf_read() entry in ata_port_operations. | ||
360 | * | ||
361 | * LOCKING: | ||
362 | * Inherited from caller. | ||
363 | */ | ||
364 | void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | ||
365 | { | ||
366 | if (ap->flags & ATA_FLAG_MMIO) | ||
367 | ata_tf_read_mmio(ap, tf); | ||
368 | else | ||
369 | ata_tf_read_pio(ap, tf); | ||
370 | } | ||
371 | |||
372 | /** | ||
373 | * ata_check_status_pio - Read device status reg & clear interrupt | ||
374 | * @ap: port where the device is | ||
375 | * | ||
376 | * Reads ATA taskfile status register for currently-selected device | ||
377 | * and return its value. This also clears pending interrupts | ||
378 | * from this device | ||
379 | * | ||
380 | * LOCKING: | ||
381 | * Inherited from caller. | ||
382 | */ | ||
383 | static u8 ata_check_status_pio(struct ata_port *ap) | ||
384 | { | ||
385 | return inb(ap->ioaddr.status_addr); | ||
386 | } | ||
387 | |||
388 | /** | ||
389 | * ata_check_status_mmio - Read device status reg & clear interrupt | ||
390 | * @ap: port where the device is | ||
391 | * | ||
392 | * Reads ATA taskfile status register for currently-selected device | ||
393 | * via MMIO and return its value. This also clears pending interrupts | ||
394 | * from this device | ||
395 | * | ||
396 | * LOCKING: | ||
397 | * Inherited from caller. | ||
398 | */ | ||
399 | static u8 ata_check_status_mmio(struct ata_port *ap) | ||
400 | { | ||
401 | return readb((void __iomem *) ap->ioaddr.status_addr); | ||
402 | } | ||
403 | |||
404 | |||
405 | /** | 177 | /** |
406 | * ata_check_status - Read device status reg & clear interrupt | 178 | * ata_check_status - Read device status reg & clear interrupt |
407 | * @ap: port where the device is | 179 | * @ap: port where the device is |
@@ -410,19 +182,14 @@ static u8 ata_check_status_mmio(struct ata_port *ap) | |||
410 | * and return its value. This also clears pending interrupts | 182 | * and return its value. This also clears pending interrupts |
411 | * from this device | 183 | * from this device |
412 | * | 184 | * |
413 | * May be used as the check_status() entry in ata_port_operations. | ||
414 | * | ||
415 | * LOCKING: | 185 | * LOCKING: |
416 | * Inherited from caller. | 186 | * Inherited from caller. |
417 | */ | 187 | */ |
418 | u8 ata_check_status(struct ata_port *ap) | 188 | u8 ata_check_status(struct ata_port *ap) |
419 | { | 189 | { |
420 | if (ap->flags & ATA_FLAG_MMIO) | 190 | return ioread8(ap->ioaddr.status_addr); |
421 | return ata_check_status_mmio(ap); | ||
422 | return ata_check_status_pio(ap); | ||
423 | } | 191 | } |
424 | 192 | ||
425 | |||
426 | /** | 193 | /** |
427 | * ata_altstatus - Read device alternate status reg | 194 | * ata_altstatus - Read device alternate status reg |
428 | * @ap: port where the device is | 195 | * @ap: port where the device is |
@@ -441,58 +208,52 @@ u8 ata_altstatus(struct ata_port *ap) | |||
441 | if (ap->ops->check_altstatus) | 208 | if (ap->ops->check_altstatus) |
442 | return ap->ops->check_altstatus(ap); | 209 | return ap->ops->check_altstatus(ap); |
443 | 210 | ||
444 | if (ap->flags & ATA_FLAG_MMIO) | 211 | return ioread8(ap->ioaddr.altstatus_addr); |
445 | return readb((void __iomem *)ap->ioaddr.altstatus_addr); | ||
446 | return inb(ap->ioaddr.altstatus_addr); | ||
447 | } | 212 | } |
448 | 213 | ||
449 | /** | 214 | /** |
450 | * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction | 215 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction |
451 | * @qc: Info associated with this ATA transaction. | 216 | * @qc: Info associated with this ATA transaction. |
452 | * | 217 | * |
453 | * LOCKING: | 218 | * LOCKING: |
454 | * spin_lock_irqsave(host lock) | 219 | * spin_lock_irqsave(host lock) |
455 | */ | 220 | */ |
456 | 221 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
457 | static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc) | ||
458 | { | 222 | { |
459 | struct ata_port *ap = qc->ap; | 223 | struct ata_port *ap = qc->ap; |
460 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | 224 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); |
461 | u8 dmactl; | 225 | u8 dmactl; |
462 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | ||
463 | 226 | ||
464 | /* load PRD table addr. */ | 227 | /* load PRD table addr. */ |
465 | mb(); /* make sure PRD table writes are visible to controller */ | 228 | mb(); /* make sure PRD table writes are visible to controller */ |
466 | writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS); | 229 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); |
467 | 230 | ||
468 | /* specify data direction, triple-check start bit is clear */ | 231 | /* specify data direction, triple-check start bit is clear */ |
469 | dmactl = readb(mmio + ATA_DMA_CMD); | 232 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
470 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | 233 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); |
471 | if (!rw) | 234 | if (!rw) |
472 | dmactl |= ATA_DMA_WR; | 235 | dmactl |= ATA_DMA_WR; |
473 | writeb(dmactl, mmio + ATA_DMA_CMD); | 236 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
474 | 237 | ||
475 | /* issue r/w command */ | 238 | /* issue r/w command */ |
476 | ap->ops->exec_command(ap, &qc->tf); | 239 | ap->ops->exec_command(ap, &qc->tf); |
477 | } | 240 | } |
478 | 241 | ||
479 | /** | 242 | /** |
480 | * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction | 243 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction |
481 | * @qc: Info associated with this ATA transaction. | 244 | * @qc: Info associated with this ATA transaction. |
482 | * | 245 | * |
483 | * LOCKING: | 246 | * LOCKING: |
484 | * spin_lock_irqsave(host lock) | 247 | * spin_lock_irqsave(host lock) |
485 | */ | 248 | */ |
486 | 249 | void ata_bmdma_start (struct ata_queued_cmd *qc) | |
487 | static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc) | ||
488 | { | 250 | { |
489 | struct ata_port *ap = qc->ap; | 251 | struct ata_port *ap = qc->ap; |
490 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | ||
491 | u8 dmactl; | 252 | u8 dmactl; |
492 | 253 | ||
493 | /* start host DMA transaction */ | 254 | /* start host DMA transaction */ |
494 | dmactl = readb(mmio + ATA_DMA_CMD); | 255 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
495 | writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); | 256 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
496 | 257 | ||
497 | /* Strictly, one may wish to issue a readb() here, to | 258 | /* Strictly, one may wish to issue a readb() here, to |
498 | * flush the mmio write. However, control also passes | 259 | * flush the mmio write. However, control also passes |
@@ -508,96 +269,6 @@ static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc) | |||
508 | } | 269 | } |
509 | 270 | ||
510 | /** | 271 | /** |
511 | * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO) | ||
512 | * @qc: Info associated with this ATA transaction. | ||
513 | * | ||
514 | * LOCKING: | ||
515 | * spin_lock_irqsave(host lock) | ||
516 | */ | ||
517 | |||
518 | static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc) | ||
519 | { | ||
520 | struct ata_port *ap = qc->ap; | ||
521 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | ||
522 | u8 dmactl; | ||
523 | |||
524 | /* load PRD table addr. */ | ||
525 | outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | ||
526 | |||
527 | /* specify data direction, triple-check start bit is clear */ | ||
528 | dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
529 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | ||
530 | if (!rw) | ||
531 | dmactl |= ATA_DMA_WR; | ||
532 | outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
533 | |||
534 | /* issue r/w command */ | ||
535 | ap->ops->exec_command(ap, &qc->tf); | ||
536 | } | ||
537 | |||
538 | /** | ||
539 | * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO) | ||
540 | * @qc: Info associated with this ATA transaction. | ||
541 | * | ||
542 | * LOCKING: | ||
543 | * spin_lock_irqsave(host lock) | ||
544 | */ | ||
545 | |||
546 | static void ata_bmdma_start_pio (struct ata_queued_cmd *qc) | ||
547 | { | ||
548 | struct ata_port *ap = qc->ap; | ||
549 | u8 dmactl; | ||
550 | |||
551 | /* start host DMA transaction */ | ||
552 | dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
553 | outb(dmactl | ATA_DMA_START, | ||
554 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
555 | } | ||
556 | |||
557 | |||
558 | /** | ||
559 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | ||
560 | * @qc: Info associated with this ATA transaction. | ||
561 | * | ||
562 | * Writes the ATA_DMA_START flag to the DMA command register. | ||
563 | * | ||
564 | * May be used as the bmdma_start() entry in ata_port_operations. | ||
565 | * | ||
566 | * LOCKING: | ||
567 | * spin_lock_irqsave(host lock) | ||
568 | */ | ||
569 | void ata_bmdma_start(struct ata_queued_cmd *qc) | ||
570 | { | ||
571 | if (qc->ap->flags & ATA_FLAG_MMIO) | ||
572 | ata_bmdma_start_mmio(qc); | ||
573 | else | ||
574 | ata_bmdma_start_pio(qc); | ||
575 | } | ||
576 | |||
577 | |||
578 | /** | ||
579 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | ||
580 | * @qc: Info associated with this ATA transaction. | ||
581 | * | ||
582 | * Writes address of PRD table to device's PRD Table Address | ||
583 | * register, sets the DMA control register, and calls | ||
584 | * ops->exec_command() to start the transfer. | ||
585 | * | ||
586 | * May be used as the bmdma_setup() entry in ata_port_operations. | ||
587 | * | ||
588 | * LOCKING: | ||
589 | * spin_lock_irqsave(host lock) | ||
590 | */ | ||
591 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | ||
592 | { | ||
593 | if (qc->ap->flags & ATA_FLAG_MMIO) | ||
594 | ata_bmdma_setup_mmio(qc); | ||
595 | else | ||
596 | ata_bmdma_setup_pio(qc); | ||
597 | } | ||
598 | |||
599 | |||
600 | /** | ||
601 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. | 272 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. |
602 | * @ap: Port associated with this ATA transaction. | 273 | * @ap: Port associated with this ATA transaction. |
603 | * | 274 | * |
@@ -608,23 +279,16 @@ void ata_bmdma_setup(struct ata_queued_cmd *qc) | |||
608 | * LOCKING: | 279 | * LOCKING: |
609 | * spin_lock_irqsave(host lock) | 280 | * spin_lock_irqsave(host lock) |
610 | */ | 281 | */ |
611 | |||
612 | void ata_bmdma_irq_clear(struct ata_port *ap) | 282 | void ata_bmdma_irq_clear(struct ata_port *ap) |
613 | { | 283 | { |
614 | if (!ap->ioaddr.bmdma_addr) | 284 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
285 | |||
286 | if (!mmio) | ||
615 | return; | 287 | return; |
616 | 288 | ||
617 | if (ap->flags & ATA_FLAG_MMIO) { | 289 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); |
618 | void __iomem *mmio = | ||
619 | ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS; | ||
620 | writeb(readb(mmio), mmio); | ||
621 | } else { | ||
622 | unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS; | ||
623 | outb(inb(addr), addr); | ||
624 | } | ||
625 | } | 290 | } |
626 | 291 | ||
627 | |||
628 | /** | 292 | /** |
629 | * ata_bmdma_status - Read PCI IDE BMDMA status | 293 | * ata_bmdma_status - Read PCI IDE BMDMA status |
630 | * @ap: Port associated with this ATA transaction. | 294 | * @ap: Port associated with this ATA transaction. |
@@ -636,19 +300,11 @@ void ata_bmdma_irq_clear(struct ata_port *ap) | |||
636 | * LOCKING: | 300 | * LOCKING: |
637 | * spin_lock_irqsave(host lock) | 301 | * spin_lock_irqsave(host lock) |
638 | */ | 302 | */ |
639 | |||
640 | u8 ata_bmdma_status(struct ata_port *ap) | 303 | u8 ata_bmdma_status(struct ata_port *ap) |
641 | { | 304 | { |
642 | u8 host_stat; | 305 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); |
643 | if (ap->flags & ATA_FLAG_MMIO) { | ||
644 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | ||
645 | host_stat = readb(mmio + ATA_DMA_STATUS); | ||
646 | } else | ||
647 | host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | ||
648 | return host_stat; | ||
649 | } | 306 | } |
650 | 307 | ||
651 | |||
652 | /** | 308 | /** |
653 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | 309 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer |
654 | * @qc: Command we are ending DMA for | 310 | * @qc: Command we are ending DMA for |
@@ -660,21 +316,14 @@ u8 ata_bmdma_status(struct ata_port *ap) | |||
660 | * LOCKING: | 316 | * LOCKING: |
661 | * spin_lock_irqsave(host lock) | 317 | * spin_lock_irqsave(host lock) |
662 | */ | 318 | */ |
663 | |||
664 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | 319 | void ata_bmdma_stop(struct ata_queued_cmd *qc) |
665 | { | 320 | { |
666 | struct ata_port *ap = qc->ap; | 321 | struct ata_port *ap = qc->ap; |
667 | if (ap->flags & ATA_FLAG_MMIO) { | 322 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
668 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | ||
669 | 323 | ||
670 | /* clear start/stop bit */ | 324 | /* clear start/stop bit */ |
671 | writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | 325 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, |
672 | mmio + ATA_DMA_CMD); | 326 | mmio + ATA_DMA_CMD); |
673 | } else { | ||
674 | /* clear start/stop bit */ | ||
675 | outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START, | ||
676 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
677 | } | ||
678 | 327 | ||
679 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | 328 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ |
680 | ata_altstatus(ap); /* dummy read */ | 329 | ata_altstatus(ap); /* dummy read */ |
@@ -696,10 +345,7 @@ void ata_bmdma_freeze(struct ata_port *ap) | |||
696 | ap->ctl |= ATA_NIEN; | 345 | ap->ctl |= ATA_NIEN; |
697 | ap->last_ctl = ap->ctl; | 346 | ap->last_ctl = ap->ctl; |
698 | 347 | ||
699 | if (ap->flags & ATA_FLAG_MMIO) | 348 | iowrite8(ap->ctl, ioaddr->ctl_addr); |
700 | writeb(ap->ctl, (void __iomem *)ioaddr->ctl_addr); | ||
701 | else | ||
702 | outb(ap->ctl, ioaddr->ctl_addr); | ||
703 | 349 | ||
704 | /* Under certain circumstances, some controllers raise IRQ on | 350 | /* Under certain circumstances, some controllers raise IRQ on |
705 | * ATA_NIEN manipulation. Also, many controllers fail to mask | 351 | * ATA_NIEN manipulation. Also, many controllers fail to mask |
@@ -868,11 +514,24 @@ static int ata_resources_present(struct pci_dev *pdev, int port) | |||
868 | struct ata_probe_ent * | 514 | struct ata_probe_ent * |
869 | ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports) | 515 | ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports) |
870 | { | 516 | { |
871 | struct ata_probe_ent *probe_ent = | 517 | struct ata_probe_ent *probe_ent; |
872 | ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); | 518 | int i, p = 0; |
873 | int p = 0; | 519 | void __iomem * const *iomap; |
874 | unsigned long bmdma; | 520 | |
521 | /* iomap BARs */ | ||
522 | for (i = 0; i < 4; i++) { | ||
523 | if (pcim_iomap(pdev, i, 0) == NULL) { | ||
524 | dev_printk(KERN_ERR, &pdev->dev, | ||
525 | "failed to iomap PCI BAR %d\n", i); | ||
526 | return NULL; | ||
527 | } | ||
528 | } | ||
529 | |||
530 | pcim_iomap(pdev, 4, 0); /* may fail */ | ||
531 | iomap = pcim_iomap_table(pdev); | ||
875 | 532 | ||
533 | /* alloc and init probe_ent */ | ||
534 | probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); | ||
876 | if (!probe_ent) | 535 | if (!probe_ent) |
877 | return NULL; | 536 | return NULL; |
878 | 537 | ||
@@ -887,33 +546,30 @@ ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int | |||
887 | ports &= ~ATA_PORT_SECONDARY; | 546 | ports &= ~ATA_PORT_SECONDARY; |
888 | 547 | ||
889 | if (ports & ATA_PORT_PRIMARY) { | 548 | if (ports & ATA_PORT_PRIMARY) { |
890 | probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 0); | 549 | probe_ent->port[p].cmd_addr = iomap[0]; |
891 | probe_ent->port[p].altstatus_addr = | 550 | probe_ent->port[p].altstatus_addr = |
892 | probe_ent->port[p].ctl_addr = | 551 | probe_ent->port[p].ctl_addr = (void __iomem *) |
893 | pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS; | 552 | ((unsigned long)iomap[1] | ATA_PCI_CTL_OFS); |
894 | bmdma = pci_resource_start(pdev, 4); | 553 | if (iomap[4]) { |
895 | if (bmdma) { | ||
896 | if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && | 554 | if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
897 | (inb(bmdma + 2) & 0x80)) | 555 | (ioread8(iomap[4] + 2) & 0x80)) |
898 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; | 556 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
899 | probe_ent->port[p].bmdma_addr = bmdma; | 557 | probe_ent->port[p].bmdma_addr = iomap[4]; |
900 | } | 558 | } |
901 | ata_std_ports(&probe_ent->port[p]); | 559 | ata_std_ports(&probe_ent->port[p]); |
902 | p++; | 560 | p++; |
903 | } | 561 | } |
904 | 562 | ||
905 | if (ports & ATA_PORT_SECONDARY) { | 563 | if (ports & ATA_PORT_SECONDARY) { |
906 | probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 2); | 564 | probe_ent->port[p].cmd_addr = iomap[2]; |
907 | probe_ent->port[p].altstatus_addr = | 565 | probe_ent->port[p].altstatus_addr = |
908 | probe_ent->port[p].ctl_addr = | 566 | probe_ent->port[p].ctl_addr = (void __iomem *) |
909 | pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS; | 567 | ((unsigned long)iomap[3] | ATA_PCI_CTL_OFS); |
910 | bmdma = pci_resource_start(pdev, 4); | 568 | if (iomap[4]) { |
911 | if (bmdma) { | ||
912 | bmdma += 8; | ||
913 | if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && | 569 | if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
914 | (inb(bmdma + 2) & 0x80)) | 570 | (ioread8(iomap[4] + 10) & 0x80)) |
915 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; | 571 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
916 | probe_ent->port[p].bmdma_addr = bmdma; | 572 | probe_ent->port[p].bmdma_addr = iomap[4] + 8; |
917 | } | 573 | } |
918 | ata_std_ports(&probe_ent->port[p]); | 574 | ata_std_ports(&probe_ent->port[p]); |
919 | probe_ent->pinfo2 = port[1]; | 575 | probe_ent->pinfo2 = port[1]; |
@@ -924,13 +580,29 @@ ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int | |||
924 | return probe_ent; | 580 | return probe_ent; |
925 | } | 581 | } |
926 | 582 | ||
927 | |||
928 | static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, | 583 | static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, |
929 | struct ata_port_info **port, int port_mask) | 584 | struct ata_port_info **port, int port_mask) |
930 | { | 585 | { |
931 | struct ata_probe_ent *probe_ent; | 586 | struct ata_probe_ent *probe_ent; |
932 | unsigned long bmdma = pci_resource_start(pdev, 4); | 587 | void __iomem *iomap[5] = { }, *bmdma; |
588 | |||
589 | if (port_mask & ATA_PORT_PRIMARY) { | ||
590 | iomap[0] = devm_ioport_map(&pdev->dev, ATA_PRIMARY_CMD, 8); | ||
591 | iomap[1] = devm_ioport_map(&pdev->dev, ATA_PRIMARY_CTL, 1); | ||
592 | if (!iomap[0] || !iomap[1]) | ||
593 | return NULL; | ||
594 | } | ||
595 | |||
596 | if (port_mask & ATA_PORT_SECONDARY) { | ||
597 | iomap[2] = devm_ioport_map(&pdev->dev, ATA_SECONDARY_CMD, 8); | ||
598 | iomap[3] = devm_ioport_map(&pdev->dev, ATA_SECONDARY_CTL, 1); | ||
599 | if (!iomap[2] || !iomap[3]) | ||
600 | return NULL; | ||
601 | } | ||
602 | |||
603 | bmdma = pcim_iomap(pdev, 4, 16); /* may fail */ | ||
933 | 604 | ||
605 | /* alloc and init probe_ent */ | ||
934 | probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); | 606 | probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); |
935 | if (!probe_ent) | 607 | if (!probe_ent) |
936 | return NULL; | 608 | return NULL; |
@@ -940,13 +612,13 @@ static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, | |||
940 | 612 | ||
941 | if (port_mask & ATA_PORT_PRIMARY) { | 613 | if (port_mask & ATA_PORT_PRIMARY) { |
942 | probe_ent->irq = ATA_PRIMARY_IRQ(pdev); | 614 | probe_ent->irq = ATA_PRIMARY_IRQ(pdev); |
943 | probe_ent->port[0].cmd_addr = ATA_PRIMARY_CMD; | 615 | probe_ent->port[0].cmd_addr = iomap[0]; |
944 | probe_ent->port[0].altstatus_addr = | 616 | probe_ent->port[0].altstatus_addr = |
945 | probe_ent->port[0].ctl_addr = ATA_PRIMARY_CTL; | 617 | probe_ent->port[0].ctl_addr = iomap[1]; |
946 | if (bmdma) { | 618 | if (bmdma) { |
947 | probe_ent->port[0].bmdma_addr = bmdma; | 619 | probe_ent->port[0].bmdma_addr = bmdma; |
948 | if ((!(port[0]->flags & ATA_FLAG_IGN_SIMPLEX)) && | 620 | if ((!(port[0]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
949 | (inb(bmdma + 2) & 0x80)) | 621 | (ioread8(bmdma + 2) & 0x80)) |
950 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; | 622 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
951 | } | 623 | } |
952 | ata_std_ports(&probe_ent->port[0]); | 624 | ata_std_ports(&probe_ent->port[0]); |
@@ -958,13 +630,13 @@ static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, | |||
958 | probe_ent->irq2 = ATA_SECONDARY_IRQ(pdev); | 630 | probe_ent->irq2 = ATA_SECONDARY_IRQ(pdev); |
959 | else | 631 | else |
960 | probe_ent->irq = ATA_SECONDARY_IRQ(pdev); | 632 | probe_ent->irq = ATA_SECONDARY_IRQ(pdev); |
961 | probe_ent->port[1].cmd_addr = ATA_SECONDARY_CMD; | 633 | probe_ent->port[1].cmd_addr = iomap[2]; |
962 | probe_ent->port[1].altstatus_addr = | 634 | probe_ent->port[1].altstatus_addr = |
963 | probe_ent->port[1].ctl_addr = ATA_SECONDARY_CTL; | 635 | probe_ent->port[1].ctl_addr = iomap[3]; |
964 | if (bmdma) { | 636 | if (bmdma) { |
965 | probe_ent->port[1].bmdma_addr = bmdma + 8; | 637 | probe_ent->port[1].bmdma_addr = bmdma + 8; |
966 | if ((!(port[1]->flags & ATA_FLAG_IGN_SIMPLEX)) && | 638 | if ((!(port[1]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
967 | (inb(bmdma + 10) & 0x80)) | 639 | (ioread8(bmdma + 10) & 0x80)) |
968 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; | 640 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
969 | } | 641 | } |
970 | ata_std_ports(&probe_ent->port[1]); | 642 | ata_std_ports(&probe_ent->port[1]); |