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authorAnton Vorontsov <avorontsov@ru.mvista.com>2010-03-28 00:22:14 -0400
committerJeff Garzik <jgarzik@redhat.com>2010-05-14 17:08:01 -0400
commit365cfa1ed5a36f9bcb9f64c9f0f52155af2e9fef (patch)
treedcafbc73e4232ac9cfd65d25c2c7da8fa5390976 /drivers/ata/libahci.c
parent0cbb0e774b0ea0547ec1b9e795637e309327ae27 (diff)
ahci: Move generic code into libahci
This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/ata/libahci.c')
-rw-r--r--drivers/ata/libahci.c2091
1 files changed, 2091 insertions, 0 deletions
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
new file mode 100644
index 000000000000..38e1b4e9ecf4
--- /dev/null
+++ b/drivers/ata/libahci.c
@@ -0,0 +1,2091 @@
1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <scsi/scsi_host.h>
44#include <scsi/scsi_cmnd.h>
45#include <linux/libata.h>
46#include "ahci.h"
47
48static int ahci_skip_host_reset;
49int ahci_ignore_sss;
50EXPORT_SYMBOL_GPL(ahci_ignore_sss);
51
52module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
53MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
54
55module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
56MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
57
58static int ahci_enable_alpm(struct ata_port *ap,
59 enum link_pm policy);
60static void ahci_disable_alpm(struct ata_port *ap);
61static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
63 size_t size);
64static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
65 ssize_t size);
66
67
68
69static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
72static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73static int ahci_port_start(struct ata_port *ap);
74static void ahci_port_stop(struct ata_port *ap);
75static void ahci_qc_prep(struct ata_queued_cmd *qc);
76static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77static void ahci_freeze(struct ata_port *ap);
78static void ahci_thaw(struct ata_port *ap);
79static void ahci_enable_fbs(struct ata_port *ap);
80static void ahci_disable_fbs(struct ata_port *ap);
81static void ahci_pmp_attach(struct ata_port *ap);
82static void ahci_pmp_detach(struct ata_port *ap);
83static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87static void ahci_postreset(struct ata_link *link, unsigned int *class);
88static void ahci_error_handler(struct ata_port *ap);
89static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
90static int ahci_port_resume(struct ata_port *ap);
91static void ahci_dev_config(struct ata_device *dev);
92static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
93 u32 opts);
94#ifdef CONFIG_PM
95static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96#endif
97static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100static void ahci_init_sw_activity(struct ata_link *link);
101
102static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
110
111static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
112static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
113static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
114static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
115
116static struct device_attribute *ahci_shost_attrs[] = {
117 &dev_attr_link_power_management_policy,
118 &dev_attr_em_message_type,
119 &dev_attr_em_message,
120 &dev_attr_ahci_host_caps,
121 &dev_attr_ahci_host_cap2,
122 &dev_attr_ahci_host_version,
123 &dev_attr_ahci_port_cmd,
124 NULL
125};
126
127static struct device_attribute *ahci_sdev_attrs[] = {
128 &dev_attr_sw_activity,
129 &dev_attr_unload_heads,
130 NULL
131};
132
133struct scsi_host_template ahci_sht = {
134 ATA_NCQ_SHT("ahci"),
135 .can_queue = AHCI_MAX_CMDS - 1,
136 .sg_tablesize = AHCI_MAX_SG,
137 .dma_boundary = AHCI_DMA_BOUNDARY,
138 .shost_attrs = ahci_shost_attrs,
139 .sdev_attrs = ahci_sdev_attrs,
140};
141EXPORT_SYMBOL_GPL(ahci_sht);
142
143struct ata_port_operations ahci_ops = {
144 .inherits = &sata_pmp_port_ops,
145
146 .qc_defer = ahci_pmp_qc_defer,
147 .qc_prep = ahci_qc_prep,
148 .qc_issue = ahci_qc_issue,
149 .qc_fill_rtf = ahci_qc_fill_rtf,
150
151 .freeze = ahci_freeze,
152 .thaw = ahci_thaw,
153 .softreset = ahci_softreset,
154 .hardreset = ahci_hardreset,
155 .postreset = ahci_postreset,
156 .pmp_softreset = ahci_softreset,
157 .error_handler = ahci_error_handler,
158 .post_internal_cmd = ahci_post_internal_cmd,
159 .dev_config = ahci_dev_config,
160
161 .scr_read = ahci_scr_read,
162 .scr_write = ahci_scr_write,
163 .pmp_attach = ahci_pmp_attach,
164 .pmp_detach = ahci_pmp_detach,
165
166 .enable_pm = ahci_enable_alpm,
167 .disable_pm = ahci_disable_alpm,
168 .em_show = ahci_led_show,
169 .em_store = ahci_led_store,
170 .sw_activity_show = ahci_activity_show,
171 .sw_activity_store = ahci_activity_store,
172#ifdef CONFIG_PM
173 .port_suspend = ahci_port_suspend,
174 .port_resume = ahci_port_resume,
175#endif
176 .port_start = ahci_port_start,
177 .port_stop = ahci_port_stop,
178};
179EXPORT_SYMBOL_GPL(ahci_ops);
180
181int ahci_em_messages = 1;
182EXPORT_SYMBOL_GPL(ahci_em_messages);
183module_param(ahci_em_messages, int, 0444);
184/* add other LED protocol types when they become supported */
185MODULE_PARM_DESC(ahci_em_messages,
186 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
187
188static void ahci_enable_ahci(void __iomem *mmio)
189{
190 int i;
191 u32 tmp;
192
193 /* turn on AHCI_EN */
194 tmp = readl(mmio + HOST_CTL);
195 if (tmp & HOST_AHCI_EN)
196 return;
197
198 /* Some controllers need AHCI_EN to be written multiple times.
199 * Try a few times before giving up.
200 */
201 for (i = 0; i < 5; i++) {
202 tmp |= HOST_AHCI_EN;
203 writel(tmp, mmio + HOST_CTL);
204 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
205 if (tmp & HOST_AHCI_EN)
206 return;
207 msleep(10);
208 }
209
210 WARN_ON(1);
211}
212
213static ssize_t ahci_show_host_caps(struct device *dev,
214 struct device_attribute *attr, char *buf)
215{
216 struct Scsi_Host *shost = class_to_shost(dev);
217 struct ata_port *ap = ata_shost_to_port(shost);
218 struct ahci_host_priv *hpriv = ap->host->private_data;
219
220 return sprintf(buf, "%x\n", hpriv->cap);
221}
222
223static ssize_t ahci_show_host_cap2(struct device *dev,
224 struct device_attribute *attr, char *buf)
225{
226 struct Scsi_Host *shost = class_to_shost(dev);
227 struct ata_port *ap = ata_shost_to_port(shost);
228 struct ahci_host_priv *hpriv = ap->host->private_data;
229
230 return sprintf(buf, "%x\n", hpriv->cap2);
231}
232
233static ssize_t ahci_show_host_version(struct device *dev,
234 struct device_attribute *attr, char *buf)
235{
236 struct Scsi_Host *shost = class_to_shost(dev);
237 struct ata_port *ap = ata_shost_to_port(shost);
238 struct ahci_host_priv *hpriv = ap->host->private_data;
239 void __iomem *mmio = hpriv->mmio;
240
241 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
242}
243
244static ssize_t ahci_show_port_cmd(struct device *dev,
245 struct device_attribute *attr, char *buf)
246{
247 struct Scsi_Host *shost = class_to_shost(dev);
248 struct ata_port *ap = ata_shost_to_port(shost);
249 void __iomem *port_mmio = ahci_port_base(ap);
250
251 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
252}
253
254/**
255 * ahci_save_initial_config - Save and fixup initial config values
256 * @dev: target AHCI device
257 * @hpriv: host private area to store config values
258 * @force_port_map: force port map to a specified value
259 * @mask_port_map: mask out particular bits from port map
260 *
261 * Some registers containing configuration info might be setup by
262 * BIOS and might be cleared on reset. This function saves the
263 * initial values of those registers into @hpriv such that they
264 * can be restored after controller reset.
265 *
266 * If inconsistent, config values are fixed up by this function.
267 *
268 * LOCKING:
269 * None.
270 */
271void ahci_save_initial_config(struct device *dev,
272 struct ahci_host_priv *hpriv,
273 unsigned int force_port_map,
274 unsigned int mask_port_map)
275{
276 void __iomem *mmio = hpriv->mmio;
277 u32 cap, cap2, vers, port_map;
278 int i;
279
280 /* make sure AHCI mode is enabled before accessing CAP */
281 ahci_enable_ahci(mmio);
282
283 /* Values prefixed with saved_ are written back to host after
284 * reset. Values without are used for driver operation.
285 */
286 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
287 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
288
289 /* CAP2 register is only defined for AHCI 1.2 and later */
290 vers = readl(mmio + HOST_VERSION);
291 if ((vers >> 16) > 1 ||
292 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
293 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
294 else
295 hpriv->saved_cap2 = cap2 = 0;
296
297 /* some chips have errata preventing 64bit use */
298 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
299 dev_printk(KERN_INFO, dev,
300 "controller can't do 64bit DMA, forcing 32bit\n");
301 cap &= ~HOST_CAP_64;
302 }
303
304 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
305 dev_printk(KERN_INFO, dev,
306 "controller can't do NCQ, turning off CAP_NCQ\n");
307 cap &= ~HOST_CAP_NCQ;
308 }
309
310 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
311 dev_printk(KERN_INFO, dev,
312 "controller can do NCQ, turning on CAP_NCQ\n");
313 cap |= HOST_CAP_NCQ;
314 }
315
316 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
317 dev_printk(KERN_INFO, dev,
318 "controller can't do PMP, turning off CAP_PMP\n");
319 cap &= ~HOST_CAP_PMP;
320 }
321
322 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
323 dev_printk(KERN_INFO, dev,
324 "controller can't do SNTF, turning off CAP_SNTF\n");
325 cap &= ~HOST_CAP_SNTF;
326 }
327
328 if (force_port_map && port_map != force_port_map) {
329 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
330 port_map, force_port_map);
331 port_map = force_port_map;
332 }
333
334 if (mask_port_map) {
335 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
336 port_map,
337 port_map & mask_port_map);
338 port_map &= mask_port_map;
339 }
340
341 /* cross check port_map and cap.n_ports */
342 if (port_map) {
343 int map_ports = 0;
344
345 for (i = 0; i < AHCI_MAX_PORTS; i++)
346 if (port_map & (1 << i))
347 map_ports++;
348
349 /* If PI has more ports than n_ports, whine, clear
350 * port_map and let it be generated from n_ports.
351 */
352 if (map_ports > ahci_nr_ports(cap)) {
353 dev_printk(KERN_WARNING, dev,
354 "implemented port map (0x%x) contains more "
355 "ports than nr_ports (%u), using nr_ports\n",
356 port_map, ahci_nr_ports(cap));
357 port_map = 0;
358 }
359 }
360
361 /* fabricate port_map from cap.nr_ports */
362 if (!port_map) {
363 port_map = (1 << ahci_nr_ports(cap)) - 1;
364 dev_printk(KERN_WARNING, dev,
365 "forcing PORTS_IMPL to 0x%x\n", port_map);
366
367 /* write the fixed up value to the PI register */
368 hpriv->saved_port_map = port_map;
369 }
370
371 /* record values to use during operation */
372 hpriv->cap = cap;
373 hpriv->cap2 = cap2;
374 hpriv->port_map = port_map;
375}
376EXPORT_SYMBOL_GPL(ahci_save_initial_config);
377
378/**
379 * ahci_restore_initial_config - Restore initial config
380 * @host: target ATA host
381 *
382 * Restore initial config stored by ahci_save_initial_config().
383 *
384 * LOCKING:
385 * None.
386 */
387static void ahci_restore_initial_config(struct ata_host *host)
388{
389 struct ahci_host_priv *hpriv = host->private_data;
390 void __iomem *mmio = hpriv->mmio;
391
392 writel(hpriv->saved_cap, mmio + HOST_CAP);
393 if (hpriv->saved_cap2)
394 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
395 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
396 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
397}
398
399static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
400{
401 static const int offset[] = {
402 [SCR_STATUS] = PORT_SCR_STAT,
403 [SCR_CONTROL] = PORT_SCR_CTL,
404 [SCR_ERROR] = PORT_SCR_ERR,
405 [SCR_ACTIVE] = PORT_SCR_ACT,
406 [SCR_NOTIFICATION] = PORT_SCR_NTF,
407 };
408 struct ahci_host_priv *hpriv = ap->host->private_data;
409
410 if (sc_reg < ARRAY_SIZE(offset) &&
411 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
412 return offset[sc_reg];
413 return 0;
414}
415
416static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
417{
418 void __iomem *port_mmio = ahci_port_base(link->ap);
419 int offset = ahci_scr_offset(link->ap, sc_reg);
420
421 if (offset) {
422 *val = readl(port_mmio + offset);
423 return 0;
424 }
425 return -EINVAL;
426}
427
428static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
429{
430 void __iomem *port_mmio = ahci_port_base(link->ap);
431 int offset = ahci_scr_offset(link->ap, sc_reg);
432
433 if (offset) {
434 writel(val, port_mmio + offset);
435 return 0;
436 }
437 return -EINVAL;
438}
439
440void ahci_start_engine(struct ata_port *ap)
441{
442 void __iomem *port_mmio = ahci_port_base(ap);
443 u32 tmp;
444
445 /* start DMA */
446 tmp = readl(port_mmio + PORT_CMD);
447 tmp |= PORT_CMD_START;
448 writel(tmp, port_mmio + PORT_CMD);
449 readl(port_mmio + PORT_CMD); /* flush */
450}
451EXPORT_SYMBOL_GPL(ahci_start_engine);
452
453int ahci_stop_engine(struct ata_port *ap)
454{
455 void __iomem *port_mmio = ahci_port_base(ap);
456 u32 tmp;
457
458 tmp = readl(port_mmio + PORT_CMD);
459
460 /* check if the HBA is idle */
461 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
462 return 0;
463
464 /* setting HBA to idle */
465 tmp &= ~PORT_CMD_START;
466 writel(tmp, port_mmio + PORT_CMD);
467
468 /* wait for engine to stop. This could be as long as 500 msec */
469 tmp = ata_wait_register(port_mmio + PORT_CMD,
470 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
471 if (tmp & PORT_CMD_LIST_ON)
472 return -EIO;
473
474 return 0;
475}
476EXPORT_SYMBOL_GPL(ahci_stop_engine);
477
478static void ahci_start_fis_rx(struct ata_port *ap)
479{
480 void __iomem *port_mmio = ahci_port_base(ap);
481 struct ahci_host_priv *hpriv = ap->host->private_data;
482 struct ahci_port_priv *pp = ap->private_data;
483 u32 tmp;
484
485 /* set FIS registers */
486 if (hpriv->cap & HOST_CAP_64)
487 writel((pp->cmd_slot_dma >> 16) >> 16,
488 port_mmio + PORT_LST_ADDR_HI);
489 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
490
491 if (hpriv->cap & HOST_CAP_64)
492 writel((pp->rx_fis_dma >> 16) >> 16,
493 port_mmio + PORT_FIS_ADDR_HI);
494 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
495
496 /* enable FIS reception */
497 tmp = readl(port_mmio + PORT_CMD);
498 tmp |= PORT_CMD_FIS_RX;
499 writel(tmp, port_mmio + PORT_CMD);
500
501 /* flush */
502 readl(port_mmio + PORT_CMD);
503}
504
505static int ahci_stop_fis_rx(struct ata_port *ap)
506{
507 void __iomem *port_mmio = ahci_port_base(ap);
508 u32 tmp;
509
510 /* disable FIS reception */
511 tmp = readl(port_mmio + PORT_CMD);
512 tmp &= ~PORT_CMD_FIS_RX;
513 writel(tmp, port_mmio + PORT_CMD);
514
515 /* wait for completion, spec says 500ms, give it 1000 */
516 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
517 PORT_CMD_FIS_ON, 10, 1000);
518 if (tmp & PORT_CMD_FIS_ON)
519 return -EBUSY;
520
521 return 0;
522}
523
524static void ahci_power_up(struct ata_port *ap)
525{
526 struct ahci_host_priv *hpriv = ap->host->private_data;
527 void __iomem *port_mmio = ahci_port_base(ap);
528 u32 cmd;
529
530 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
531
532 /* spin up device */
533 if (hpriv->cap & HOST_CAP_SSS) {
534 cmd |= PORT_CMD_SPIN_UP;
535 writel(cmd, port_mmio + PORT_CMD);
536 }
537
538 /* wake up link */
539 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
540}
541
542static void ahci_disable_alpm(struct ata_port *ap)
543{
544 struct ahci_host_priv *hpriv = ap->host->private_data;
545 void __iomem *port_mmio = ahci_port_base(ap);
546 u32 cmd;
547 struct ahci_port_priv *pp = ap->private_data;
548
549 /* IPM bits should be disabled by libata-core */
550 /* get the existing command bits */
551 cmd = readl(port_mmio + PORT_CMD);
552
553 /* disable ALPM and ASP */
554 cmd &= ~PORT_CMD_ASP;
555 cmd &= ~PORT_CMD_ALPE;
556
557 /* force the interface back to active */
558 cmd |= PORT_CMD_ICC_ACTIVE;
559
560 /* write out new cmd value */
561 writel(cmd, port_mmio + PORT_CMD);
562 cmd = readl(port_mmio + PORT_CMD);
563
564 /* wait 10ms to be sure we've come out of any low power state */
565 msleep(10);
566
567 /* clear out any PhyRdy stuff from interrupt status */
568 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
569
570 /* go ahead and clean out PhyRdy Change from Serror too */
571 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
572
573 /*
574 * Clear flag to indicate that we should ignore all PhyRdy
575 * state changes
576 */
577 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
578
579 /*
580 * Enable interrupts on Phy Ready.
581 */
582 pp->intr_mask |= PORT_IRQ_PHYRDY;
583 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
584
585 /*
586 * don't change the link pm policy - we can be called
587 * just to turn of link pm temporarily
588 */
589}
590
591static int ahci_enable_alpm(struct ata_port *ap,
592 enum link_pm policy)
593{
594 struct ahci_host_priv *hpriv = ap->host->private_data;
595 void __iomem *port_mmio = ahci_port_base(ap);
596 u32 cmd;
597 struct ahci_port_priv *pp = ap->private_data;
598 u32 asp;
599
600 /* Make sure the host is capable of link power management */
601 if (!(hpriv->cap & HOST_CAP_ALPM))
602 return -EINVAL;
603
604 switch (policy) {
605 case MAX_PERFORMANCE:
606 case NOT_AVAILABLE:
607 /*
608 * if we came here with NOT_AVAILABLE,
609 * it just means this is the first time we
610 * have tried to enable - default to max performance,
611 * and let the user go to lower power modes on request.
612 */
613 ahci_disable_alpm(ap);
614 return 0;
615 case MIN_POWER:
616 /* configure HBA to enter SLUMBER */
617 asp = PORT_CMD_ASP;
618 break;
619 case MEDIUM_POWER:
620 /* configure HBA to enter PARTIAL */
621 asp = 0;
622 break;
623 default:
624 return -EINVAL;
625 }
626
627 /*
628 * Disable interrupts on Phy Ready. This keeps us from
629 * getting woken up due to spurious phy ready interrupts
630 * TBD - Hot plug should be done via polling now, is
631 * that even supported?
632 */
633 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
634 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
635
636 /*
637 * Set a flag to indicate that we should ignore all PhyRdy
638 * state changes since these can happen now whenever we
639 * change link state
640 */
641 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
642
643 /* get the existing command bits */
644 cmd = readl(port_mmio + PORT_CMD);
645
646 /*
647 * Set ASP based on Policy
648 */
649 cmd |= asp;
650
651 /*
652 * Setting this bit will instruct the HBA to aggressively
653 * enter a lower power link state when it's appropriate and
654 * based on the value set above for ASP
655 */
656 cmd |= PORT_CMD_ALPE;
657
658 /* write out new cmd value */
659 writel(cmd, port_mmio + PORT_CMD);
660 cmd = readl(port_mmio + PORT_CMD);
661
662 /* IPM bits should be set by libata-core */
663 return 0;
664}
665
666#ifdef CONFIG_PM
667static void ahci_power_down(struct ata_port *ap)
668{
669 struct ahci_host_priv *hpriv = ap->host->private_data;
670 void __iomem *port_mmio = ahci_port_base(ap);
671 u32 cmd, scontrol;
672
673 if (!(hpriv->cap & HOST_CAP_SSS))
674 return;
675
676 /* put device into listen mode, first set PxSCTL.DET to 0 */
677 scontrol = readl(port_mmio + PORT_SCR_CTL);
678 scontrol &= ~0xf;
679 writel(scontrol, port_mmio + PORT_SCR_CTL);
680
681 /* then set PxCMD.SUD to 0 */
682 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
683 cmd &= ~PORT_CMD_SPIN_UP;
684 writel(cmd, port_mmio + PORT_CMD);
685}
686#endif
687
688static void ahci_start_port(struct ata_port *ap)
689{
690 struct ahci_port_priv *pp = ap->private_data;
691 struct ata_link *link;
692 struct ahci_em_priv *emp;
693 ssize_t rc;
694 int i;
695
696 /* enable FIS reception */
697 ahci_start_fis_rx(ap);
698
699 /* enable DMA */
700 ahci_start_engine(ap);
701
702 /* turn on LEDs */
703 if (ap->flags & ATA_FLAG_EM) {
704 ata_for_each_link(link, ap, EDGE) {
705 emp = &pp->em_priv[link->pmp];
706
707 /* EM Transmit bit maybe busy during init */
708 for (i = 0; i < EM_MAX_RETRY; i++) {
709 rc = ahci_transmit_led_message(ap,
710 emp->led_state,
711 4);
712 if (rc == -EBUSY)
713 msleep(1);
714 else
715 break;
716 }
717 }
718 }
719
720 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
721 ata_for_each_link(link, ap, EDGE)
722 ahci_init_sw_activity(link);
723
724}
725
726static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
727{
728 int rc;
729
730 /* disable DMA */
731 rc = ahci_stop_engine(ap);
732 if (rc) {
733 *emsg = "failed to stop engine";
734 return rc;
735 }
736
737 /* disable FIS reception */
738 rc = ahci_stop_fis_rx(ap);
739 if (rc) {
740 *emsg = "failed stop FIS RX";
741 return rc;
742 }
743
744 return 0;
745}
746
747int ahci_reset_controller(struct ata_host *host)
748{
749 struct ahci_host_priv *hpriv = host->private_data;
750 void __iomem *mmio = hpriv->mmio;
751 u32 tmp;
752
753 /* we must be in AHCI mode, before using anything
754 * AHCI-specific, such as HOST_RESET.
755 */
756 ahci_enable_ahci(mmio);
757
758 /* global controller reset */
759 if (!ahci_skip_host_reset) {
760 tmp = readl(mmio + HOST_CTL);
761 if ((tmp & HOST_RESET) == 0) {
762 writel(tmp | HOST_RESET, mmio + HOST_CTL);
763 readl(mmio + HOST_CTL); /* flush */
764 }
765
766 /*
767 * to perform host reset, OS should set HOST_RESET
768 * and poll until this bit is read to be "0".
769 * reset must complete within 1 second, or
770 * the hardware should be considered fried.
771 */
772 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
773 HOST_RESET, 10, 1000);
774
775 if (tmp & HOST_RESET) {
776 dev_printk(KERN_ERR, host->dev,
777 "controller reset failed (0x%x)\n", tmp);
778 return -EIO;
779 }
780
781 /* turn on AHCI mode */
782 ahci_enable_ahci(mmio);
783
784 /* Some registers might be cleared on reset. Restore
785 * initial values.
786 */
787 ahci_restore_initial_config(host);
788 } else
789 dev_printk(KERN_INFO, host->dev,
790 "skipping global host reset\n");
791
792 return 0;
793}
794EXPORT_SYMBOL_GPL(ahci_reset_controller);
795
796static void ahci_sw_activity(struct ata_link *link)
797{
798 struct ata_port *ap = link->ap;
799 struct ahci_port_priv *pp = ap->private_data;
800 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
801
802 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
803 return;
804
805 emp->activity++;
806 if (!timer_pending(&emp->timer))
807 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
808}
809
810static void ahci_sw_activity_blink(unsigned long arg)
811{
812 struct ata_link *link = (struct ata_link *)arg;
813 struct ata_port *ap = link->ap;
814 struct ahci_port_priv *pp = ap->private_data;
815 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
816 unsigned long led_message = emp->led_state;
817 u32 activity_led_state;
818 unsigned long flags;
819
820 led_message &= EM_MSG_LED_VALUE;
821 led_message |= ap->port_no | (link->pmp << 8);
822
823 /* check to see if we've had activity. If so,
824 * toggle state of LED and reset timer. If not,
825 * turn LED to desired idle state.
826 */
827 spin_lock_irqsave(ap->lock, flags);
828 if (emp->saved_activity != emp->activity) {
829 emp->saved_activity = emp->activity;
830 /* get the current LED state */
831 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
832
833 if (activity_led_state)
834 activity_led_state = 0;
835 else
836 activity_led_state = 1;
837
838 /* clear old state */
839 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
840
841 /* toggle state */
842 led_message |= (activity_led_state << 16);
843 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
844 } else {
845 /* switch to idle */
846 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
847 if (emp->blink_policy == BLINK_OFF)
848 led_message |= (1 << 16);
849 }
850 spin_unlock_irqrestore(ap->lock, flags);
851 ahci_transmit_led_message(ap, led_message, 4);
852}
853
854static void ahci_init_sw_activity(struct ata_link *link)
855{
856 struct ata_port *ap = link->ap;
857 struct ahci_port_priv *pp = ap->private_data;
858 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
859
860 /* init activity stats, setup timer */
861 emp->saved_activity = emp->activity = 0;
862 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
863
864 /* check our blink policy and set flag for link if it's enabled */
865 if (emp->blink_policy)
866 link->flags |= ATA_LFLAG_SW_ACTIVITY;
867}
868
869int ahci_reset_em(struct ata_host *host)
870{
871 struct ahci_host_priv *hpriv = host->private_data;
872 void __iomem *mmio = hpriv->mmio;
873 u32 em_ctl;
874
875 em_ctl = readl(mmio + HOST_EM_CTL);
876 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
877 return -EINVAL;
878
879 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
880 return 0;
881}
882EXPORT_SYMBOL_GPL(ahci_reset_em);
883
884static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
885 ssize_t size)
886{
887 struct ahci_host_priv *hpriv = ap->host->private_data;
888 struct ahci_port_priv *pp = ap->private_data;
889 void __iomem *mmio = hpriv->mmio;
890 u32 em_ctl;
891 u32 message[] = {0, 0};
892 unsigned long flags;
893 int pmp;
894 struct ahci_em_priv *emp;
895
896 /* get the slot number from the message */
897 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
898 if (pmp < EM_MAX_SLOTS)
899 emp = &pp->em_priv[pmp];
900 else
901 return -EINVAL;
902
903 spin_lock_irqsave(ap->lock, flags);
904
905 /*
906 * if we are still busy transmitting a previous message,
907 * do not allow
908 */
909 em_ctl = readl(mmio + HOST_EM_CTL);
910 if (em_ctl & EM_CTL_TM) {
911 spin_unlock_irqrestore(ap->lock, flags);
912 return -EBUSY;
913 }
914
915 /*
916 * create message header - this is all zero except for
917 * the message size, which is 4 bytes.
918 */
919 message[0] |= (4 << 8);
920
921 /* ignore 0:4 of byte zero, fill in port info yourself */
922 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
923
924 /* write message to EM_LOC */
925 writel(message[0], mmio + hpriv->em_loc);
926 writel(message[1], mmio + hpriv->em_loc+4);
927
928 /* save off new led state for port/slot */
929 emp->led_state = state;
930
931 /*
932 * tell hardware to transmit the message
933 */
934 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
935
936 spin_unlock_irqrestore(ap->lock, flags);
937 return size;
938}
939
940static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
941{
942 struct ahci_port_priv *pp = ap->private_data;
943 struct ata_link *link;
944 struct ahci_em_priv *emp;
945 int rc = 0;
946
947 ata_for_each_link(link, ap, EDGE) {
948 emp = &pp->em_priv[link->pmp];
949 rc += sprintf(buf, "%lx\n", emp->led_state);
950 }
951 return rc;
952}
953
954static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
955 size_t size)
956{
957 int state;
958 int pmp;
959 struct ahci_port_priv *pp = ap->private_data;
960 struct ahci_em_priv *emp;
961
962 state = simple_strtoul(buf, NULL, 0);
963
964 /* get the slot number from the message */
965 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
966 if (pmp < EM_MAX_SLOTS)
967 emp = &pp->em_priv[pmp];
968 else
969 return -EINVAL;
970
971 /* mask off the activity bits if we are in sw_activity
972 * mode, user should turn off sw_activity before setting
973 * activity led through em_message
974 */
975 if (emp->blink_policy)
976 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
977
978 return ahci_transmit_led_message(ap, state, size);
979}
980
981static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
982{
983 struct ata_link *link = dev->link;
984 struct ata_port *ap = link->ap;
985 struct ahci_port_priv *pp = ap->private_data;
986 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
987 u32 port_led_state = emp->led_state;
988
989 /* save the desired Activity LED behavior */
990 if (val == OFF) {
991 /* clear LFLAG */
992 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
993
994 /* set the LED to OFF */
995 port_led_state &= EM_MSG_LED_VALUE_OFF;
996 port_led_state |= (ap->port_no | (link->pmp << 8));
997 ahci_transmit_led_message(ap, port_led_state, 4);
998 } else {
999 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1000 if (val == BLINK_OFF) {
1001 /* set LED to ON for idle */
1002 port_led_state &= EM_MSG_LED_VALUE_OFF;
1003 port_led_state |= (ap->port_no | (link->pmp << 8));
1004 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1005 ahci_transmit_led_message(ap, port_led_state, 4);
1006 }
1007 }
1008 emp->blink_policy = val;
1009 return 0;
1010}
1011
1012static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1013{
1014 struct ata_link *link = dev->link;
1015 struct ata_port *ap = link->ap;
1016 struct ahci_port_priv *pp = ap->private_data;
1017 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1018
1019 /* display the saved value of activity behavior for this
1020 * disk.
1021 */
1022 return sprintf(buf, "%d\n", emp->blink_policy);
1023}
1024
1025static void ahci_port_init(struct device *dev, struct ata_port *ap,
1026 int port_no, void __iomem *mmio,
1027 void __iomem *port_mmio)
1028{
1029 const char *emsg = NULL;
1030 int rc;
1031 u32 tmp;
1032
1033 /* make sure port is not active */
1034 rc = ahci_deinit_port(ap, &emsg);
1035 if (rc)
1036 dev_warn(dev, "%s (%d)\n", emsg, rc);
1037
1038 /* clear SError */
1039 tmp = readl(port_mmio + PORT_SCR_ERR);
1040 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1041 writel(tmp, port_mmio + PORT_SCR_ERR);
1042
1043 /* clear port IRQ */
1044 tmp = readl(port_mmio + PORT_IRQ_STAT);
1045 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1046 if (tmp)
1047 writel(tmp, port_mmio + PORT_IRQ_STAT);
1048
1049 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1050}
1051
1052void ahci_init_controller(struct ata_host *host)
1053{
1054 struct ahci_host_priv *hpriv = host->private_data;
1055 void __iomem *mmio = hpriv->mmio;
1056 int i;
1057 void __iomem *port_mmio;
1058 u32 tmp;
1059
1060 for (i = 0; i < host->n_ports; i++) {
1061 struct ata_port *ap = host->ports[i];
1062
1063 port_mmio = ahci_port_base(ap);
1064 if (ata_port_is_dummy(ap))
1065 continue;
1066
1067 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1068 }
1069
1070 tmp = readl(mmio + HOST_CTL);
1071 VPRINTK("HOST_CTL 0x%x\n", tmp);
1072 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1073 tmp = readl(mmio + HOST_CTL);
1074 VPRINTK("HOST_CTL 0x%x\n", tmp);
1075}
1076EXPORT_SYMBOL_GPL(ahci_init_controller);
1077
1078static void ahci_dev_config(struct ata_device *dev)
1079{
1080 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1081
1082 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1083 dev->max_sectors = 255;
1084 ata_dev_printk(dev, KERN_INFO,
1085 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1086 }
1087}
1088
1089static unsigned int ahci_dev_classify(struct ata_port *ap)
1090{
1091 void __iomem *port_mmio = ahci_port_base(ap);
1092 struct ata_taskfile tf;
1093 u32 tmp;
1094
1095 tmp = readl(port_mmio + PORT_SIG);
1096 tf.lbah = (tmp >> 24) & 0xff;
1097 tf.lbam = (tmp >> 16) & 0xff;
1098 tf.lbal = (tmp >> 8) & 0xff;
1099 tf.nsect = (tmp) & 0xff;
1100
1101 return ata_dev_classify(&tf);
1102}
1103
1104static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1105 u32 opts)
1106{
1107 dma_addr_t cmd_tbl_dma;
1108
1109 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1110
1111 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1112 pp->cmd_slot[tag].status = 0;
1113 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1114 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1115}
1116
1117int ahci_kick_engine(struct ata_port *ap)
1118{
1119 void __iomem *port_mmio = ahci_port_base(ap);
1120 struct ahci_host_priv *hpriv = ap->host->private_data;
1121 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1122 u32 tmp;
1123 int busy, rc;
1124
1125 /* stop engine */
1126 rc = ahci_stop_engine(ap);
1127 if (rc)
1128 goto out_restart;
1129
1130 /* need to do CLO?
1131 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1132 */
1133 busy = status & (ATA_BUSY | ATA_DRQ);
1134 if (!busy && !sata_pmp_attached(ap)) {
1135 rc = 0;
1136 goto out_restart;
1137 }
1138
1139 if (!(hpriv->cap & HOST_CAP_CLO)) {
1140 rc = -EOPNOTSUPP;
1141 goto out_restart;
1142 }
1143
1144 /* perform CLO */
1145 tmp = readl(port_mmio + PORT_CMD);
1146 tmp |= PORT_CMD_CLO;
1147 writel(tmp, port_mmio + PORT_CMD);
1148
1149 rc = 0;
1150 tmp = ata_wait_register(port_mmio + PORT_CMD,
1151 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1152 if (tmp & PORT_CMD_CLO)
1153 rc = -EIO;
1154
1155 /* restart engine */
1156 out_restart:
1157 ahci_start_engine(ap);
1158 return rc;
1159}
1160EXPORT_SYMBOL_GPL(ahci_kick_engine);
1161
1162static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1163 struct ata_taskfile *tf, int is_cmd, u16 flags,
1164 unsigned long timeout_msec)
1165{
1166 const u32 cmd_fis_len = 5; /* five dwords */
1167 struct ahci_port_priv *pp = ap->private_data;
1168 void __iomem *port_mmio = ahci_port_base(ap);
1169 u8 *fis = pp->cmd_tbl;
1170 u32 tmp;
1171
1172 /* prep the command */
1173 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1174 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1175
1176 /* issue & wait */
1177 writel(1, port_mmio + PORT_CMD_ISSUE);
1178
1179 if (timeout_msec) {
1180 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1181 1, timeout_msec);
1182 if (tmp & 0x1) {
1183 ahci_kick_engine(ap);
1184 return -EBUSY;
1185 }
1186 } else
1187 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1188
1189 return 0;
1190}
1191
1192int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1193 int pmp, unsigned long deadline,
1194 int (*check_ready)(struct ata_link *link))
1195{
1196 struct ata_port *ap = link->ap;
1197 struct ahci_host_priv *hpriv = ap->host->private_data;
1198 const char *reason = NULL;
1199 unsigned long now, msecs;
1200 struct ata_taskfile tf;
1201 int rc;
1202
1203 DPRINTK("ENTER\n");
1204
1205 /* prepare for SRST (AHCI-1.1 10.4.1) */
1206 rc = ahci_kick_engine(ap);
1207 if (rc && rc != -EOPNOTSUPP)
1208 ata_link_printk(link, KERN_WARNING,
1209 "failed to reset engine (errno=%d)\n", rc);
1210
1211 ata_tf_init(link->device, &tf);
1212
1213 /* issue the first D2H Register FIS */
1214 msecs = 0;
1215 now = jiffies;
1216 if (time_after(now, deadline))
1217 msecs = jiffies_to_msecs(deadline - now);
1218
1219 tf.ctl |= ATA_SRST;
1220 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1221 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1222 rc = -EIO;
1223 reason = "1st FIS failed";
1224 goto fail;
1225 }
1226
1227 /* spec says at least 5us, but be generous and sleep for 1ms */
1228 msleep(1);
1229
1230 /* issue the second D2H Register FIS */
1231 tf.ctl &= ~ATA_SRST;
1232 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1233
1234 /* wait for link to become ready */
1235 rc = ata_wait_after_reset(link, deadline, check_ready);
1236 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1237 /*
1238 * Workaround for cases where link online status can't
1239 * be trusted. Treat device readiness timeout as link
1240 * offline.
1241 */
1242 ata_link_printk(link, KERN_INFO,
1243 "device not ready, treating as offline\n");
1244 *class = ATA_DEV_NONE;
1245 } else if (rc) {
1246 /* link occupied, -ENODEV too is an error */
1247 reason = "device not ready";
1248 goto fail;
1249 } else
1250 *class = ahci_dev_classify(ap);
1251
1252 DPRINTK("EXIT, class=%u\n", *class);
1253 return 0;
1254
1255 fail:
1256 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1257 return rc;
1258}
1259
1260int ahci_check_ready(struct ata_link *link)
1261{
1262 void __iomem *port_mmio = ahci_port_base(link->ap);
1263 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1264
1265 return ata_check_ready(status);
1266}
1267EXPORT_SYMBOL_GPL(ahci_check_ready);
1268
1269static int ahci_softreset(struct ata_link *link, unsigned int *class,
1270 unsigned long deadline)
1271{
1272 int pmp = sata_srst_pmp(link);
1273
1274 DPRINTK("ENTER\n");
1275
1276 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1277}
1278EXPORT_SYMBOL_GPL(ahci_do_softreset);
1279
1280static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1281 unsigned long deadline)
1282{
1283 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1284 struct ata_port *ap = link->ap;
1285 struct ahci_port_priv *pp = ap->private_data;
1286 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1287 struct ata_taskfile tf;
1288 bool online;
1289 int rc;
1290
1291 DPRINTK("ENTER\n");
1292
1293 ahci_stop_engine(ap);
1294
1295 /* clear D2H reception area to properly wait for D2H FIS */
1296 ata_tf_init(link->device, &tf);
1297 tf.command = 0x80;
1298 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1299
1300 rc = sata_link_hardreset(link, timing, deadline, &online,
1301 ahci_check_ready);
1302
1303 ahci_start_engine(ap);
1304
1305 if (online)
1306 *class = ahci_dev_classify(ap);
1307
1308 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1309 return rc;
1310}
1311
1312static void ahci_postreset(struct ata_link *link, unsigned int *class)
1313{
1314 struct ata_port *ap = link->ap;
1315 void __iomem *port_mmio = ahci_port_base(ap);
1316 u32 new_tmp, tmp;
1317
1318 ata_std_postreset(link, class);
1319
1320 /* Make sure port's ATAPI bit is set appropriately */
1321 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1322 if (*class == ATA_DEV_ATAPI)
1323 new_tmp |= PORT_CMD_ATAPI;
1324 else
1325 new_tmp &= ~PORT_CMD_ATAPI;
1326 if (new_tmp != tmp) {
1327 writel(new_tmp, port_mmio + PORT_CMD);
1328 readl(port_mmio + PORT_CMD); /* flush */
1329 }
1330}
1331
1332static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1333{
1334 struct scatterlist *sg;
1335 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1336 unsigned int si;
1337
1338 VPRINTK("ENTER\n");
1339
1340 /*
1341 * Next, the S/G list.
1342 */
1343 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1344 dma_addr_t addr = sg_dma_address(sg);
1345 u32 sg_len = sg_dma_len(sg);
1346
1347 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1348 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1349 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1350 }
1351
1352 return si;
1353}
1354
1355static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1356{
1357 struct ata_port *ap = qc->ap;
1358 struct ahci_port_priv *pp = ap->private_data;
1359
1360 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1361 return ata_std_qc_defer(qc);
1362 else
1363 return sata_pmp_qc_defer_cmd_switch(qc);
1364}
1365
1366static void ahci_qc_prep(struct ata_queued_cmd *qc)
1367{
1368 struct ata_port *ap = qc->ap;
1369 struct ahci_port_priv *pp = ap->private_data;
1370 int is_atapi = ata_is_atapi(qc->tf.protocol);
1371 void *cmd_tbl;
1372 u32 opts;
1373 const u32 cmd_fis_len = 5; /* five dwords */
1374 unsigned int n_elem;
1375
1376 /*
1377 * Fill in command table information. First, the header,
1378 * a SATA Register - Host to Device command FIS.
1379 */
1380 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1381
1382 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1383 if (is_atapi) {
1384 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1385 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1386 }
1387
1388 n_elem = 0;
1389 if (qc->flags & ATA_QCFLAG_DMAMAP)
1390 n_elem = ahci_fill_sg(qc, cmd_tbl);
1391
1392 /*
1393 * Fill in command slot information.
1394 */
1395 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1396 if (qc->tf.flags & ATA_TFLAG_WRITE)
1397 opts |= AHCI_CMD_WRITE;
1398 if (is_atapi)
1399 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1400
1401 ahci_fill_cmd_slot(pp, qc->tag, opts);
1402}
1403
1404static void ahci_fbs_dec_intr(struct ata_port *ap)
1405{
1406 struct ahci_port_priv *pp = ap->private_data;
1407 void __iomem *port_mmio = ahci_port_base(ap);
1408 u32 fbs = readl(port_mmio + PORT_FBS);
1409 int retries = 3;
1410
1411 DPRINTK("ENTER\n");
1412 BUG_ON(!pp->fbs_enabled);
1413
1414 /* time to wait for DEC is not specified by AHCI spec,
1415 * add a retry loop for safety.
1416 */
1417 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1418 fbs = readl(port_mmio + PORT_FBS);
1419 while ((fbs & PORT_FBS_DEC) && retries--) {
1420 udelay(1);
1421 fbs = readl(port_mmio + PORT_FBS);
1422 }
1423
1424 if (fbs & PORT_FBS_DEC)
1425 dev_printk(KERN_ERR, ap->host->dev,
1426 "failed to clear device error\n");
1427}
1428
1429static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1430{
1431 struct ahci_host_priv *hpriv = ap->host->private_data;
1432 struct ahci_port_priv *pp = ap->private_data;
1433 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1434 struct ata_link *link = NULL;
1435 struct ata_queued_cmd *active_qc;
1436 struct ata_eh_info *active_ehi;
1437 bool fbs_need_dec = false;
1438 u32 serror;
1439
1440 /* determine active link with error */
1441 if (pp->fbs_enabled) {
1442 void __iomem *port_mmio = ahci_port_base(ap);
1443 u32 fbs = readl(port_mmio + PORT_FBS);
1444 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1445
1446 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
1447 ata_link_online(&ap->pmp_link[pmp])) {
1448 link = &ap->pmp_link[pmp];
1449 fbs_need_dec = true;
1450 }
1451
1452 } else
1453 ata_for_each_link(link, ap, EDGE)
1454 if (ata_link_active(link))
1455 break;
1456
1457 if (!link)
1458 link = &ap->link;
1459
1460 active_qc = ata_qc_from_tag(ap, link->active_tag);
1461 active_ehi = &link->eh_info;
1462
1463 /* record irq stat */
1464 ata_ehi_clear_desc(host_ehi);
1465 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1466
1467 /* AHCI needs SError cleared; otherwise, it might lock up */
1468 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1469 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1470 host_ehi->serror |= serror;
1471
1472 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1473 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1474 irq_stat &= ~PORT_IRQ_IF_ERR;
1475
1476 if (irq_stat & PORT_IRQ_TF_ERR) {
1477 /* If qc is active, charge it; otherwise, the active
1478 * link. There's no active qc on NCQ errors. It will
1479 * be determined by EH by reading log page 10h.
1480 */
1481 if (active_qc)
1482 active_qc->err_mask |= AC_ERR_DEV;
1483 else
1484 active_ehi->err_mask |= AC_ERR_DEV;
1485
1486 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1487 host_ehi->serror &= ~SERR_INTERNAL;
1488 }
1489
1490 if (irq_stat & PORT_IRQ_UNK_FIS) {
1491 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1492
1493 active_ehi->err_mask |= AC_ERR_HSM;
1494 active_ehi->action |= ATA_EH_RESET;
1495 ata_ehi_push_desc(active_ehi,
1496 "unknown FIS %08x %08x %08x %08x" ,
1497 unk[0], unk[1], unk[2], unk[3]);
1498 }
1499
1500 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1501 active_ehi->err_mask |= AC_ERR_HSM;
1502 active_ehi->action |= ATA_EH_RESET;
1503 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1504 }
1505
1506 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1507 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1508 host_ehi->action |= ATA_EH_RESET;
1509 ata_ehi_push_desc(host_ehi, "host bus error");
1510 }
1511
1512 if (irq_stat & PORT_IRQ_IF_ERR) {
1513 if (fbs_need_dec)
1514 active_ehi->err_mask |= AC_ERR_DEV;
1515 else {
1516 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1517 host_ehi->action |= ATA_EH_RESET;
1518 }
1519
1520 ata_ehi_push_desc(host_ehi, "interface fatal error");
1521 }
1522
1523 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1524 ata_ehi_hotplugged(host_ehi);
1525 ata_ehi_push_desc(host_ehi, "%s",
1526 irq_stat & PORT_IRQ_CONNECT ?
1527 "connection status changed" : "PHY RDY changed");
1528 }
1529
1530 /* okay, let's hand over to EH */
1531
1532 if (irq_stat & PORT_IRQ_FREEZE)
1533 ata_port_freeze(ap);
1534 else if (fbs_need_dec) {
1535 ata_link_abort(link);
1536 ahci_fbs_dec_intr(ap);
1537 } else
1538 ata_port_abort(ap);
1539}
1540
1541static void ahci_port_intr(struct ata_port *ap)
1542{
1543 void __iomem *port_mmio = ahci_port_base(ap);
1544 struct ata_eh_info *ehi = &ap->link.eh_info;
1545 struct ahci_port_priv *pp = ap->private_data;
1546 struct ahci_host_priv *hpriv = ap->host->private_data;
1547 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1548 u32 status, qc_active = 0;
1549 int rc;
1550
1551 status = readl(port_mmio + PORT_IRQ_STAT);
1552 writel(status, port_mmio + PORT_IRQ_STAT);
1553
1554 /* ignore BAD_PMP while resetting */
1555 if (unlikely(resetting))
1556 status &= ~PORT_IRQ_BAD_PMP;
1557
1558 /* If we are getting PhyRdy, this is
1559 * just a power state change, we should
1560 * clear out this, plus the PhyRdy/Comm
1561 * Wake bits from Serror
1562 */
1563 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1564 (status & PORT_IRQ_PHYRDY)) {
1565 status &= ~PORT_IRQ_PHYRDY;
1566 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1567 }
1568
1569 if (unlikely(status & PORT_IRQ_ERROR)) {
1570 ahci_error_intr(ap, status);
1571 return;
1572 }
1573
1574 if (status & PORT_IRQ_SDB_FIS) {
1575 /* If SNotification is available, leave notification
1576 * handling to sata_async_notification(). If not,
1577 * emulate it by snooping SDB FIS RX area.
1578 *
1579 * Snooping FIS RX area is probably cheaper than
1580 * poking SNotification but some constrollers which
1581 * implement SNotification, ICH9 for example, don't
1582 * store AN SDB FIS into receive area.
1583 */
1584 if (hpriv->cap & HOST_CAP_SNTF)
1585 sata_async_notification(ap);
1586 else {
1587 /* If the 'N' bit in word 0 of the FIS is set,
1588 * we just received asynchronous notification.
1589 * Tell libata about it.
1590 *
1591 * Lack of SNotification should not appear in
1592 * ahci 1.2, so the workaround is unnecessary
1593 * when FBS is enabled.
1594 */
1595 if (pp->fbs_enabled)
1596 WARN_ON_ONCE(1);
1597 else {
1598 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1599 u32 f0 = le32_to_cpu(f[0]);
1600 if (f0 & (1 << 15))
1601 sata_async_notification(ap);
1602 }
1603 }
1604 }
1605
1606 /* pp->active_link is not reliable once FBS is enabled, both
1607 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1608 * NCQ and non-NCQ commands may be in flight at the same time.
1609 */
1610 if (pp->fbs_enabled) {
1611 if (ap->qc_active) {
1612 qc_active = readl(port_mmio + PORT_SCR_ACT);
1613 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1614 }
1615 } else {
1616 /* pp->active_link is valid iff any command is in flight */
1617 if (ap->qc_active && pp->active_link->sactive)
1618 qc_active = readl(port_mmio + PORT_SCR_ACT);
1619 else
1620 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1621 }
1622
1623
1624 rc = ata_qc_complete_multiple(ap, qc_active);
1625
1626 /* while resetting, invalid completions are expected */
1627 if (unlikely(rc < 0 && !resetting)) {
1628 ehi->err_mask |= AC_ERR_HSM;
1629 ehi->action |= ATA_EH_RESET;
1630 ata_port_freeze(ap);
1631 }
1632}
1633
1634irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1635{
1636 struct ata_host *host = dev_instance;
1637 struct ahci_host_priv *hpriv;
1638 unsigned int i, handled = 0;
1639 void __iomem *mmio;
1640 u32 irq_stat, irq_masked;
1641
1642 VPRINTK("ENTER\n");
1643
1644 hpriv = host->private_data;
1645 mmio = hpriv->mmio;
1646
1647 /* sigh. 0xffffffff is a valid return from h/w */
1648 irq_stat = readl(mmio + HOST_IRQ_STAT);
1649 if (!irq_stat)
1650 return IRQ_NONE;
1651
1652 irq_masked = irq_stat & hpriv->port_map;
1653
1654 spin_lock(&host->lock);
1655
1656 for (i = 0; i < host->n_ports; i++) {
1657 struct ata_port *ap;
1658
1659 if (!(irq_masked & (1 << i)))
1660 continue;
1661
1662 ap = host->ports[i];
1663 if (ap) {
1664 ahci_port_intr(ap);
1665 VPRINTK("port %u\n", i);
1666 } else {
1667 VPRINTK("port %u (no irq)\n", i);
1668 if (ata_ratelimit())
1669 dev_printk(KERN_WARNING, host->dev,
1670 "interrupt on disabled port %u\n", i);
1671 }
1672
1673 handled = 1;
1674 }
1675
1676 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1677 * it should be cleared after all the port events are cleared;
1678 * otherwise, it will raise a spurious interrupt after each
1679 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1680 * information.
1681 *
1682 * Also, use the unmasked value to clear interrupt as spurious
1683 * pending event on a dummy port might cause screaming IRQ.
1684 */
1685 writel(irq_stat, mmio + HOST_IRQ_STAT);
1686
1687 spin_unlock(&host->lock);
1688
1689 VPRINTK("EXIT\n");
1690
1691 return IRQ_RETVAL(handled);
1692}
1693EXPORT_SYMBOL_GPL(ahci_interrupt);
1694
1695static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1696{
1697 struct ata_port *ap = qc->ap;
1698 void __iomem *port_mmio = ahci_port_base(ap);
1699 struct ahci_port_priv *pp = ap->private_data;
1700
1701 /* Keep track of the currently active link. It will be used
1702 * in completion path to determine whether NCQ phase is in
1703 * progress.
1704 */
1705 pp->active_link = qc->dev->link;
1706
1707 if (qc->tf.protocol == ATA_PROT_NCQ)
1708 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1709
1710 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1711 u32 fbs = readl(port_mmio + PORT_FBS);
1712 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1713 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1714 writel(fbs, port_mmio + PORT_FBS);
1715 pp->fbs_last_dev = qc->dev->link->pmp;
1716 }
1717
1718 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1719
1720 ahci_sw_activity(qc->dev->link);
1721
1722 return 0;
1723}
1724
1725static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1726{
1727 struct ahci_port_priv *pp = qc->ap->private_data;
1728 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1729
1730 if (pp->fbs_enabled)
1731 d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1732
1733 ata_tf_from_fis(d2h_fis, &qc->result_tf);
1734 return true;
1735}
1736
1737static void ahci_freeze(struct ata_port *ap)
1738{
1739 void __iomem *port_mmio = ahci_port_base(ap);
1740
1741 /* turn IRQ off */
1742 writel(0, port_mmio + PORT_IRQ_MASK);
1743}
1744
1745static void ahci_thaw(struct ata_port *ap)
1746{
1747 struct ahci_host_priv *hpriv = ap->host->private_data;
1748 void __iomem *mmio = hpriv->mmio;
1749 void __iomem *port_mmio = ahci_port_base(ap);
1750 u32 tmp;
1751 struct ahci_port_priv *pp = ap->private_data;
1752
1753 /* clear IRQ */
1754 tmp = readl(port_mmio + PORT_IRQ_STAT);
1755 writel(tmp, port_mmio + PORT_IRQ_STAT);
1756 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1757
1758 /* turn IRQ back on */
1759 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1760}
1761
1762static void ahci_error_handler(struct ata_port *ap)
1763{
1764 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1765 /* restart engine */
1766 ahci_stop_engine(ap);
1767 ahci_start_engine(ap);
1768 }
1769
1770 sata_pmp_error_handler(ap);
1771}
1772
1773static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1774{
1775 struct ata_port *ap = qc->ap;
1776
1777 /* make DMA engine forget about the failed command */
1778 if (qc->flags & ATA_QCFLAG_FAILED)
1779 ahci_kick_engine(ap);
1780}
1781
1782static void ahci_enable_fbs(struct ata_port *ap)
1783{
1784 struct ahci_port_priv *pp = ap->private_data;
1785 void __iomem *port_mmio = ahci_port_base(ap);
1786 u32 fbs;
1787 int rc;
1788
1789 if (!pp->fbs_supported)
1790 return;
1791
1792 fbs = readl(port_mmio + PORT_FBS);
1793 if (fbs & PORT_FBS_EN) {
1794 pp->fbs_enabled = true;
1795 pp->fbs_last_dev = -1; /* initialization */
1796 return;
1797 }
1798
1799 rc = ahci_stop_engine(ap);
1800 if (rc)
1801 return;
1802
1803 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
1804 fbs = readl(port_mmio + PORT_FBS);
1805 if (fbs & PORT_FBS_EN) {
1806 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
1807 pp->fbs_enabled = true;
1808 pp->fbs_last_dev = -1; /* initialization */
1809 } else
1810 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
1811
1812 ahci_start_engine(ap);
1813}
1814
1815static void ahci_disable_fbs(struct ata_port *ap)
1816{
1817 struct ahci_port_priv *pp = ap->private_data;
1818 void __iomem *port_mmio = ahci_port_base(ap);
1819 u32 fbs;
1820 int rc;
1821
1822 if (!pp->fbs_supported)
1823 return;
1824
1825 fbs = readl(port_mmio + PORT_FBS);
1826 if ((fbs & PORT_FBS_EN) == 0) {
1827 pp->fbs_enabled = false;
1828 return;
1829 }
1830
1831 rc = ahci_stop_engine(ap);
1832 if (rc)
1833 return;
1834
1835 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
1836 fbs = readl(port_mmio + PORT_FBS);
1837 if (fbs & PORT_FBS_EN)
1838 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
1839 else {
1840 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
1841 pp->fbs_enabled = false;
1842 }
1843
1844 ahci_start_engine(ap);
1845}
1846
1847static void ahci_pmp_attach(struct ata_port *ap)
1848{
1849 void __iomem *port_mmio = ahci_port_base(ap);
1850 struct ahci_port_priv *pp = ap->private_data;
1851 u32 cmd;
1852
1853 cmd = readl(port_mmio + PORT_CMD);
1854 cmd |= PORT_CMD_PMP;
1855 writel(cmd, port_mmio + PORT_CMD);
1856
1857 ahci_enable_fbs(ap);
1858
1859 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1860 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1861}
1862
1863static void ahci_pmp_detach(struct ata_port *ap)
1864{
1865 void __iomem *port_mmio = ahci_port_base(ap);
1866 struct ahci_port_priv *pp = ap->private_data;
1867 u32 cmd;
1868
1869 ahci_disable_fbs(ap);
1870
1871 cmd = readl(port_mmio + PORT_CMD);
1872 cmd &= ~PORT_CMD_PMP;
1873 writel(cmd, port_mmio + PORT_CMD);
1874
1875 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1876 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1877}
1878
1879static int ahci_port_resume(struct ata_port *ap)
1880{
1881 ahci_power_up(ap);
1882 ahci_start_port(ap);
1883
1884 if (sata_pmp_attached(ap))
1885 ahci_pmp_attach(ap);
1886 else
1887 ahci_pmp_detach(ap);
1888
1889 return 0;
1890}
1891
1892#ifdef CONFIG_PM
1893static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1894{
1895 const char *emsg = NULL;
1896 int rc;
1897
1898 rc = ahci_deinit_port(ap, &emsg);
1899 if (rc == 0)
1900 ahci_power_down(ap);
1901 else {
1902 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1903 ahci_start_port(ap);
1904 }
1905
1906 return rc;
1907}
1908#endif
1909
1910static int ahci_port_start(struct ata_port *ap)
1911{
1912 struct ahci_host_priv *hpriv = ap->host->private_data;
1913 struct device *dev = ap->host->dev;
1914 struct ahci_port_priv *pp;
1915 void *mem;
1916 dma_addr_t mem_dma;
1917 size_t dma_sz, rx_fis_sz;
1918
1919 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1920 if (!pp)
1921 return -ENOMEM;
1922
1923 /* check FBS capability */
1924 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
1925 void __iomem *port_mmio = ahci_port_base(ap);
1926 u32 cmd = readl(port_mmio + PORT_CMD);
1927 if (cmd & PORT_CMD_FBSCP)
1928 pp->fbs_supported = true;
1929 else
1930 dev_printk(KERN_WARNING, dev,
1931 "The port is not capable of FBS\n");
1932 }
1933
1934 if (pp->fbs_supported) {
1935 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
1936 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
1937 } else {
1938 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
1939 rx_fis_sz = AHCI_RX_FIS_SZ;
1940 }
1941
1942 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
1943 if (!mem)
1944 return -ENOMEM;
1945 memset(mem, 0, dma_sz);
1946
1947 /*
1948 * First item in chunk of DMA memory: 32-slot command table,
1949 * 32 bytes each in size
1950 */
1951 pp->cmd_slot = mem;
1952 pp->cmd_slot_dma = mem_dma;
1953
1954 mem += AHCI_CMD_SLOT_SZ;
1955 mem_dma += AHCI_CMD_SLOT_SZ;
1956
1957 /*
1958 * Second item: Received-FIS area
1959 */
1960 pp->rx_fis = mem;
1961 pp->rx_fis_dma = mem_dma;
1962
1963 mem += rx_fis_sz;
1964 mem_dma += rx_fis_sz;
1965
1966 /*
1967 * Third item: data area for storing a single command
1968 * and its scatter-gather table
1969 */
1970 pp->cmd_tbl = mem;
1971 pp->cmd_tbl_dma = mem_dma;
1972
1973 /*
1974 * Save off initial list of interrupts to be enabled.
1975 * This could be changed later
1976 */
1977 pp->intr_mask = DEF_PORT_IRQ;
1978
1979 ap->private_data = pp;
1980
1981 /* engage engines, captain */
1982 return ahci_port_resume(ap);
1983}
1984
1985static void ahci_port_stop(struct ata_port *ap)
1986{
1987 const char *emsg = NULL;
1988 int rc;
1989
1990 /* de-initialize port */
1991 rc = ahci_deinit_port(ap, &emsg);
1992 if (rc)
1993 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1994}
1995
1996void ahci_print_info(struct ata_host *host, const char *scc_s)
1997{
1998 struct ahci_host_priv *hpriv = host->private_data;
1999 void __iomem *mmio = hpriv->mmio;
2000 u32 vers, cap, cap2, impl, speed;
2001 const char *speed_s;
2002
2003 vers = readl(mmio + HOST_VERSION);
2004 cap = hpriv->cap;
2005 cap2 = hpriv->cap2;
2006 impl = hpriv->port_map;
2007
2008 speed = (cap >> 20) & 0xf;
2009 if (speed == 1)
2010 speed_s = "1.5";
2011 else if (speed == 2)
2012 speed_s = "3";
2013 else if (speed == 3)
2014 speed_s = "6";
2015 else
2016 speed_s = "?";
2017
2018 dev_info(host->dev,
2019 "AHCI %02x%02x.%02x%02x "
2020 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2021 ,
2022
2023 (vers >> 24) & 0xff,
2024 (vers >> 16) & 0xff,
2025 (vers >> 8) & 0xff,
2026 vers & 0xff,
2027
2028 ((cap >> 8) & 0x1f) + 1,
2029 (cap & 0x1f) + 1,
2030 speed_s,
2031 impl,
2032 scc_s);
2033
2034 dev_info(host->dev,
2035 "flags: "
2036 "%s%s%s%s%s%s%s"
2037 "%s%s%s%s%s%s%s"
2038 "%s%s%s%s%s%s\n"
2039 ,
2040
2041 cap & HOST_CAP_64 ? "64bit " : "",
2042 cap & HOST_CAP_NCQ ? "ncq " : "",
2043 cap & HOST_CAP_SNTF ? "sntf " : "",
2044 cap & HOST_CAP_MPS ? "ilck " : "",
2045 cap & HOST_CAP_SSS ? "stag " : "",
2046 cap & HOST_CAP_ALPM ? "pm " : "",
2047 cap & HOST_CAP_LED ? "led " : "",
2048 cap & HOST_CAP_CLO ? "clo " : "",
2049 cap & HOST_CAP_ONLY ? "only " : "",
2050 cap & HOST_CAP_PMP ? "pmp " : "",
2051 cap & HOST_CAP_FBS ? "fbs " : "",
2052 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2053 cap & HOST_CAP_SSC ? "slum " : "",
2054 cap & HOST_CAP_PART ? "part " : "",
2055 cap & HOST_CAP_CCC ? "ccc " : "",
2056 cap & HOST_CAP_EMS ? "ems " : "",
2057 cap & HOST_CAP_SXS ? "sxs " : "",
2058 cap2 & HOST_CAP2_APST ? "apst " : "",
2059 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2060 cap2 & HOST_CAP2_BOH ? "boh " : ""
2061 );
2062}
2063EXPORT_SYMBOL_GPL(ahci_print_info);
2064
2065void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2066 struct ata_port_info *pi)
2067{
2068 u8 messages;
2069 void __iomem *mmio = hpriv->mmio;
2070 u32 em_loc = readl(mmio + HOST_EM_LOC);
2071 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2072
2073 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2074 return;
2075
2076 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2077
2078 /* we only support LED message type right now */
2079 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2080 /* store em_loc */
2081 hpriv->em_loc = ((em_loc >> 16) * 4);
2082 pi->flags |= ATA_FLAG_EM;
2083 if (!(em_ctl & EM_CTL_ALHD))
2084 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2085 }
2086}
2087EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2088
2089MODULE_AUTHOR("Jeff Garzik");
2090MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2091MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 14:54:28 -0500