diff options
author | Tejun Heo <htejun@gmail.com> | 2007-11-18 21:24:25 -0500 |
---|---|---|
committer | Tejun Heo <htejun@gmail.com> | 2007-11-18 22:28:11 -0500 |
commit | 00242ec87608d7a0ed989e54333f3fc8f3d665b0 (patch) | |
tree | 40abddfa3d8fb4c9d42fea8d514987d47ba020e2 /drivers/ata/ata_piix.c | |
parent | 1f71d0672ac88e79f444d77102e05292dbc66d0d (diff) |
ata_piix: reorganize controller IDs
Move piix_pata_mwdma to top, rename ich9_2port_sata to ich8_2port_sata
for consistency and use automatically incremented values instead of
assigning fixed values to ease adding new controller IDs.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Diffstat (limited to 'drivers/ata/ata_piix.c')
-rw-r--r-- | drivers/ata/ata_piix.c | 62 |
1 files changed, 31 insertions, 31 deletions
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c index 80b735b70972..77fea05990d2 100644 --- a/drivers/ata/ata_piix.c +++ b/drivers/ata/ata_piix.c | |||
@@ -119,18 +119,18 @@ enum { | |||
119 | PIIX_80C_SEC = (1 << 7) | (1 << 6), | 119 | PIIX_80C_SEC = (1 << 7) | (1 << 6), |
120 | 120 | ||
121 | /* controller IDs */ | 121 | /* controller IDs */ |
122 | piix_pata_33 = 0, /* PIIX4 at 33Mhz */ | 122 | piix_pata_mwdma = 0, /* PIIX3 MWDMA only */ |
123 | ich_pata_33 = 1, /* ICH up to UDMA 33 only */ | 123 | piix_pata_33, /* PIIX4 at 33Mhz */ |
124 | ich_pata_66 = 2, /* ICH up to 66 Mhz */ | 124 | ich_pata_33, /* ICH up to UDMA 33 only */ |
125 | ich_pata_100 = 3, /* ICH up to UDMA 100 */ | 125 | ich_pata_66, /* ICH up to 66 Mhz */ |
126 | ich5_sata = 5, | 126 | ich_pata_100, /* ICH up to UDMA 100 */ |
127 | ich6_sata = 6, | 127 | ich5_sata, |
128 | ich6_sata_ahci = 7, | 128 | ich6_sata, |
129 | ich6m_sata_ahci = 8, | 129 | ich6_sata_ahci, |
130 | ich8_sata_ahci = 9, | 130 | ich6m_sata_ahci, |
131 | piix_pata_mwdma = 10, /* PIIX3 MWDMA only */ | 131 | ich8_sata_ahci, |
132 | tolapai_sata_ahci = 11, | 132 | ich8_2port_sata, |
133 | ich9_2port_sata = 12, | 133 | tolapai_sata_ahci, |
134 | 134 | ||
135 | /* constants for mapping table */ | 135 | /* constants for mapping table */ |
136 | P0 = 0, /* port 0 */ | 136 | P0 = 0, /* port 0 */ |
@@ -239,19 +239,19 @@ static const struct pci_device_id piix_pci_tbl[] = { | |||
239 | /* SATA Controller 1 IDE (ICH8) */ | 239 | /* SATA Controller 1 IDE (ICH8) */ |
240 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | 240 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
241 | /* SATA Controller 2 IDE (ICH8) */ | 241 | /* SATA Controller 2 IDE (ICH8) */ |
242 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, | 242 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
243 | /* Mobile SATA Controller IDE (ICH8M) */ | 243 | /* Mobile SATA Controller IDE (ICH8M) */ |
244 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | 244 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
245 | /* SATA Controller IDE (ICH9) */ | 245 | /* SATA Controller IDE (ICH9) */ |
246 | { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | 246 | { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
247 | /* SATA Controller IDE (ICH9) */ | 247 | /* SATA Controller IDE (ICH9) */ |
248 | { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, | 248 | { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
249 | /* SATA Controller IDE (ICH9) */ | 249 | /* SATA Controller IDE (ICH9) */ |
250 | { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, | 250 | { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
251 | /* SATA Controller IDE (ICH9M) */ | 251 | /* SATA Controller IDE (ICH9M) */ |
252 | { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, | 252 | { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
253 | /* SATA Controller IDE (ICH9M) */ | 253 | /* SATA Controller IDE (ICH9M) */ |
254 | { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, | 254 | { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
255 | /* SATA Controller IDE (ICH9M) */ | 255 | /* SATA Controller IDE (ICH9M) */ |
256 | { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | 256 | { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
257 | /* SATA Controller IDE (Tolapai) */ | 257 | /* SATA Controller IDE (Tolapai) */ |
@@ -437,7 +437,7 @@ static const struct piix_map_db ich8_map_db = { | |||
437 | }, | 437 | }, |
438 | }; | 438 | }; |
439 | 439 | ||
440 | static const struct piix_map_db tolapai_map_db = { | 440 | static const struct piix_map_db ich8_2port_map_db = { |
441 | .mask = 0x3, | 441 | .mask = 0x3, |
442 | .port_enable = 0x3, | 442 | .port_enable = 0x3, |
443 | .map = { | 443 | .map = { |
@@ -449,7 +449,7 @@ static const struct piix_map_db tolapai_map_db = { | |||
449 | }, | 449 | }, |
450 | }; | 450 | }; |
451 | 451 | ||
452 | static const struct piix_map_db ich9_2port_map_db = { | 452 | static const struct piix_map_db tolapai_map_db = { |
453 | .mask = 0x3, | 453 | .mask = 0x3, |
454 | .port_enable = 0x3, | 454 | .port_enable = 0x3, |
455 | .map = { | 455 | .map = { |
@@ -467,11 +467,20 @@ static const struct piix_map_db *piix_map_db_table[] = { | |||
467 | [ich6_sata_ahci] = &ich6_map_db, | 467 | [ich6_sata_ahci] = &ich6_map_db, |
468 | [ich6m_sata_ahci] = &ich6m_map_db, | 468 | [ich6m_sata_ahci] = &ich6m_map_db, |
469 | [ich8_sata_ahci] = &ich8_map_db, | 469 | [ich8_sata_ahci] = &ich8_map_db, |
470 | [ich8_2port_sata] = &ich8_2port_map_db, | ||
470 | [tolapai_sata_ahci] = &tolapai_map_db, | 471 | [tolapai_sata_ahci] = &tolapai_map_db, |
471 | [ich9_2port_sata] = &ich9_2port_map_db, | ||
472 | }; | 472 | }; |
473 | 473 | ||
474 | static struct ata_port_info piix_port_info[] = { | 474 | static struct ata_port_info piix_port_info[] = { |
475 | [piix_pata_mwdma] = /* PIIX3 MWDMA only */ | ||
476 | { | ||
477 | .sht = &piix_sht, | ||
478 | .flags = PIIX_PATA_FLAGS, | ||
479 | .pio_mask = 0x1f, /* pio0-4 */ | ||
480 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | ||
481 | .port_ops = &piix_pata_ops, | ||
482 | }, | ||
483 | |||
475 | [piix_pata_33] = /* PIIX4 at 33MHz */ | 484 | [piix_pata_33] = /* PIIX4 at 33MHz */ |
476 | { | 485 | { |
477 | .sht = &piix_sht, | 486 | .sht = &piix_sht, |
@@ -565,16 +574,7 @@ static struct ata_port_info piix_port_info[] = { | |||
565 | .port_ops = &piix_sata_ops, | 574 | .port_ops = &piix_sata_ops, |
566 | }, | 575 | }, |
567 | 576 | ||
568 | [piix_pata_mwdma] = /* PIIX3 MWDMA only */ | 577 | [ich8_2port_sata] = |
569 | { | ||
570 | .sht = &piix_sht, | ||
571 | .flags = PIIX_PATA_FLAGS, | ||
572 | .pio_mask = 0x1f, /* pio0-4 */ | ||
573 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | ||
574 | .port_ops = &piix_pata_ops, | ||
575 | }, | ||
576 | |||
577 | [tolapai_sata_ahci] = | ||
578 | { | 578 | { |
579 | .sht = &piix_sht, | 579 | .sht = &piix_sht, |
580 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | | 580 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
@@ -585,7 +585,7 @@ static struct ata_port_info piix_port_info[] = { | |||
585 | .port_ops = &piix_sata_ops, | 585 | .port_ops = &piix_sata_ops, |
586 | }, | 586 | }, |
587 | 587 | ||
588 | [ich9_2port_sata] = | 588 | [tolapai_sata_ahci] = |
589 | { | 589 | { |
590 | .sht = &piix_sht, | 590 | .sht = &piix_sht, |
591 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | | 591 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |