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authorZhao Yakui <yakui.zhao@intel.com>2007-11-15 04:01:06 -0500
committerLen Brown <len.brown@intel.com>2007-11-16 21:37:14 -0500
commit49fbabf56dc715bbb51e59742e82ba762790aac0 (patch)
tree3eaa894071469d36e614048f99f09f6e3e6f1b8b /drivers/acpi/osl.c
parentef54d5ad2f58f899be6419fd1090cdeb2439851a (diff)
ACPI: Handle I/O access width requestst that are not a multiple of 8 bits.
We've run into BIOS that hand us 4-bit access width requests for T-state control when the code expected only multipls of 8-bits. Round up. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Li Shaohua <shaohua.li@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'drivers/acpi/osl.c')
-rw-r--r--drivers/acpi/osl.c25
1 files changed, 9 insertions, 16 deletions
diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c
index aabc6ca4a81c..e3a673a00845 100644
--- a/drivers/acpi/osl.c
+++ b/drivers/acpi/osl.c
@@ -387,17 +387,14 @@ acpi_status acpi_os_read_port(acpi_io_address port, u32 * value, u32 width)
387 if (!value) 387 if (!value)
388 value = &dummy; 388 value = &dummy;
389 389
390 switch (width) { 390 *value = 0;
391 case 8: 391 if (width <= 8) {
392 *(u8 *) value = inb(port); 392 *(u8 *) value = inb(port);
393 break; 393 } else if (width <= 16) {
394 case 16:
395 *(u16 *) value = inw(port); 394 *(u16 *) value = inw(port);
396 break; 395 } else if (width <= 32) {
397 case 32:
398 *(u32 *) value = inl(port); 396 *(u32 *) value = inl(port);
399 break; 397 } else {
400 default:
401 BUG(); 398 BUG();
402 } 399 }
403 400
@@ -408,17 +405,13 @@ EXPORT_SYMBOL(acpi_os_read_port);
408 405
409acpi_status acpi_os_write_port(acpi_io_address port, u32 value, u32 width) 406acpi_status acpi_os_write_port(acpi_io_address port, u32 value, u32 width)
410{ 407{
411 switch (width) { 408 if (width <= 8) {
412 case 8:
413 outb(value, port); 409 outb(value, port);
414 break; 410 } else if (width <= 16) {
415 case 16:
416 outw(value, port); 411 outw(value, port);
417 break; 412 } else if (width <= 32) {
418 case 32:
419 outl(value, port); 413 outl(value, port);
420 break; 414 } else {
421 default:
422 BUG(); 415 BUG();
423 } 416 }
424 417