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authorPavel Pisa <ppisa4lists@pikron.com>2007-02-05 19:10:20 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-11 11:46:23 -0500
commitd7ea10d9cbddd49bab282adef805203a36e43101 (patch)
tree749ee4224b139d9898dad6a3e1cd5406c00c3ea5 /crypto/sha1.c
parent8c0b254b7efaa7941b3acfe790dd16597b0964b3 (diff)
[ARM] i.MX serial: fix IRQ allocation
If RTS interrupt is caused by RTS senzing logic inside i.MX UART module the IRQ type cannot be set. It applies only for interrupts going through GPIO layer. The problem has been noticed by Konstantin Kletschke some time ago. No IRQF_TRIGGER set_type function for IRQ 26 (MPU) I would not change type to fixed 0, because it could be possible to use different GPIO MX1 pin for RTS in the theory. On the other hand it is only for documentation purposes now, because RTS read code would have to be adjusted in such case. Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'crypto/sha1.c')
0 files changed, 0 insertions, 0 deletions