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author | Dan Williams <dan.j.williams@intel.com> | 2008-07-17 20:59:55 -0400 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2008-07-17 20:59:55 -0400 |
commit | d2c52b7983b95bb3fc2a784e479f832f142d4523 (patch) | |
tree | 7bc37e7438cee523496674adcd97034df764af47 /crypto/async_tx/async_xor.c | |
parent | 669ab0b210f9bd15d94d4d6a49ae13366a85e4da (diff) |
async_tx: export async_tx_quiesce
Replace open coded "wait and acknowledge" instances with async_tx_quiesce.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'crypto/async_tx/async_xor.c')
-rw-r--r-- | crypto/async_tx/async_xor.c | 37 |
1 files changed, 2 insertions, 35 deletions
diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index 19d16e452bcc..689ecce73ee1 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c | |||
@@ -30,24 +30,6 @@ | |||
30 | #include <linux/raid/xor.h> | 30 | #include <linux/raid/xor.h> |
31 | #include <linux/async_tx.h> | 31 | #include <linux/async_tx.h> |
32 | 32 | ||
33 | /** | ||
34 | * async_tx_quiesce - ensure tx is complete and freeable upon return | ||
35 | * @tx - transaction to quiesce | ||
36 | */ | ||
37 | static void async_tx_quiesce(struct dma_async_tx_descriptor **tx) | ||
38 | { | ||
39 | if (*tx) { | ||
40 | /* if ack is already set then we cannot be sure | ||
41 | * we are referring to the correct operation | ||
42 | */ | ||
43 | BUG_ON(async_tx_test_ack(*tx)); | ||
44 | if (dma_wait_for_async_tx(*tx) == DMA_ERROR) | ||
45 | panic("DMA_ERROR waiting for transaction\n"); | ||
46 | async_tx_ack(*tx); | ||
47 | *tx = NULL; | ||
48 | } | ||
49 | } | ||
50 | |||
51 | /* do_async_xor - dma map the pages and perform the xor with an engine. | 33 | /* do_async_xor - dma map the pages and perform the xor with an engine. |
52 | * This routine is marked __always_inline so it can be compiled away | 34 | * This routine is marked __always_inline so it can be compiled away |
53 | * when CONFIG_DMA_ENGINE=n | 35 | * when CONFIG_DMA_ENGINE=n |
@@ -219,15 +201,7 @@ async_xor(struct page *dest, struct page **src_list, unsigned int offset, | |||
219 | } | 201 | } |
220 | 202 | ||
221 | /* wait for any prerequisite operations */ | 203 | /* wait for any prerequisite operations */ |
222 | if (depend_tx) { | 204 | async_tx_quiesce(&depend_tx); |
223 | /* if ack is already set then we cannot be sure | ||
224 | * we are referring to the correct operation | ||
225 | */ | ||
226 | BUG_ON(async_tx_test_ack(depend_tx)); | ||
227 | if (dma_wait_for_async_tx(depend_tx) == DMA_ERROR) | ||
228 | panic("%s: DMA_ERROR waiting for depend_tx\n", | ||
229 | __func__); | ||
230 | } | ||
231 | 205 | ||
232 | do_sync_xor(dest, src_list, offset, src_cnt, len, | 206 | do_sync_xor(dest, src_list, offset, src_cnt, len, |
233 | flags, depend_tx, cb_fn, cb_param); | 207 | flags, depend_tx, cb_fn, cb_param); |
@@ -309,17 +283,10 @@ async_xor_zero_sum(struct page *dest, struct page **src_list, | |||
309 | tx = async_xor(dest, src_list, offset, src_cnt, len, xor_flags, | 283 | tx = async_xor(dest, src_list, offset, src_cnt, len, xor_flags, |
310 | depend_tx, NULL, NULL); | 284 | depend_tx, NULL, NULL); |
311 | 285 | ||
312 | if (tx) { | 286 | async_tx_quiesce(&tx); |
313 | if (dma_wait_for_async_tx(tx) == DMA_ERROR) | ||
314 | panic("%s: DMA_ERROR waiting for tx\n", | ||
315 | __func__); | ||
316 | async_tx_ack(tx); | ||
317 | } | ||
318 | 287 | ||
319 | *result = page_is_zero(dest, offset, len) ? 0 : 1; | 288 | *result = page_is_zero(dest, offset, len) ? 0 : 1; |
320 | 289 | ||
321 | tx = NULL; | ||
322 | |||
323 | async_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param); | 290 | async_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param); |
324 | } | 291 | } |
325 | 292 | ||