MIPS: Alchemy: DB1200: Disable cascade IRQ in handler

Disable the cascade IRQ in the cascade handler.  This is required to
get the DB1300 working, and also gets rid of all spurious interrupts
previously observed on the DB1200; so Config[OD] can be disabled
again for better performance.

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/2708/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 4 insertions, 7 deletions

diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index 596ad00e7f05..463d2c4d9441 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -89,8 +89,12 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
 {
         unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
 
+        disable_irq_nosync(irq);
+
         for ( ; bisr; bisr &= bisr - 1)
                 generic_handle_irq(bcsr_csc_base + __ffs(bisr));
+
+        enable_irq(irq);
 }
 
 /* NOTE: both the enable and mask bits must be cleared, otherwise the
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
index 1dac4f27d334..4a8980027ecf 100644
--- a/arch/mips/alchemy/devboards/db1200/setup.c
+++ b/arch/mips/alchemy/devboards/db1200/setup.c
@@ -23,13 +23,6 @@ void __init board_setup(void)
         unsigned long freq0, clksrc, div, pfc;
         unsigned short whoami;
 
-        /* Set Config[OD] (disable overlapping bus transaction):
-         * This gets rid of a _lot_ of spurious interrupts (especially
-         * wrt. IDE); but incurs ~10% performance hit in some
-         * cpu-bound applications.
-         */
-        set_c0_config(1 << 19);
-
         bcsr_init(DB1200_BCSR_PHYS_ADDR,
                   DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);