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authorYinghai Lu <yhlu.kernel@gmail.com>2008-09-09 19:40:37 -0400
committerIngo Molnar <mingo@elte.hu>2008-09-10 02:21:05 -0400
commit879d792b66d633bbe466974f61d1acc9aa8c78eb (patch)
tree4e1367fcde52da73daa6558606ce34aa39547e9d /arch
parent58602c1681bdfa1a0deaa5574b8a72d6e30c0e97 (diff)
x86: let intel 64-bit use intel.c
now that arch/x86/kernel/cpu/intel_64.c and arch/x86/kernel/cpu/intel.c are equal, drop arch/x86/kernel/cpu/intel_64.c and fix up the glue. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/Kconfig.cpu10
-rw-r--r--arch/x86/kernel/cpu/Makefile3
-rw-r--r--arch/x86/kernel/cpu/intel_64.c366
3 files changed, 2 insertions, 377 deletions
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 1b29d6a87563..6761848329fa 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -423,17 +423,9 @@ menuconfig PROCESSOR_SELECT
423 This lets you choose what x86 vendor support code your kernel 423 This lets you choose what x86 vendor support code your kernel
424 will include. 424 will include.
425 425
426config CPU_SUP_INTEL_32 426config CPU_SUP_INTEL
427 default y 427 default y
428 bool "Support Intel processors" if PROCESSOR_SELECT 428 bool "Support Intel processors" if PROCESSOR_SELECT
429 depends on !64BIT
430 help
431 This enables extended support for Intel processors
432
433config CPU_SUP_INTEL_64
434 default y
435 bool "Support Intel processors" if PROCESSOR_SELECT
436 depends on 64BIT
437 help 429 help
438 This enables extended support for Intel processors 430 This enables extended support for Intel processors
439 431
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 510d1bcb058a..7f0b45a5d788 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -8,8 +8,7 @@ obj-y += proc.o capflags.o powerflags.o common.o
8obj-$(CONFIG_X86_32) += bugs.o cmpxchg.o 8obj-$(CONFIG_X86_32) += bugs.o cmpxchg.o
9obj-$(CONFIG_X86_64) += bugs_64.o 9obj-$(CONFIG_X86_64) += bugs_64.o
10 10
11obj-$(CONFIG_CPU_SUP_INTEL_32) += intel.o 11obj-$(CONFIG_CPU_SUP_INTEL) += intel.o
12obj-$(CONFIG_CPU_SUP_INTEL_64) += intel_64.o
13obj-$(CONFIG_CPU_SUP_AMD) += amd.o 12obj-$(CONFIG_CPU_SUP_AMD) += amd.o
14obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o 13obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o
15obj-$(CONFIG_CPU_SUP_CENTAUR_32) += centaur.o 14obj-$(CONFIG_CPU_SUP_CENTAUR_32) += centaur.o
diff --git a/arch/x86/kernel/cpu/intel_64.c b/arch/x86/kernel/cpu/intel_64.c
deleted file mode 100644
index 365a008080c2..000000000000
--- a/arch/x86/kernel/cpu/intel_64.c
+++ /dev/null
@@ -1,366 +0,0 @@
1#include <linux/init.h>
2#include <linux/kernel.h>
3
4#include <linux/string.h>
5#include <linux/bitops.h>
6#include <linux/smp.h>
7#include <linux/thread_info.h>
8#include <linux/module.h>
9
10#include <asm/processor.h>
11#include <asm/pgtable.h>
12#include <asm/msr.h>
13#include <asm/uaccess.h>
14#include <asm/ptrace.h>
15#include <asm/ds.h>
16#include <asm/bugs.h>
17
18#ifdef CONFIG_X86_64
19#include <asm/topology.h>
20#include <asm/numa_64.h>
21#endif
22
23#include "cpu.h"
24
25#ifdef CONFIG_X86_LOCAL_APIC
26#include <asm/mpspec.h>
27#include <asm/apic.h>
28#include <mach_apic.h>
29#endif
30
31static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
32{
33 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
34 (c->x86 == 0x6 && c->x86_model >= 0x0e))
35 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
36
37#ifdef CONFIG_X86_64
38 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
39#else
40 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
41 if (c->x86 == 15 && c->x86_cache_alignment == 64)
42 c->x86_cache_alignment = 128;
43#endif
44}
45
46#ifdef CONFIG_X86_32
47/*
48 * Early probe support logic for ppro memory erratum #50
49 *
50 * This is called before we do cpu ident work
51 */
52
53int __cpuinit ppro_with_ram_bug(void)
54{
55 /* Uses data from early_cpu_detect now */
56 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
57 boot_cpu_data.x86 == 6 &&
58 boot_cpu_data.x86_model == 1 &&
59 boot_cpu_data.x86_mask < 8) {
60 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
61 return 1;
62 }
63 return 0;
64}
65
66
67/*
68 * P4 Xeon errata 037 workaround.
69 * Hardware prefetcher may cause stale data to be loaded into the cache.
70 */
71static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
72{
73 unsigned long lo, hi;
74
75 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
76 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
77 if ((lo & (1<<9)) == 0) {
78 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
79 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
80 lo |= (1<<9); /* Disable hw prefetching */
81 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
82 }
83 }
84}
85
86
87
88#ifdef CONFIG_X86_F00F_BUG
89static void __cpuinit trap_init_f00f_bug(void)
90{
91 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
92
93 /*
94 * Update the IDT descriptor and reload the IDT so that
95 * it uses the read-only mapped virtual address.
96 */
97 idt_descr.address = fix_to_virt(FIX_F00F_IDT);
98 load_idt(&idt_descr);
99}
100#endif
101#endif
102
103static void __cpuinit srat_detect_node(void)
104{
105#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
106 unsigned node;
107 int cpu = smp_processor_id();
108 int apicid = hard_smp_processor_id();
109
110 /* Don't do the funky fallback heuristics the AMD version employs
111 for now. */
112 node = apicid_to_node[apicid];
113 if (node == NUMA_NO_NODE || !node_online(node))
114 node = first_node(node_online_map);
115 numa_set_node(cpu, node);
116
117 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
118#endif
119}
120
121/*
122 * find out the number of processor cores on the die
123 */
124static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
125{
126 unsigned int eax, ebx, ecx, edx;
127
128 if (c->cpuid_level < 4)
129 return 1;
130
131 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
132 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
133 if (eax & 0x1f)
134 return ((eax >> 26) + 1);
135 else
136 return 1;
137}
138
139static void __cpuinit init_intel(struct cpuinfo_x86 *c)
140{
141 unsigned int l2 = 0;
142 char *p = NULL;
143
144 early_init_intel(c);
145
146#ifdef CONFIG_X86_F00F_BUG
147 /*
148 * All current models of Pentium and Pentium with MMX technology CPUs
149 * have the F0 0F bug, which lets nonprivileged users lock up the system.
150 * Note that the workaround only should be initialized once...
151 */
152 c->f00f_bug = 0;
153 if (!paravirt_enabled() && c->x86 == 5) {
154 static int f00f_workaround_enabled;
155
156 c->f00f_bug = 1;
157 if (!f00f_workaround_enabled) {
158 trap_init_f00f_bug();
159 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
160 f00f_workaround_enabled = 1;
161 }
162 }
163#endif
164
165 l2 = init_intel_cacheinfo(c);
166 if (c->cpuid_level > 9) {
167 unsigned eax = cpuid_eax(10);
168 /* Check for version and the number of counters */
169 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
170 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
171 }
172
173#ifdef CONFIG_X86_32
174 /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
175 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
176 clear_cpu_cap(c, X86_FEATURE_SEP);
177
178 /*
179 * Names for the Pentium II/Celeron processors
180 * detectable only by also checking the cache size.
181 * Dixon is NOT a Celeron.
182 */
183 if (c->x86 == 6) {
184 switch (c->x86_model) {
185 case 5:
186 if (c->x86_mask == 0) {
187 if (l2 == 0)
188 p = "Celeron (Covington)";
189 else if (l2 == 256)
190 p = "Mobile Pentium II (Dixon)";
191 }
192 break;
193
194 case 6:
195 if (l2 == 128)
196 p = "Celeron (Mendocino)";
197 else if (c->x86_mask == 0 || c->x86_mask == 5)
198 p = "Celeron-A";
199 break;
200
201 case 8:
202 if (l2 == 128)
203 p = "Celeron (Coppermine)";
204 break;
205 }
206 }
207
208 if (p)
209 strcpy(c->x86_model_id, p);
210
211 Intel_errata_workarounds(c);
212
213#ifdef CONFIG_X86_INTEL_USERCOPY
214 /*
215 * Set up the preferred alignment for movsl bulk memory moves
216 */
217 switch (c->x86) {
218 case 4: /* 486: untested */
219 break;
220 case 5: /* Old Pentia: untested */
221 break;
222 case 6: /* PII/PIII only like movsl with 8-byte alignment */
223 movsl_mask.mask = 7;
224 break;
225 case 15: /* P4 is OK down to 8-byte alignment */
226 movsl_mask.mask = 7;
227 break;
228 }
229#endif
230
231#endif
232
233 if (cpu_has_xmm2)
234 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
235 if (cpu_has_ds) {
236 unsigned int l1;
237 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
238 if (!(l1 & (1<<11)))
239 set_cpu_cap(c, X86_FEATURE_BTS);
240 if (!(l1 & (1<<12)))
241 set_cpu_cap(c, X86_FEATURE_PEBS);
242 ds_init_intel(c);
243 }
244
245#ifdef CONFIG_X86_64
246 if (c->x86 == 15)
247 c->x86_cache_alignment = c->x86_clflush_size * 2;
248 if (c->x86 == 6)
249 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
250#else
251 if (c->x86 == 15)
252 set_cpu_cap(c, X86_FEATURE_P4);
253 if (c->x86 == 6)
254 set_cpu_cap(c, X86_FEATURE_P3);
255
256 if (cpu_has_bts)
257 ptrace_bts_init_intel(c);
258
259 /*
260 * See if we have a good local APIC by checking for buggy Pentia,
261 * i.e. all B steppings and the C2 stepping of P54C when using their
262 * integrated APIC (see 11AP erratum in "Pentium Processor
263 * Specification Update").
264 */
265 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
266 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
267 set_cpu_cap(c, X86_FEATURE_11AP);
268
269#ifdef CONFIG_X86_NUMAQ
270 numaq_tsc_disable();
271#endif
272#endif
273
274 detect_extended_topology(c);
275 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
276 /*
277 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
278 * detection.
279 */
280 c->x86_max_cores = intel_num_cpu_cores(c);
281#ifdef CONFIG_X86_32
282 detect_ht(c);
283#endif
284 }
285
286 /* Work around errata */
287 srat_detect_node();
288}
289
290#ifdef CONFIG_X86_32
291static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
292{
293 /*
294 * Intel PIII Tualatin. This comes in two flavours.
295 * One has 256kb of cache, the other 512. We have no way
296 * to determine which, so we use a boottime override
297 * for the 512kb model, and assume 256 otherwise.
298 */
299 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
300 size = 256;
301 return size;
302}
303#endif
304
305static struct cpu_dev intel_cpu_dev __cpuinitdata = {
306 .c_vendor = "Intel",
307 .c_ident = { "GenuineIntel" },
308#ifdef CONFIG_X86_32
309 .c_models = {
310 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
311 {
312 [0] = "486 DX-25/33",
313 [1] = "486 DX-50",
314 [2] = "486 SX",
315 [3] = "486 DX/2",
316 [4] = "486 SL",
317 [5] = "486 SX/2",
318 [7] = "486 DX/2-WB",
319 [8] = "486 DX/4",
320 [9] = "486 DX/4-WB"
321 }
322 },
323 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
324 {
325 [0] = "Pentium 60/66 A-step",
326 [1] = "Pentium 60/66",
327 [2] = "Pentium 75 - 200",
328 [3] = "OverDrive PODP5V83",
329 [4] = "Pentium MMX",
330 [7] = "Mobile Pentium 75 - 200",
331 [8] = "Mobile Pentium MMX"
332 }
333 },
334 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
335 {
336 [0] = "Pentium Pro A-step",
337 [1] = "Pentium Pro",
338 [3] = "Pentium II (Klamath)",
339 [4] = "Pentium II (Deschutes)",
340 [5] = "Pentium II (Deschutes)",
341 [6] = "Mobile Pentium II",
342 [7] = "Pentium III (Katmai)",
343 [8] = "Pentium III (Coppermine)",
344 [10] = "Pentium III (Cascades)",
345 [11] = "Pentium III (Tualatin)",
346 }
347 },
348 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
349 {
350 [0] = "Pentium 4 (Unknown)",
351 [1] = "Pentium 4 (Willamette)",
352 [2] = "Pentium 4 (Northwood)",
353 [4] = "Pentium 4 (Foster)",
354 [5] = "Pentium 4 (Foster)",
355 }
356 },
357 },
358 .c_size_cache = intel_size_cache,
359#endif
360 .c_early_init = early_init_intel,
361 .c_init = init_intel,
362 .c_x86_vendor = X86_VENDOR_INTEL,
363};
364
365cpu_dev_register(intel_cpu_dev);
366
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