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authorLinus Torvalds <torvalds@linux-foundation.org>2011-07-22 20:04:55 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-07-22 20:04:55 -0400
commit3e0b8df79ddb8955d2cce5e858972a9cfe763384 (patch)
treedbe35b7403c462aaaabb4176c02229feb991be1c /arch
parent805120795947008612ef64618bba8a6aa30cf88b (diff)
parentae90c232be376bd8a283f3b6fb37cb5bd2635d67 (diff)
Merge branch 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, UV: Correct UV2 BAU destination timeout x86, UV: Correct failed topology memory leak x86, UV: Remove cpumask_t from the stack x86, UV: Rename hubmask to pnmask x86, UV: Correct reset_with_ipi() x86, UV: Allow for non-consecutive sockets x86, UV: Inline header file functions x86, UV: Fix smp_processor_id() use in a preemptable region x66, UV: Enable 64-bit ACPI MFCG support for SGI UV2 platform x86, UV: Clean up uv_mmrs.h
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/include/asm/uv/uv_bau.h59
-rw-r--r--arch/x86/include/asm/uv/uv_mmrs.h2889
-rw-r--r--arch/x86/pci/mmconfig-shared.c3
-rw-r--r--arch/x86/platform/uv/tlb_uv.c69
4 files changed, 1691 insertions, 1329 deletions
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index a291c40efd43..37d369859c8e 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -67,7 +67,7 @@
67 * we're using 655us, similar to UV1: 65 units of 10us 67 * we're using 655us, similar to UV1: 65 units of 10us
68 */ 68 */
69#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL) 69#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
70#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (65*10UL) 70#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
71 71
72#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \ 72#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
73 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \ 73 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
@@ -106,12 +106,20 @@
106#define DS_SOURCE_TIMEOUT 3 106#define DS_SOURCE_TIMEOUT 3
107/* 107/*
108 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2 108 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
109 * values 1 and 5 will not occur 109 * values 1 and 3 will not occur
110 * Decoded meaning ERROR BUSY AUX ERR
111 * ------------------------------- ---- ----- -------
112 * IDLE 0 0 0
113 * BUSY (active) 0 1 0
114 * SW Ack Timeout (destination) 1 0 0
115 * SW Ack INTD rejected (strong NACK) 1 0 1
116 * Source Side Time Out Detected 1 1 0
117 * Destination Side PUT Failed 1 1 1
110 */ 118 */
111#define UV2H_DESC_IDLE 0 119#define UV2H_DESC_IDLE 0
112#define UV2H_DESC_DEST_TIMEOUT 2 120#define UV2H_DESC_BUSY 2
113#define UV2H_DESC_DEST_STRONG_NACK 3 121#define UV2H_DESC_DEST_TIMEOUT 4
114#define UV2H_DESC_BUSY 4 122#define UV2H_DESC_DEST_STRONG_NACK 5
115#define UV2H_DESC_SOURCE_TIMEOUT 6 123#define UV2H_DESC_SOURCE_TIMEOUT 6
116#define UV2H_DESC_DEST_PUT_ERR 7 124#define UV2H_DESC_DEST_PUT_ERR 7
117 125
@@ -183,7 +191,7 @@
183 * 'base_dest_nasid' field of the header corresponds to the 191 * 'base_dest_nasid' field of the header corresponds to the
184 * destination nodeID associated with that specified bit. 192 * destination nodeID associated with that specified bit.
185 */ 193 */
186struct bau_targ_hubmask { 194struct pnmask {
187 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)]; 195 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
188}; 196};
189 197
@@ -314,7 +322,7 @@ struct bau_msg_header {
314 * Should be 64 bytes 322 * Should be 64 bytes
315 */ 323 */
316struct bau_desc { 324struct bau_desc {
317 struct bau_targ_hubmask distribution; 325 struct pnmask distribution;
318 /* 326 /*
319 * message template, consisting of header and payload: 327 * message template, consisting of header and payload:
320 */ 328 */
@@ -488,6 +496,7 @@ struct bau_control {
488 struct bau_control *uvhub_master; 496 struct bau_control *uvhub_master;
489 struct bau_control *socket_master; 497 struct bau_control *socket_master;
490 struct ptc_stats *statp; 498 struct ptc_stats *statp;
499 cpumask_t *cpumask;
491 unsigned long timeout_interval; 500 unsigned long timeout_interval;
492 unsigned long set_bau_on_time; 501 unsigned long set_bau_on_time;
493 atomic_t active_descriptor_count; 502 atomic_t active_descriptor_count;
@@ -526,90 +535,90 @@ struct bau_control {
526 struct hub_and_pnode *thp; 535 struct hub_and_pnode *thp;
527}; 536};
528 537
529static unsigned long read_mmr_uv2_status(void) 538static inline unsigned long read_mmr_uv2_status(void)
530{ 539{
531 return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2); 540 return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
532} 541}
533 542
534static void write_mmr_data_broadcast(int pnode, unsigned long mmr_image) 543static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
535{ 544{
536 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image); 545 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
537} 546}
538 547
539static void write_mmr_descriptor_base(int pnode, unsigned long mmr_image) 548static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
540{ 549{
541 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image); 550 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
542} 551}
543 552
544static void write_mmr_activation(unsigned long index) 553static inline void write_mmr_activation(unsigned long index)
545{ 554{
546 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index); 555 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
547} 556}
548 557
549static void write_gmmr_activation(int pnode, unsigned long mmr_image) 558static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
550{ 559{
551 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image); 560 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
552} 561}
553 562
554static void write_mmr_payload_first(int pnode, unsigned long mmr_image) 563static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
555{ 564{
556 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image); 565 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
557} 566}
558 567
559static void write_mmr_payload_tail(int pnode, unsigned long mmr_image) 568static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
560{ 569{
561 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image); 570 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
562} 571}
563 572
564static void write_mmr_payload_last(int pnode, unsigned long mmr_image) 573static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
565{ 574{
566 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image); 575 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
567} 576}
568 577
569static void write_mmr_misc_control(int pnode, unsigned long mmr_image) 578static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
570{ 579{
571 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image); 580 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
572} 581}
573 582
574static unsigned long read_mmr_misc_control(int pnode) 583static inline unsigned long read_mmr_misc_control(int pnode)
575{ 584{
576 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL); 585 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
577} 586}
578 587
579static void write_mmr_sw_ack(unsigned long mr) 588static inline void write_mmr_sw_ack(unsigned long mr)
580{ 589{
581 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr); 590 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
582} 591}
583 592
584static unsigned long read_mmr_sw_ack(void) 593static inline unsigned long read_mmr_sw_ack(void)
585{ 594{
586 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); 595 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
587} 596}
588 597
589static unsigned long read_gmmr_sw_ack(int pnode) 598static inline unsigned long read_gmmr_sw_ack(int pnode)
590{ 599{
591 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); 600 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
592} 601}
593 602
594static void write_mmr_data_config(int pnode, unsigned long mr) 603static inline void write_mmr_data_config(int pnode, unsigned long mr)
595{ 604{
596 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr); 605 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
597} 606}
598 607
599static inline int bau_uvhub_isset(int uvhub, struct bau_targ_hubmask *dstp) 608static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
600{ 609{
601 return constant_test_bit(uvhub, &dstp->bits[0]); 610 return constant_test_bit(uvhub, &dstp->bits[0]);
602} 611}
603static inline void bau_uvhub_set(int pnode, struct bau_targ_hubmask *dstp) 612static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
604{ 613{
605 __set_bit(pnode, &dstp->bits[0]); 614 __set_bit(pnode, &dstp->bits[0]);
606} 615}
607static inline void bau_uvhubs_clear(struct bau_targ_hubmask *dstp, 616static inline void bau_uvhubs_clear(struct pnmask *dstp,
608 int nbits) 617 int nbits)
609{ 618{
610 bitmap_zero(&dstp->bits[0], nbits); 619 bitmap_zero(&dstp->bits[0], nbits);
611} 620}
612static inline int bau_uvhub_weight(struct bau_targ_hubmask *dstp) 621static inline int bau_uvhub_weight(struct pnmask *dstp)
613{ 622{
614 return bitmap_weight((unsigned long *)&dstp->bits[0], 623 return bitmap_weight((unsigned long *)&dstp->bits[0],
615 UV_DISTRIBUTION_SIZE); 624 UV_DISTRIBUTION_SIZE);
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index 4be52c863448..10474fb1185d 100644
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -61,1689 +61,2016 @@
61/* Compat: if this #define is present, UV headers support UV2 */ 61/* Compat: if this #define is present, UV headers support UV2 */
62#define UV2_HUB_IS_SUPPORTED 1 62#define UV2_HUB_IS_SUPPORTED 1
63 63
64/* KABI compat: if this #define is present, KABI hacks are present */
65#define UV2_HUB_KABI_HACKS 1
66
67/* ========================================================================= */ 64/* ========================================================================= */
68/* UVH_BAU_DATA_BROADCAST */ 65/* UVH_BAU_DATA_BROADCAST */
69/* ========================================================================= */ 66/* ========================================================================= */
70#define UVH_BAU_DATA_BROADCAST 0x61688UL 67#define UVH_BAU_DATA_BROADCAST 0x61688UL
71#define UVH_BAU_DATA_BROADCAST_32 0x440 68#define UVH_BAU_DATA_BROADCAST_32 0x440
72 69
73#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 70#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0
74#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL 71#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
75 72
76union uvh_bau_data_broadcast_u { 73union uvh_bau_data_broadcast_u {
77 unsigned long v; 74 unsigned long v;
78 struct uvh_bau_data_broadcast_s { 75 struct uvh_bau_data_broadcast_s {
79 unsigned long enable : 1; /* RW */ 76 unsigned long enable:1; /* RW */
80 unsigned long rsvd_1_63: 63; /* */ 77 unsigned long rsvd_1_63:63;
81 } s; 78 } s;
82}; 79};
83 80
84/* ========================================================================= */ 81/* ========================================================================= */
85/* UVH_BAU_DATA_CONFIG */ 82/* UVH_BAU_DATA_CONFIG */
86/* ========================================================================= */ 83/* ========================================================================= */
87#define UVH_BAU_DATA_CONFIG 0x61680UL 84#define UVH_BAU_DATA_CONFIG 0x61680UL
88#define UVH_BAU_DATA_CONFIG_32 0x438 85#define UVH_BAU_DATA_CONFIG_32 0x438
89 86
90#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 87#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
91#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL 88#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
92#define UVH_BAU_DATA_CONFIG_DM_SHFT 8 89#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
93#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL 90#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
94#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 91#define UVH_BAU_DATA_CONFIG_P_SHFT 13
95#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL 92#define UVH_BAU_DATA_CONFIG_T_SHFT 15
96#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12 93#define UVH_BAU_DATA_CONFIG_M_SHFT 16
97#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL 94#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
98#define UVH_BAU_DATA_CONFIG_P_SHFT 13 95#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
99#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL 96#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
100#define UVH_BAU_DATA_CONFIG_T_SHFT 15 97#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
101#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL 98#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
102#define UVH_BAU_DATA_CONFIG_M_SHFT 16 99#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
103#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL 100#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
104#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 101#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
105#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 102#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
106 103
107union uvh_bau_data_config_u { 104union uvh_bau_data_config_u {
108 unsigned long v; 105 unsigned long v;
109 struct uvh_bau_data_config_s { 106 struct uvh_bau_data_config_s {
110 unsigned long vector_ : 8; /* RW */ 107 unsigned long vector_:8; /* RW */
111 unsigned long dm : 3; /* RW */ 108 unsigned long dm:3; /* RW */
112 unsigned long destmode : 1; /* RW */ 109 unsigned long destmode:1; /* RW */
113 unsigned long status : 1; /* RO */ 110 unsigned long status:1; /* RO */
114 unsigned long p : 1; /* RO */ 111 unsigned long p:1; /* RO */
115 unsigned long rsvd_14 : 1; /* */ 112 unsigned long rsvd_14:1;
116 unsigned long t : 1; /* RO */ 113 unsigned long t:1; /* RO */
117 unsigned long m : 1; /* RW */ 114 unsigned long m:1; /* RW */
118 unsigned long rsvd_17_31: 15; /* */ 115 unsigned long rsvd_17_31:15;
119 unsigned long apic_id : 32; /* RW */ 116 unsigned long apic_id:32; /* RW */
120 } s; 117 } s;
121}; 118};
122 119
123/* ========================================================================= */ 120/* ========================================================================= */
124/* UVH_EVENT_OCCURRED0 */ 121/* UVH_EVENT_OCCURRED0 */
125/* ========================================================================= */ 122/* ========================================================================= */
126#define UVH_EVENT_OCCURRED0 0x70000UL 123#define UVH_EVENT_OCCURRED0 0x70000UL
127#define UVH_EVENT_OCCURRED0_32 0x5e8 124#define UVH_EVENT_OCCURRED0_32 0x5e8
128 125
129#define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0 126#define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
130#define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 127#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
131#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 128#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
132#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL 129#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3
133#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 130#define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4
134#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL 131#define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5
135#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3 132#define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6
136#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL 133#define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
137#define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4 134#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
138#define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL 135#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
139#define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5 136#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
140#define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL 137#define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
141#define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6 138#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
142#define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL 139#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
143#define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7 140#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
144#define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL 141#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
145#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 142#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
146#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL 143#define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
147#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 144#define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
148#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL 145#define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
149#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 146#define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
150#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL 147#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
151#define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 148#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
152#define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 149#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
153#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 150#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
154#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL 151#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
155#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 152#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
156#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL 153#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
157#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 154#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
158#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL 155#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
159#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15 156#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
160#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL 157#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
161#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16 158#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
162#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL 159#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
163#define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17 160#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
164#define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL 161#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
165#define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18 162#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
166#define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL 163#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
167#define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19 164#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
168#define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL 165#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
169#define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20 166#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
170#define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL 167#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
171#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21 168#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
172#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL 169#define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43
173#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22 170#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
174#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL 171#define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45
175#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23 172#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
176#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL 173#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
177#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24 174#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
178#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL 175#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
179#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25 176#define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
180#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL 177#define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51
181#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26 178#define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52
182#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL 179#define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53
183#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27 180#define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54
184#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL 181#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55
185#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28 182#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
186#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL 183#define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
187#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29 184#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
188#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL 185#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
189#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30 186#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
190#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL 187#define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
191#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31 188#define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
192#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL 189#define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
193#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32 190#define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
194#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL 191#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
195#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33 192#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
196#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL 193#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
197#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34 194#define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
198#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL 195#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
199#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35 196#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
200#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL 197#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
201#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36 198#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
202#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL 199#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
203#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37 200#define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
204#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL 201#define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
205#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38 202#define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
206#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL 203#define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
207#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39 204#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
208#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL 205#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
209#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40 206#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
210#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL 207#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
211#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41 208#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
212#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL 209#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
213#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42 210#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
214#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL 211#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
215#define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43 212#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
216#define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL 213#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
217#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44 214#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
218#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL 215#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
219#define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45 216#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
220#define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL 217#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
221#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46 218#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
222#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL 219#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
223#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47 220#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
224#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL 221#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
225#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48 222#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
226#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL 223#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
227#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49 224#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
228#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL 225#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
229#define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50 226#define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
230#define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL 227#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
231#define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51 228#define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
232#define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL 229#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
233#define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52 230#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
234#define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL 231#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
235#define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53 232#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
236#define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL 233#define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
237#define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54 234#define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
238#define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL 235#define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
239#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55 236#define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
240#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL 237#define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
241#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 238#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
242#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL 239#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
243 240
244#define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0 241#define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
245#define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 242#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1
246#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 243#define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2
247#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 244#define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
248#define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2 245#define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4
249#define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL 246#define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5
250#define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 247#define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6
251#define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL 248#define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7
252#define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4 249#define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
253#define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL 250#define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
254#define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5 251#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
255#define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL 252#define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
256#define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6 253#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
257#define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL 254#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
258#define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7 255#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
259#define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL 256#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15
260#define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 257#define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16
261#define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL 258#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
262#define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 259#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
263#define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL 260#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
264#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 261#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
265#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 262#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
266#define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 263#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
267#define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 264#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
268#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 265#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
269#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL 266#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
270#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 267#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
271#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL 268#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
272#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 269#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
273#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL 270#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
274#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15 271#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
275#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL 272#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
276#define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16 273#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
277#define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL 274#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
278#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 275#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
279#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 276#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
280#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 277#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
281#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 278#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
282#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 279#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
283#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 280#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
284#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 281#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
285#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 282#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
286#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 283#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
287#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 284#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
288#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 285#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
289#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 286#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
290#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 287#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
291#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 288#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
292#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 289#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
293#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 290#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
294#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 291#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
295#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 292#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
296#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 293#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
297#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 294#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53
298#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 295#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
299#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 296#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
300#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 297#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
301#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 298#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
302#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 299#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
303#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 300#define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
304#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 301#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
305#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 302#define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
306#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 303#define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
307#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 304#define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL
308#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 305#define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL
309#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 306#define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL
310#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 307#define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL
311#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 308#define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
312#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 309#define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
313#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 310#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
314#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 311#define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
315#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 312#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
316#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 313#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
317#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 314#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
318#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 315#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL
319#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 316#define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL
320#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 317#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
321#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 318#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
322#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 319#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
323#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 320#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
324#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 321#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
325#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 322#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
326#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 323#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
327#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 324#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
328#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 325#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
329#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 326#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
330#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 327#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
331#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 328#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
332#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 329#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
333#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 330#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
334#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 331#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
335#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 332#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
336#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 333#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
337#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 334#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
338#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 335#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
339#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 336#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
340#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 337#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
341#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 338#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
342#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 339#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
343#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 340#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
344#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 341#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
345#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 342#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
346#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 343#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
347#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 344#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
348#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 345#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
349#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 346#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
350#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53 347#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
351#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 348#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
352#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 349#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
353#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 350#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
354#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 351#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
355#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 352#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
356#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 353#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
357#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 354#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
358#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 355#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
359#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 356#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
360#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 357#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
361#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 358#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
362 359
363union uvh_event_occurred0_u { 360union uvh_event_occurred0_u {
364 unsigned long v; 361 unsigned long v;
365 struct uv1h_event_occurred0_s { 362 struct uv1h_event_occurred0_s {
366 unsigned long lb_hcerr : 1; /* RW, W1C */ 363 unsigned long lb_hcerr:1; /* RW, W1C */
367 unsigned long gr0_hcerr : 1; /* RW, W1C */ 364 unsigned long gr0_hcerr:1; /* RW, W1C */
368 unsigned long gr1_hcerr : 1; /* RW, W1C */ 365 unsigned long gr1_hcerr:1; /* RW, W1C */
369 unsigned long lh_hcerr : 1; /* RW, W1C */ 366 unsigned long lh_hcerr:1; /* RW, W1C */
370 unsigned long rh_hcerr : 1; /* RW, W1C */ 367 unsigned long rh_hcerr:1; /* RW, W1C */
371 unsigned long xn_hcerr : 1; /* RW, W1C */ 368 unsigned long xn_hcerr:1; /* RW, W1C */
372 unsigned long si_hcerr : 1; /* RW, W1C */ 369 unsigned long si_hcerr:1; /* RW, W1C */
373 unsigned long lb_aoerr0 : 1; /* RW, W1C */ 370 unsigned long lb_aoerr0:1; /* RW, W1C */
374 unsigned long gr0_aoerr0 : 1; /* RW, W1C */ 371 unsigned long gr0_aoerr0:1; /* RW, W1C */
375 unsigned long gr1_aoerr0 : 1; /* RW, W1C */ 372 unsigned long gr1_aoerr0:1; /* RW, W1C */
376 unsigned long lh_aoerr0 : 1; /* RW, W1C */ 373 unsigned long lh_aoerr0:1; /* RW, W1C */
377 unsigned long rh_aoerr0 : 1; /* RW, W1C */ 374 unsigned long rh_aoerr0:1; /* RW, W1C */
378 unsigned long xn_aoerr0 : 1; /* RW, W1C */ 375 unsigned long xn_aoerr0:1; /* RW, W1C */
379 unsigned long si_aoerr0 : 1; /* RW, W1C */ 376 unsigned long si_aoerr0:1; /* RW, W1C */
380 unsigned long lb_aoerr1 : 1; /* RW, W1C */ 377 unsigned long lb_aoerr1:1; /* RW, W1C */
381 unsigned long gr0_aoerr1 : 1; /* RW, W1C */ 378 unsigned long gr0_aoerr1:1; /* RW, W1C */
382 unsigned long gr1_aoerr1 : 1; /* RW, W1C */ 379 unsigned long gr1_aoerr1:1; /* RW, W1C */
383 unsigned long lh_aoerr1 : 1; /* RW, W1C */ 380 unsigned long lh_aoerr1:1; /* RW, W1C */
384 unsigned long rh_aoerr1 : 1; /* RW, W1C */ 381 unsigned long rh_aoerr1:1; /* RW, W1C */
385 unsigned long xn_aoerr1 : 1; /* RW, W1C */ 382 unsigned long xn_aoerr1:1; /* RW, W1C */
386 unsigned long si_aoerr1 : 1; /* RW, W1C */ 383 unsigned long si_aoerr1:1; /* RW, W1C */
387 unsigned long rh_vpi_int : 1; /* RW, W1C */ 384 unsigned long rh_vpi_int:1; /* RW, W1C */
388 unsigned long system_shutdown_int : 1; /* RW, W1C */ 385 unsigned long system_shutdown_int:1; /* RW, W1C */
389 unsigned long lb_irq_int_0 : 1; /* RW, W1C */ 386 unsigned long lb_irq_int_0:1; /* RW, W1C */
390 unsigned long lb_irq_int_1 : 1; /* RW, W1C */ 387 unsigned long lb_irq_int_1:1; /* RW, W1C */
391 unsigned long lb_irq_int_2 : 1; /* RW, W1C */ 388 unsigned long lb_irq_int_2:1; /* RW, W1C */
392 unsigned long lb_irq_int_3 : 1; /* RW, W1C */ 389 unsigned long lb_irq_int_3:1; /* RW, W1C */
393 unsigned long lb_irq_int_4 : 1; /* RW, W1C */ 390 unsigned long lb_irq_int_4:1; /* RW, W1C */
394 unsigned long lb_irq_int_5 : 1; /* RW, W1C */ 391 unsigned long lb_irq_int_5:1; /* RW, W1C */
395 unsigned long lb_irq_int_6 : 1; /* RW, W1C */ 392 unsigned long lb_irq_int_6:1; /* RW, W1C */
396 unsigned long lb_irq_int_7 : 1; /* RW, W1C */ 393 unsigned long lb_irq_int_7:1; /* RW, W1C */
397 unsigned long lb_irq_int_8 : 1; /* RW, W1C */ 394 unsigned long lb_irq_int_8:1; /* RW, W1C */
398 unsigned long lb_irq_int_9 : 1; /* RW, W1C */ 395 unsigned long lb_irq_int_9:1; /* RW, W1C */
399 unsigned long lb_irq_int_10 : 1; /* RW, W1C */ 396 unsigned long lb_irq_int_10:1; /* RW, W1C */
400 unsigned long lb_irq_int_11 : 1; /* RW, W1C */ 397 unsigned long lb_irq_int_11:1; /* RW, W1C */
401 unsigned long lb_irq_int_12 : 1; /* RW, W1C */ 398 unsigned long lb_irq_int_12:1; /* RW, W1C */
402 unsigned long lb_irq_int_13 : 1; /* RW, W1C */ 399 unsigned long lb_irq_int_13:1; /* RW, W1C */
403 unsigned long lb_irq_int_14 : 1; /* RW, W1C */ 400 unsigned long lb_irq_int_14:1; /* RW, W1C */
404 unsigned long lb_irq_int_15 : 1; /* RW, W1C */ 401 unsigned long lb_irq_int_15:1; /* RW, W1C */
405 unsigned long l1_nmi_int : 1; /* RW, W1C */ 402 unsigned long l1_nmi_int:1; /* RW, W1C */
406 unsigned long stop_clock : 1; /* RW, W1C */ 403 unsigned long stop_clock:1; /* RW, W1C */
407 unsigned long asic_to_l1 : 1; /* RW, W1C */ 404 unsigned long asic_to_l1:1; /* RW, W1C */
408 unsigned long l1_to_asic : 1; /* RW, W1C */ 405 unsigned long l1_to_asic:1; /* RW, W1C */
409 unsigned long ltc_int : 1; /* RW, W1C */ 406 unsigned long ltc_int:1; /* RW, W1C */
410 unsigned long la_seq_trigger : 1; /* RW, W1C */ 407 unsigned long la_seq_trigger:1; /* RW, W1C */
411 unsigned long ipi_int : 1; /* RW, W1C */ 408 unsigned long ipi_int:1; /* RW, W1C */
412 unsigned long extio_int0 : 1; /* RW, W1C */ 409 unsigned long extio_int0:1; /* RW, W1C */
413 unsigned long extio_int1 : 1; /* RW, W1C */ 410 unsigned long extio_int1:1; /* RW, W1C */
414 unsigned long extio_int2 : 1; /* RW, W1C */ 411 unsigned long extio_int2:1; /* RW, W1C */
415 unsigned long extio_int3 : 1; /* RW, W1C */ 412 unsigned long extio_int3:1; /* RW, W1C */
416 unsigned long profile_int : 1; /* RW, W1C */ 413 unsigned long profile_int:1; /* RW, W1C */
417 unsigned long rtc0 : 1; /* RW, W1C */ 414 unsigned long rtc0:1; /* RW, W1C */
418 unsigned long rtc1 : 1; /* RW, W1C */ 415 unsigned long rtc1:1; /* RW, W1C */
419 unsigned long rtc2 : 1; /* RW, W1C */ 416 unsigned long rtc2:1; /* RW, W1C */
420 unsigned long rtc3 : 1; /* RW, W1C */ 417 unsigned long rtc3:1; /* RW, W1C */
421 unsigned long bau_data : 1; /* RW, W1C */ 418 unsigned long bau_data:1; /* RW, W1C */
422 unsigned long power_management_req : 1; /* RW, W1C */ 419 unsigned long power_management_req:1; /* RW, W1C */
423 unsigned long rsvd_57_63 : 7; /* */ 420 unsigned long rsvd_57_63:7;
424 } s1; 421 } s1;
425 struct uv2h_event_occurred0_s { 422 struct uv2h_event_occurred0_s {
426 unsigned long lb_hcerr : 1; /* RW */ 423 unsigned long lb_hcerr:1; /* RW */
427 unsigned long qp_hcerr : 1; /* RW */ 424 unsigned long qp_hcerr:1; /* RW */
428 unsigned long rh_hcerr : 1; /* RW */ 425 unsigned long rh_hcerr:1; /* RW */
429 unsigned long lh0_hcerr : 1; /* RW */ 426 unsigned long lh0_hcerr:1; /* RW */
430 unsigned long lh1_hcerr : 1; /* RW */ 427 unsigned long lh1_hcerr:1; /* RW */
431 unsigned long gr0_hcerr : 1; /* RW */ 428 unsigned long gr0_hcerr:1; /* RW */
432 unsigned long gr1_hcerr : 1; /* RW */ 429 unsigned long gr1_hcerr:1; /* RW */
433 unsigned long ni0_hcerr : 1; /* RW */ 430 unsigned long ni0_hcerr:1; /* RW */
434 unsigned long ni1_hcerr : 1; /* RW */ 431 unsigned long ni1_hcerr:1; /* RW */
435 unsigned long lb_aoerr0 : 1; /* RW */ 432 unsigned long lb_aoerr0:1; /* RW */
436 unsigned long qp_aoerr0 : 1; /* RW */ 433 unsigned long qp_aoerr0:1; /* RW */
437 unsigned long rh_aoerr0 : 1; /* RW */ 434 unsigned long rh_aoerr0:1; /* RW */
438 unsigned long lh0_aoerr0 : 1; /* RW */ 435 unsigned long lh0_aoerr0:1; /* RW */
439 unsigned long lh1_aoerr0 : 1; /* RW */ 436 unsigned long lh1_aoerr0:1; /* RW */
440 unsigned long gr0_aoerr0 : 1; /* RW */ 437 unsigned long gr0_aoerr0:1; /* RW */
441 unsigned long gr1_aoerr0 : 1; /* RW */ 438 unsigned long gr1_aoerr0:1; /* RW */
442 unsigned long xb_aoerr0 : 1; /* RW */ 439 unsigned long xb_aoerr0:1; /* RW */
443 unsigned long rt_aoerr0 : 1; /* RW */ 440 unsigned long rt_aoerr0:1; /* RW */
444 unsigned long ni0_aoerr0 : 1; /* RW */ 441 unsigned long ni0_aoerr0:1; /* RW */
445 unsigned long ni1_aoerr0 : 1; /* RW */ 442 unsigned long ni1_aoerr0:1; /* RW */
446 unsigned long lb_aoerr1 : 1; /* RW */ 443 unsigned long lb_aoerr1:1; /* RW */
447 unsigned long qp_aoerr1 : 1; /* RW */ 444 unsigned long qp_aoerr1:1; /* RW */
448 unsigned long rh_aoerr1 : 1; /* RW */ 445 unsigned long rh_aoerr1:1; /* RW */
449 unsigned long lh0_aoerr1 : 1; /* RW */ 446 unsigned long lh0_aoerr1:1; /* RW */
450 unsigned long lh1_aoerr1 : 1; /* RW */ 447 unsigned long lh1_aoerr1:1; /* RW */
451 unsigned long gr0_aoerr1 : 1; /* RW */ 448 unsigned long gr0_aoerr1:1; /* RW */
452 unsigned long gr1_aoerr1 : 1; /* RW */ 449 unsigned long gr1_aoerr1:1; /* RW */
453 unsigned long xb_aoerr1 : 1; /* RW */ 450 unsigned long xb_aoerr1:1; /* RW */
454 unsigned long rt_aoerr1 : 1; /* RW */ 451 unsigned long rt_aoerr1:1; /* RW */
455 unsigned long ni0_aoerr1 : 1; /* RW */ 452 unsigned long ni0_aoerr1:1; /* RW */
456 unsigned long ni1_aoerr1 : 1; /* RW */ 453 unsigned long ni1_aoerr1:1; /* RW */
457 unsigned long system_shutdown_int : 1; /* RW */ 454 unsigned long system_shutdown_int:1; /* RW */
458 unsigned long lb_irq_int_0 : 1; /* RW */ 455 unsigned long lb_irq_int_0:1; /* RW */
459 unsigned long lb_irq_int_1 : 1; /* RW */ 456 unsigned long lb_irq_int_1:1; /* RW */
460 unsigned long lb_irq_int_2 : 1; /* RW */ 457 unsigned long lb_irq_int_2:1; /* RW */
461 unsigned long lb_irq_int_3 : 1; /* RW */ 458 unsigned long lb_irq_int_3:1; /* RW */
462 unsigned long lb_irq_int_4 : 1; /* RW */ 459 unsigned long lb_irq_int_4:1; /* RW */
463 unsigned long lb_irq_int_5 : 1; /* RW */ 460 unsigned long lb_irq_int_5:1; /* RW */
464 unsigned long lb_irq_int_6 : 1; /* RW */ 461 unsigned long lb_irq_int_6:1; /* RW */
465 unsigned long lb_irq_int_7 : 1; /* RW */ 462 unsigned long lb_irq_int_7:1; /* RW */
466 unsigned long lb_irq_int_8 : 1; /* RW */ 463 unsigned long lb_irq_int_8:1; /* RW */
467 unsigned long lb_irq_int_9 : 1; /* RW */ 464 unsigned long lb_irq_int_9:1; /* RW */
468 unsigned long lb_irq_int_10 : 1; /* RW */ 465 unsigned long lb_irq_int_10:1; /* RW */
469 unsigned long lb_irq_int_11 : 1; /* RW */ 466 unsigned long lb_irq_int_11:1; /* RW */
470 unsigned long lb_irq_int_12 : 1; /* RW */ 467 unsigned long lb_irq_int_12:1; /* RW */
471 unsigned long lb_irq_int_13 : 1; /* RW */ 468 unsigned long lb_irq_int_13:1; /* RW */
472 unsigned long lb_irq_int_14 : 1; /* RW */ 469 unsigned long lb_irq_int_14:1; /* RW */
473 unsigned long lb_irq_int_15 : 1; /* RW */ 470 unsigned long lb_irq_int_15:1; /* RW */
474 unsigned long l1_nmi_int : 1; /* RW */ 471 unsigned long l1_nmi_int:1; /* RW */
475 unsigned long stop_clock : 1; /* RW */ 472 unsigned long stop_clock:1; /* RW */
476 unsigned long asic_to_l1 : 1; /* RW */ 473 unsigned long asic_to_l1:1; /* RW */
477 unsigned long l1_to_asic : 1; /* RW */ 474 unsigned long l1_to_asic:1; /* RW */
478 unsigned long la_seq_trigger : 1; /* RW */ 475 unsigned long la_seq_trigger:1; /* RW */
479 unsigned long ipi_int : 1; /* RW */ 476 unsigned long ipi_int:1; /* RW */
480 unsigned long extio_int0 : 1; /* RW */ 477 unsigned long extio_int0:1; /* RW */
481 unsigned long extio_int1 : 1; /* RW */ 478 unsigned long extio_int1:1; /* RW */
482 unsigned long extio_int2 : 1; /* RW */ 479 unsigned long extio_int2:1; /* RW */
483 unsigned long extio_int3 : 1; /* RW */ 480 unsigned long extio_int3:1; /* RW */
484 unsigned long profile_int : 1; /* RW */ 481 unsigned long profile_int:1; /* RW */
485 unsigned long rsvd_59_63 : 5; /* */ 482 unsigned long rsvd_59_63:5;
486 } s2; 483 } s2;
487}; 484};
488 485
489/* ========================================================================= */ 486/* ========================================================================= */
490/* UVH_EVENT_OCCURRED0_ALIAS */ 487/* UVH_EVENT_OCCURRED0_ALIAS */
491/* ========================================================================= */ 488/* ========================================================================= */
492#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL 489#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
493#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0 490#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
494 491
495/* ========================================================================= */ 492/* ========================================================================= */
496/* UVH_GR0_TLB_INT0_CONFIG */ 493/* UVH_GR0_TLB_INT0_CONFIG */
497/* ========================================================================= */ 494/* ========================================================================= */
498#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL 495#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
499 496
500#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 497#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
501#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 498#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
502#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 499#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
503#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 500#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
504#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 501#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13
505#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 502#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15
506#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 503#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16
507#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 504#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
508#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13 505#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
509#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 506#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
510#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15 507#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
511#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 508#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
512#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16 509#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
513#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 510#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
514#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 511#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
515#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 512#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
516 513
517union uvh_gr0_tlb_int0_config_u { 514union uvh_gr0_tlb_int0_config_u {
518 unsigned long v; 515 unsigned long v;
519 struct uvh_gr0_tlb_int0_config_s { 516 struct uvh_gr0_tlb_int0_config_s {
520 unsigned long vector_ : 8; /* RW */ 517 unsigned long vector_:8; /* RW */
521 unsigned long dm : 3; /* RW */ 518 unsigned long dm:3; /* RW */
522 unsigned long destmode : 1; /* RW */ 519 unsigned long destmode:1; /* RW */
523 unsigned long status : 1; /* RO */ 520 unsigned long status:1; /* RO */
524 unsigned long p : 1; /* RO */ 521 unsigned long p:1; /* RO */
525 unsigned long rsvd_14 : 1; /* */ 522 unsigned long rsvd_14:1;
526 unsigned long t : 1; /* RO */ 523 unsigned long t:1; /* RO */
527 unsigned long m : 1; /* RW */ 524 unsigned long m:1; /* RW */
528 unsigned long rsvd_17_31: 15; /* */ 525 unsigned long rsvd_17_31:15;
529 unsigned long apic_id : 32; /* RW */ 526 unsigned long apic_id:32; /* RW */
530 } s; 527 } s;
531}; 528};
532 529
533/* ========================================================================= */ 530/* ========================================================================= */
534/* UVH_GR0_TLB_INT1_CONFIG */ 531/* UVH_GR0_TLB_INT1_CONFIG */
535/* ========================================================================= */ 532/* ========================================================================= */
536#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL 533#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
537 534
538#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 535#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
539#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 536#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
540#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 537#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
541#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 538#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
542#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 539#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13
543#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 540#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15
544#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 541#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16
545#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 542#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
546#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13 543#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
547#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 544#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
548#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15 545#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
549#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 546#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
550#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16 547#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
551#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 548#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
552#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 549#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
553#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 550#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
554 551
555union uvh_gr0_tlb_int1_config_u { 552union uvh_gr0_tlb_int1_config_u {
556 unsigned long v; 553 unsigned long v;
557 struct uvh_gr0_tlb_int1_config_s { 554 struct uvh_gr0_tlb_int1_config_s {
558 unsigned long vector_ : 8; /* RW */ 555 unsigned long vector_:8; /* RW */
559 unsigned long dm : 3; /* RW */ 556 unsigned long dm:3; /* RW */
560 unsigned long destmode : 1; /* RW */ 557 unsigned long destmode:1; /* RW */
561 unsigned long status : 1; /* RO */ 558 unsigned long status:1; /* RO */
562 unsigned long p : 1; /* RO */ 559 unsigned long p:1; /* RO */
563 unsigned long rsvd_14 : 1; /* */ 560 unsigned long rsvd_14:1;
564 unsigned long t : 1; /* RO */ 561 unsigned long t:1; /* RO */
565 unsigned long m : 1; /* RW */ 562 unsigned long m:1; /* RW */
566 unsigned long rsvd_17_31: 15; /* */ 563 unsigned long rsvd_17_31:15;
567 unsigned long apic_id : 32; /* RW */ 564 unsigned long apic_id:32; /* RW */
568 } s; 565 } s;
566};
567
568/* ========================================================================= */
569/* UVH_GR0_TLB_MMR_CONTROL */
570/* ========================================================================= */
571#define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL
572#define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL
573#define UVH_GR0_TLB_MMR_CONTROL (is_uv1_hub() ? \
574 UV1H_GR0_TLB_MMR_CONTROL : \
575 UV2H_GR0_TLB_MMR_CONTROL)
576
577#define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0
578#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
579#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
580#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
581#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
582#define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31
583#define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
584#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
585#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
586#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
587#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
588#define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
589
590#define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0
591#define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
592#define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
593#define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
594#define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
595#define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31
596#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48
597#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52
598#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
599#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56
600#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60
601#define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
602#define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
603#define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
604#define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
605#define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
606#define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
607#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL
608#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL
609#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
610#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL
611#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL
612
613#define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0
614#define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
615#define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
616#define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
617#define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
618#define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31
619#define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32
620#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48
621#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52
622#define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
623#define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
624#define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
625#define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
626#define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
627#define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
628#define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL
629#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL
630#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL
631
632union uvh_gr0_tlb_mmr_control_u {
633 unsigned long v;
634 struct uvh_gr0_tlb_mmr_control_s {
635 unsigned long index:12; /* RW */
636 unsigned long mem_sel:2; /* RW */
637 unsigned long rsvd_14_15:2;
638 unsigned long auto_valid_en:1; /* RW */
639 unsigned long rsvd_17_19:3;
640 unsigned long mmr_hash_index_en:1; /* RW */
641 unsigned long rsvd_21_29:9;
642 unsigned long mmr_write:1; /* WP */
643 unsigned long mmr_read:1; /* WP */
644 unsigned long rsvd_32_63:32;
645 } s;
646 struct uv1h_gr0_tlb_mmr_control_s {
647 unsigned long index:12; /* RW */
648 unsigned long mem_sel:2; /* RW */
649 unsigned long rsvd_14_15:2;
650 unsigned long auto_valid_en:1; /* RW */
651 unsigned long rsvd_17_19:3;
652 unsigned long mmr_hash_index_en:1; /* RW */
653 unsigned long rsvd_21_29:9;
654 unsigned long mmr_write:1; /* WP */
655 unsigned long mmr_read:1; /* WP */
656 unsigned long rsvd_32_47:16;
657 unsigned long mmr_inj_con:1; /* RW */
658 unsigned long rsvd_49_51:3;
659 unsigned long mmr_inj_tlbram:1; /* RW */
660 unsigned long rsvd_53:1;
661 unsigned long mmr_inj_tlbpgsize:1; /* RW */
662 unsigned long rsvd_55:1;
663 unsigned long mmr_inj_tlbrreg:1; /* RW */
664 unsigned long rsvd_57_59:3;
665 unsigned long mmr_inj_tlblruv:1; /* RW */
666 unsigned long rsvd_61_63:3;
667 } s1;
668 struct uv2h_gr0_tlb_mmr_control_s {
669 unsigned long index:12; /* RW */
670 unsigned long mem_sel:2; /* RW */
671 unsigned long rsvd_14_15:2;
672 unsigned long auto_valid_en:1; /* RW */
673 unsigned long rsvd_17_19:3;
674 unsigned long mmr_hash_index_en:1; /* RW */
675 unsigned long rsvd_21_29:9;
676 unsigned long mmr_write:1; /* WP */
677 unsigned long mmr_read:1; /* WP */
678 unsigned long mmr_op_done:1; /* RW */
679 unsigned long rsvd_33_47:15;
680 unsigned long mmr_inj_con:1; /* RW */
681 unsigned long rsvd_49_51:3;
682 unsigned long mmr_inj_tlbram:1; /* RW */
683 unsigned long rsvd_53_63:11;
684 } s2;
685};
686
687/* ========================================================================= */
688/* UVH_GR0_TLB_MMR_READ_DATA_HI */
689/* ========================================================================= */
690#define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL
691#define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
692#define UVH_GR0_TLB_MMR_READ_DATA_HI (is_uv1_hub() ? \
693 UV1H_GR0_TLB_MMR_READ_DATA_HI : \
694 UV2H_GR0_TLB_MMR_READ_DATA_HI)
695
696#define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
697#define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
698#define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43
699#define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44
700#define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL
701#define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL
702#define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL
703#define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL
704
705union uvh_gr0_tlb_mmr_read_data_hi_u {
706 unsigned long v;
707 struct uvh_gr0_tlb_mmr_read_data_hi_s {
708 unsigned long pfn:41; /* RO */
709 unsigned long gaa:2; /* RO */
710 unsigned long dirty:1; /* RO */
711 unsigned long larger:1; /* RO */
712 unsigned long rsvd_45_63:19;
713 } s;
714};
715
716/* ========================================================================= */
717/* UVH_GR0_TLB_MMR_READ_DATA_LO */
718/* ========================================================================= */
719#define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL
720#define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
721#define UVH_GR0_TLB_MMR_READ_DATA_LO (is_uv1_hub() ? \
722 UV1H_GR0_TLB_MMR_READ_DATA_LO : \
723 UV2H_GR0_TLB_MMR_READ_DATA_LO)
724
725#define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0
726#define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39
727#define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63
728#define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL
729#define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL
730#define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL
731
732union uvh_gr0_tlb_mmr_read_data_lo_u {
733 unsigned long v;
734 struct uvh_gr0_tlb_mmr_read_data_lo_s {
735 unsigned long vpn:39; /* RO */
736 unsigned long asid:24; /* RO */
737 unsigned long valid:1; /* RO */
738 } s;
569}; 739};
570 740
571/* ========================================================================= */ 741/* ========================================================================= */
572/* UVH_GR1_TLB_INT0_CONFIG */ 742/* UVH_GR1_TLB_INT0_CONFIG */
573/* ========================================================================= */ 743/* ========================================================================= */
574#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL 744#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
575 745
576#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 746#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
577#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 747#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
578#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 748#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
579#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 749#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
580#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 750#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13
581#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 751#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15
582#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 752#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16
583#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 753#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
584#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13 754#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
585#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 755#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
586#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15 756#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
587#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 757#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
588#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16 758#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
589#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 759#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
590#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 760#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
591#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 761#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
592 762
593union uvh_gr1_tlb_int0_config_u { 763union uvh_gr1_tlb_int0_config_u {
594 unsigned long v; 764 unsigned long v;
595 struct uvh_gr1_tlb_int0_config_s { 765 struct uvh_gr1_tlb_int0_config_s {
596 unsigned long vector_ : 8; /* RW */ 766 unsigned long vector_:8; /* RW */
597 unsigned long dm : 3; /* RW */ 767 unsigned long dm:3; /* RW */
598 unsigned long destmode : 1; /* RW */ 768 unsigned long destmode:1; /* RW */
599 unsigned long status : 1; /* RO */ 769 unsigned long status:1; /* RO */
600 unsigned long p : 1; /* RO */ 770 unsigned long p:1; /* RO */
601 unsigned long rsvd_14 : 1; /* */ 771 unsigned long rsvd_14:1;
602 unsigned long t : 1; /* RO */ 772 unsigned long t:1; /* RO */
603 unsigned long m : 1; /* RW */ 773 unsigned long m:1; /* RW */
604 unsigned long rsvd_17_31: 15; /* */ 774 unsigned long rsvd_17_31:15;
605 unsigned long apic_id : 32; /* RW */ 775 unsigned long apic_id:32; /* RW */
606 } s; 776 } s;
607}; 777};
608 778
609/* ========================================================================= */ 779/* ========================================================================= */
610/* UVH_GR1_TLB_INT1_CONFIG */ 780/* UVH_GR1_TLB_INT1_CONFIG */
611/* ========================================================================= */ 781/* ========================================================================= */
612#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL 782#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
613 783
614#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 784#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
615#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 785#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
616#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 786#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
617#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 787#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
618#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 788#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13
619#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 789#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15
620#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 790#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16
621#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 791#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
622#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13 792#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
623#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 793#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
624#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15 794#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
625#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 795#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
626#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16 796#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
627#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 797#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
628#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 798#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
629#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 799#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
630 800
631union uvh_gr1_tlb_int1_config_u { 801union uvh_gr1_tlb_int1_config_u {
632 unsigned long v; 802 unsigned long v;
633 struct uvh_gr1_tlb_int1_config_s { 803 struct uvh_gr1_tlb_int1_config_s {
634 unsigned long vector_ : 8; /* RW */ 804 unsigned long vector_:8; /* RW */
635 unsigned long dm : 3; /* RW */ 805 unsigned long dm:3; /* RW */
636 unsigned long destmode : 1; /* RW */ 806 unsigned long destmode:1; /* RW */
637 unsigned long status : 1; /* RO */ 807 unsigned long status:1; /* RO */
638 unsigned long p : 1; /* RO */ 808 unsigned long p:1; /* RO */
639 unsigned long rsvd_14 : 1; /* */ 809 unsigned long rsvd_14:1;
640 unsigned long t : 1; /* RO */ 810 unsigned long t:1; /* RO */
641 unsigned long m : 1; /* RW */ 811 unsigned long m:1; /* RW */
642 unsigned long rsvd_17_31: 15; /* */ 812 unsigned long rsvd_17_31:15;
643 unsigned long apic_id : 32; /* RW */ 813 unsigned long apic_id:32; /* RW */
644 } s; 814 } s;
815};
816
817/* ========================================================================= */
818/* UVH_GR1_TLB_MMR_CONTROL */
819/* ========================================================================= */
820#define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL
821#define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL
822#define UVH_GR1_TLB_MMR_CONTROL (is_uv1_hub() ? \
823 UV1H_GR1_TLB_MMR_CONTROL : \
824 UV2H_GR1_TLB_MMR_CONTROL)
825
826#define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0
827#define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
828#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
829#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
830#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
831#define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31
832#define UVH_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
833#define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
834#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
835#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
836#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
837#define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
838
839#define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0
840#define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
841#define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
842#define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
843#define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
844#define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31
845#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48
846#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52
847#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
848#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56
849#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60
850#define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
851#define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
852#define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
853#define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
854#define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
855#define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
856#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL
857#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL
858#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
859#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL
860#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL
861
862#define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0
863#define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
864#define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
865#define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
866#define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
867#define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31
868#define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32
869#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48
870#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52
871#define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
872#define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
873#define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
874#define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
875#define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
876#define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
877#define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL
878#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL
879#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL
880
881union uvh_gr1_tlb_mmr_control_u {
882 unsigned long v;
883 struct uvh_gr1_tlb_mmr_control_s {
884 unsigned long index:12; /* RW */
885 unsigned long mem_sel:2; /* RW */
886 unsigned long rsvd_14_15:2;
887 unsigned long auto_valid_en:1; /* RW */
888 unsigned long rsvd_17_19:3;
889 unsigned long mmr_hash_index_en:1; /* RW */
890 unsigned long rsvd_21_29:9;
891 unsigned long mmr_write:1; /* WP */
892 unsigned long mmr_read:1; /* WP */
893 unsigned long rsvd_32_63:32;
894 } s;
895 struct uv1h_gr1_tlb_mmr_control_s {
896 unsigned long index:12; /* RW */
897 unsigned long mem_sel:2; /* RW */
898 unsigned long rsvd_14_15:2;
899 unsigned long auto_valid_en:1; /* RW */
900 unsigned long rsvd_17_19:3;
901 unsigned long mmr_hash_index_en:1; /* RW */
902 unsigned long rsvd_21_29:9;
903 unsigned long mmr_write:1; /* WP */
904 unsigned long mmr_read:1; /* WP */
905 unsigned long rsvd_32_47:16;
906 unsigned long mmr_inj_con:1; /* RW */
907 unsigned long rsvd_49_51:3;
908 unsigned long mmr_inj_tlbram:1; /* RW */
909 unsigned long rsvd_53:1;
910 unsigned long mmr_inj_tlbpgsize:1; /* RW */
911 unsigned long rsvd_55:1;
912 unsigned long mmr_inj_tlbrreg:1; /* RW */
913 unsigned long rsvd_57_59:3;
914 unsigned long mmr_inj_tlblruv:1; /* RW */
915 unsigned long rsvd_61_63:3;
916 } s1;
917 struct uv2h_gr1_tlb_mmr_control_s {
918 unsigned long index:12; /* RW */
919 unsigned long mem_sel:2; /* RW */
920 unsigned long rsvd_14_15:2;
921 unsigned long auto_valid_en:1; /* RW */
922 unsigned long rsvd_17_19:3;
923 unsigned long mmr_hash_index_en:1; /* RW */
924 unsigned long rsvd_21_29:9;
925 unsigned long mmr_write:1; /* WP */
926 unsigned long mmr_read:1; /* WP */
927 unsigned long mmr_op_done:1; /* RW */
928 unsigned long rsvd_33_47:15;
929 unsigned long mmr_inj_con:1; /* RW */
930 unsigned long rsvd_49_51:3;
931 unsigned long mmr_inj_tlbram:1; /* RW */
932 unsigned long rsvd_53_63:11;
933 } s2;
934};
935
936/* ========================================================================= */
937/* UVH_GR1_TLB_MMR_READ_DATA_HI */
938/* ========================================================================= */
939#define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL
940#define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
941#define UVH_GR1_TLB_MMR_READ_DATA_HI (is_uv1_hub() ? \
942 UV1H_GR1_TLB_MMR_READ_DATA_HI : \
943 UV2H_GR1_TLB_MMR_READ_DATA_HI)
944
945#define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
946#define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
947#define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43
948#define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44
949#define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL
950#define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL
951#define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL
952#define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL
953
954union uvh_gr1_tlb_mmr_read_data_hi_u {
955 unsigned long v;
956 struct uvh_gr1_tlb_mmr_read_data_hi_s {
957 unsigned long pfn:41; /* RO */
958 unsigned long gaa:2; /* RO */
959 unsigned long dirty:1; /* RO */
960 unsigned long larger:1; /* RO */
961 unsigned long rsvd_45_63:19;
962 } s;
963};
964
965/* ========================================================================= */
966/* UVH_GR1_TLB_MMR_READ_DATA_LO */
967/* ========================================================================= */
968#define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL
969#define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
970#define UVH_GR1_TLB_MMR_READ_DATA_LO (is_uv1_hub() ? \
971 UV1H_GR1_TLB_MMR_READ_DATA_LO : \
972 UV2H_GR1_TLB_MMR_READ_DATA_LO)
973
974#define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0
975#define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39
976#define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63
977#define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL
978#define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL
979#define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL
980
981union uvh_gr1_tlb_mmr_read_data_lo_u {
982 unsigned long v;
983 struct uvh_gr1_tlb_mmr_read_data_lo_s {
984 unsigned long vpn:39; /* RO */
985 unsigned long asid:24; /* RO */
986 unsigned long valid:1; /* RO */
987 } s;
645}; 988};
646 989
647/* ========================================================================= */ 990/* ========================================================================= */
648/* UVH_INT_CMPB */ 991/* UVH_INT_CMPB */
649/* ========================================================================= */ 992/* ========================================================================= */
650#define UVH_INT_CMPB 0x22080UL 993#define UVH_INT_CMPB 0x22080UL
651 994
652#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 995#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
653#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL 996#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
654 997
655union uvh_int_cmpb_u { 998union uvh_int_cmpb_u {
656 unsigned long v; 999 unsigned long v;
657 struct uvh_int_cmpb_s { 1000 struct uvh_int_cmpb_s {
658 unsigned long real_time_cmpb : 56; /* RW */ 1001 unsigned long real_time_cmpb:56; /* RW */
659 unsigned long rsvd_56_63 : 8; /* */ 1002 unsigned long rsvd_56_63:8;
660 } s; 1003 } s;
661}; 1004};
662 1005
663/* ========================================================================= */ 1006/* ========================================================================= */
664/* UVH_INT_CMPC */ 1007/* UVH_INT_CMPC */
665/* ========================================================================= */ 1008/* ========================================================================= */
666#define UVH_INT_CMPC 0x22100UL 1009#define UVH_INT_CMPC 0x22100UL
667 1010
668#define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0 1011#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
669#define UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT 0 1012#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL
670#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT (is_uv1_hub() ? \
671 UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT : \
672 UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT)
673#define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL
674#define UV2H_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL
675#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK (is_uv1_hub() ? \
676 UV1H_INT_CMPC_REAL_TIME_CMPC_MASK : \
677 UV2H_INT_CMPC_REAL_TIME_CMPC_MASK)
678 1013
679union uvh_int_cmpc_u { 1014union uvh_int_cmpc_u {
680 unsigned long v; 1015 unsigned long v;
681 struct uvh_int_cmpc_s { 1016 struct uvh_int_cmpc_s {
682 unsigned long real_time_cmpc : 56; /* RW */ 1017 unsigned long real_time_cmpc:56; /* RW */
683 unsigned long rsvd_56_63 : 8; /* */ 1018 unsigned long rsvd_56_63:8;
684 } s; 1019 } s;
685}; 1020};
686 1021
687/* ========================================================================= */ 1022/* ========================================================================= */
688/* UVH_INT_CMPD */ 1023/* UVH_INT_CMPD */
689/* ========================================================================= */ 1024/* ========================================================================= */
690#define UVH_INT_CMPD 0x22180UL 1025#define UVH_INT_CMPD 0x22180UL
691 1026
692#define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0 1027#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
693#define UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT 0 1028#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL
694#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT (is_uv1_hub() ? \
695 UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT : \
696 UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT)
697#define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL
698#define UV2H_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL
699#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK (is_uv1_hub() ? \
700 UV1H_INT_CMPD_REAL_TIME_CMPD_MASK : \
701 UV2H_INT_CMPD_REAL_TIME_CMPD_MASK)
702 1029
703union uvh_int_cmpd_u { 1030union uvh_int_cmpd_u {
704 unsigned long v; 1031 unsigned long v;
705 struct uvh_int_cmpd_s { 1032 struct uvh_int_cmpd_s {
706 unsigned long real_time_cmpd : 56; /* RW */ 1033 unsigned long real_time_cmpd:56; /* RW */
707 unsigned long rsvd_56_63 : 8; /* */ 1034 unsigned long rsvd_56_63:8;
708 } s; 1035 } s;
709}; 1036};
710 1037
711/* ========================================================================= */ 1038/* ========================================================================= */
712/* UVH_IPI_INT */ 1039/* UVH_IPI_INT */
713/* ========================================================================= */ 1040/* ========================================================================= */
714#define UVH_IPI_INT 0x60500UL 1041#define UVH_IPI_INT 0x60500UL
715#define UVH_IPI_INT_32 0x348 1042#define UVH_IPI_INT_32 0x348
716 1043
717#define UVH_IPI_INT_VECTOR_SHFT 0 1044#define UVH_IPI_INT_VECTOR_SHFT 0
718#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL 1045#define UVH_IPI_INT_DELIVERY_MODE_SHFT 8
719#define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 1046#define UVH_IPI_INT_DESTMODE_SHFT 11
720#define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL 1047#define UVH_IPI_INT_APIC_ID_SHFT 16
721#define UVH_IPI_INT_DESTMODE_SHFT 11 1048#define UVH_IPI_INT_SEND_SHFT 63
722#define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL 1049#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
723#define UVH_IPI_INT_APIC_ID_SHFT 16 1050#define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
724#define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL 1051#define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
725#define UVH_IPI_INT_SEND_SHFT 63 1052#define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
726#define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL 1053#define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
727 1054
728union uvh_ipi_int_u { 1055union uvh_ipi_int_u {
729 unsigned long v; 1056 unsigned long v;
730 struct uvh_ipi_int_s { 1057 struct uvh_ipi_int_s {
731 unsigned long vector_ : 8; /* RW */ 1058 unsigned long vector_:8; /* RW */
732 unsigned long delivery_mode : 3; /* RW */ 1059 unsigned long delivery_mode:3; /* RW */
733 unsigned long destmode : 1; /* RW */ 1060 unsigned long destmode:1; /* RW */
734 unsigned long rsvd_12_15 : 4; /* */ 1061 unsigned long rsvd_12_15:4;
735 unsigned long apic_id : 32; /* RW */ 1062 unsigned long apic_id:32; /* RW */
736 unsigned long rsvd_48_62 : 15; /* */ 1063 unsigned long rsvd_48_62:15;
737 unsigned long send : 1; /* WP */ 1064 unsigned long send:1; /* WP */
738 } s; 1065 } s;
739}; 1066};
740 1067
741/* ========================================================================= */ 1068/* ========================================================================= */
742/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ 1069/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */
743/* ========================================================================= */ 1070/* ========================================================================= */
744#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1071#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
745#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0 1072#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
746 1073
747#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1074#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
748#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
749#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1075#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1076#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
750#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1077#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
751 1078
752union uvh_lb_bau_intd_payload_queue_first_u { 1079union uvh_lb_bau_intd_payload_queue_first_u {
753 unsigned long v; 1080 unsigned long v;
754 struct uvh_lb_bau_intd_payload_queue_first_s { 1081 struct uvh_lb_bau_intd_payload_queue_first_s {
755 unsigned long rsvd_0_3: 4; /* */ 1082 unsigned long rsvd_0_3:4;
756 unsigned long address : 39; /* RW */ 1083 unsigned long address:39; /* RW */
757 unsigned long rsvd_43_48: 6; /* */ 1084 unsigned long rsvd_43_48:6;
758 unsigned long node_id : 14; /* RW */ 1085 unsigned long node_id:14; /* RW */
759 unsigned long rsvd_63 : 1; /* */ 1086 unsigned long rsvd_63:1;
760 } s; 1087 } s;
761}; 1088};
762 1089
763/* ========================================================================= */ 1090/* ========================================================================= */
764/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ 1091/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */
765/* ========================================================================= */ 1092/* ========================================================================= */
766#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1093#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
767#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8 1094#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
768 1095
769#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1096#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
770#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1097#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
771 1098
772union uvh_lb_bau_intd_payload_queue_last_u { 1099union uvh_lb_bau_intd_payload_queue_last_u {
773 unsigned long v; 1100 unsigned long v;
774 struct uvh_lb_bau_intd_payload_queue_last_s { 1101 struct uvh_lb_bau_intd_payload_queue_last_s {
775 unsigned long rsvd_0_3: 4; /* */ 1102 unsigned long rsvd_0_3:4;
776 unsigned long address : 39; /* RW */ 1103 unsigned long address:39; /* RW */
777 unsigned long rsvd_43_63: 21; /* */ 1104 unsigned long rsvd_43_63:21;
778 } s; 1105 } s;
779}; 1106};
780 1107
781/* ========================================================================= */ 1108/* ========================================================================= */
782/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ 1109/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */
783/* ========================================================================= */ 1110/* ========================================================================= */
784#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1111#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
785#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0 1112#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
786 1113
787#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1114#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
788#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1115#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
789 1116
790union uvh_lb_bau_intd_payload_queue_tail_u { 1117union uvh_lb_bau_intd_payload_queue_tail_u {
791 unsigned long v; 1118 unsigned long v;
792 struct uvh_lb_bau_intd_payload_queue_tail_s { 1119 struct uvh_lb_bau_intd_payload_queue_tail_s {
793 unsigned long rsvd_0_3: 4; /* */ 1120 unsigned long rsvd_0_3:4;
794 unsigned long address : 39; /* RW */ 1121 unsigned long address:39; /* RW */
795 unsigned long rsvd_43_63: 21; /* */ 1122 unsigned long rsvd_43_63:21;
796 } s; 1123 } s;
797}; 1124};
798 1125
799/* ========================================================================= */ 1126/* ========================================================================= */
800/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ 1127/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */
801/* ========================================================================= */ 1128/* ========================================================================= */
802#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 1129#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
803#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68 1130#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
804 1131
805#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 1132#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
806#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
807#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 1133#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
808#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
809#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 1134#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
810#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
811#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 1135#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
812#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
813#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 1136#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
814#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
815#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 1137#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
816#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
817#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 1138#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
818#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
819#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 1139#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
820#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
821#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 1140#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
822#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
823#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 1141#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
824#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
825#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 1142#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
826#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
827#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 1143#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
828#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
829#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 1144#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
830#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
831#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 1145#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
832#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
833#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 1146#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
834#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
835#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 1147#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
1148#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
1149#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
1150#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
1151#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
1152#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
1153#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
1154#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
1155#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
1156#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
1157#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
1158#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
1159#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
1160#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
1161#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
1162#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
836#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 1163#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
837 1164
838union uvh_lb_bau_intd_software_acknowledge_u { 1165union uvh_lb_bau_intd_software_acknowledge_u {
839 unsigned long v; 1166 unsigned long v;
840 struct uvh_lb_bau_intd_software_acknowledge_s { 1167 struct uvh_lb_bau_intd_software_acknowledge_s {
841 unsigned long pending_0 : 1; /* RW, W1C */ 1168 unsigned long pending_0:1; /* RW, W1C */
842 unsigned long pending_1 : 1; /* RW, W1C */ 1169 unsigned long pending_1:1; /* RW, W1C */
843 unsigned long pending_2 : 1; /* RW, W1C */ 1170 unsigned long pending_2:1; /* RW, W1C */
844 unsigned long pending_3 : 1; /* RW, W1C */ 1171 unsigned long pending_3:1; /* RW, W1C */
845 unsigned long pending_4 : 1; /* RW, W1C */ 1172 unsigned long pending_4:1; /* RW, W1C */
846 unsigned long pending_5 : 1; /* RW, W1C */ 1173 unsigned long pending_5:1; /* RW, W1C */
847 unsigned long pending_6 : 1; /* RW, W1C */ 1174 unsigned long pending_6:1; /* RW, W1C */
848 unsigned long pending_7 : 1; /* RW, W1C */ 1175 unsigned long pending_7:1; /* RW, W1C */
849 unsigned long timeout_0 : 1; /* RW, W1C */ 1176 unsigned long timeout_0:1; /* RW, W1C */
850 unsigned long timeout_1 : 1; /* RW, W1C */ 1177 unsigned long timeout_1:1; /* RW, W1C */
851 unsigned long timeout_2 : 1; /* RW, W1C */ 1178 unsigned long timeout_2:1; /* RW, W1C */
852 unsigned long timeout_3 : 1; /* RW, W1C */ 1179 unsigned long timeout_3:1; /* RW, W1C */
853 unsigned long timeout_4 : 1; /* RW, W1C */ 1180 unsigned long timeout_4:1; /* RW, W1C */
854 unsigned long timeout_5 : 1; /* RW, W1C */ 1181 unsigned long timeout_5:1; /* RW, W1C */
855 unsigned long timeout_6 : 1; /* RW, W1C */ 1182 unsigned long timeout_6:1; /* RW, W1C */
856 unsigned long timeout_7 : 1; /* RW, W1C */ 1183 unsigned long timeout_7:1; /* RW, W1C */
857 unsigned long rsvd_16_63: 48; /* */ 1184 unsigned long rsvd_16_63:48;
858 } s; 1185 } s;
859}; 1186};
860 1187
861/* ========================================================================= */ 1188/* ========================================================================= */
862/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ 1189/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */
863/* ========================================================================= */ 1190/* ========================================================================= */
864#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL 1191#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
865#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70 1192#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
866 1193
867/* ========================================================================= */ 1194/* ========================================================================= */
868/* UVH_LB_BAU_MISC_CONTROL */ 1195/* UVH_LB_BAU_MISC_CONTROL */
869/* ========================================================================= */ 1196/* ========================================================================= */
870#define UVH_LB_BAU_MISC_CONTROL 0x320170UL 1197#define UVH_LB_BAU_MISC_CONTROL 0x320170UL
871#define UVH_LB_BAU_MISC_CONTROL_32 0xa10 1198#define UVH_LB_BAU_MISC_CONTROL_32 0xa10
872 1199
873#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1200#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
874#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1201#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
875#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1202#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
876#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1203#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
877#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
878#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
879#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
880#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
881#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1204#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
882#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
883#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1205#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
884#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
885#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 1206#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
886#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
887#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 1207#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
888#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
889#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1208#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
890#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
891#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1209#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
892#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
893#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1210#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
894#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
895#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1211#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
896#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
897#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1212#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
898#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
899#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1213#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
900#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
901#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1214#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
1215#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
1216#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
1217#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
1218#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
1219#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1220#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1221#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1222#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1223#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1224#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1225#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1226#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1227#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1228#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
902#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1229#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
903 1230
904#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1231#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
905#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1232#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
906#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1233#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
907#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1234#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
908#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
909#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
910#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
911#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
912#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1235#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
913#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
914#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1236#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
915#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
916#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 1237#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
917#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
918#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 1238#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
919#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
920#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1239#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
921#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
922#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1240#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
923#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
924#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1241#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
925#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
926#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1242#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
927#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
928#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1243#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
929#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
930#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1244#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
931#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
932#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1245#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
1246#define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
1247#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
1248#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
1249#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
1250#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
1251#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1252#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1253#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1254#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1255#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1256#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1257#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1258#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1259#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1260#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
933#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1261#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
934#define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1262#define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
935#define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 1263
936 1264#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
937#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1265#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
938#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1266#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
939#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1267#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
940#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
941#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
942#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
943#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
944#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
945#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1268#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
946#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
947#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1269#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
948#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
949#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 1270#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
950#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
951#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 1271#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
952#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
953#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1272#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
954#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
955#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1273#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
956#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
957#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1274#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
958#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
959#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1275#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
960#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
961#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1276#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
962#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
963#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1277#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
964#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
965#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1278#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
966#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
967#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 1279#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
968#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 1280#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30
969#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30
970#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL
971#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 1281#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
972#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
973#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 1282#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
974#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
975#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 1283#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
976#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
977#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 1284#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
978#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
979#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 1285#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
1286#define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
1287#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
1288#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
1289#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
1290#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
1291#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1292#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1293#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1294#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1295#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1296#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1297#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1298#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1299#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1300#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
1301#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
1302#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
1303#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL
1304#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
1305#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
1306#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
1307#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
980#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 1308#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
981#define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1309#define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
982#define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
983 1310
984union uvh_lb_bau_misc_control_u { 1311union uvh_lb_bau_misc_control_u {
985 unsigned long v; 1312 unsigned long v;
986 struct uvh_lb_bau_misc_control_s { 1313 struct uvh_lb_bau_misc_control_s {
987 unsigned long rejection_delay : 8; /* RW */ 1314 unsigned long rejection_delay:8; /* RW */
988 unsigned long apic_mode : 1; /* RW */ 1315 unsigned long apic_mode:1; /* RW */
989 unsigned long force_broadcast : 1; /* RW */ 1316 unsigned long force_broadcast:1; /* RW */
990 unsigned long force_lock_nop : 1; /* RW */ 1317 unsigned long force_lock_nop:1; /* RW */
991 unsigned long qpi_agent_presence_vector : 3; /* RW */ 1318 unsigned long qpi_agent_presence_vector:3; /* RW */
992 unsigned long descriptor_fetch_mode : 1; /* RW */ 1319 unsigned long descriptor_fetch_mode:1; /* RW */
993 unsigned long enable_intd_soft_ack_mode : 1; /* RW */ 1320 unsigned long enable_intd_soft_ack_mode:1; /* RW */
994 unsigned long intd_soft_ack_timeout_period : 4; /* RW */ 1321 unsigned long intd_soft_ack_timeout_period:4; /* RW */
995 unsigned long enable_dual_mapping_mode : 1; /* RW */ 1322 unsigned long enable_dual_mapping_mode:1; /* RW */
996 unsigned long vga_io_port_decode_enable : 1; /* RW */ 1323 unsigned long vga_io_port_decode_enable:1; /* RW */
997 unsigned long vga_io_port_16_bit_decode : 1; /* RW */ 1324 unsigned long vga_io_port_16_bit_decode:1; /* RW */
998 unsigned long suppress_dest_registration : 1; /* RW */ 1325 unsigned long suppress_dest_registration:1; /* RW */
999 unsigned long programmed_initial_priority : 3; /* RW */ 1326 unsigned long programmed_initial_priority:3; /* RW */
1000 unsigned long use_incoming_priority : 1; /* RW */ 1327 unsigned long use_incoming_priority:1; /* RW */
1001 unsigned long enable_programmed_initial_priority : 1; /* RW */ 1328 unsigned long enable_programmed_initial_priority:1;/* RW */
1002 unsigned long rsvd_29_63 : 35; 1329 unsigned long rsvd_29_63:35;
1003 } s; 1330 } s;
1004 struct uv1h_lb_bau_misc_control_s { 1331 struct uv1h_lb_bau_misc_control_s {
1005 unsigned long rejection_delay : 8; /* RW */ 1332 unsigned long rejection_delay:8; /* RW */
1006 unsigned long apic_mode : 1; /* RW */ 1333 unsigned long apic_mode:1; /* RW */
1007 unsigned long force_broadcast : 1; /* RW */ 1334 unsigned long force_broadcast:1; /* RW */
1008 unsigned long force_lock_nop : 1; /* RW */ 1335 unsigned long force_lock_nop:1; /* RW */
1009 unsigned long qpi_agent_presence_vector : 3; /* RW */ 1336 unsigned long qpi_agent_presence_vector:3; /* RW */
1010 unsigned long descriptor_fetch_mode : 1; /* RW */ 1337 unsigned long descriptor_fetch_mode:1; /* RW */
1011 unsigned long enable_intd_soft_ack_mode : 1; /* RW */ 1338 unsigned long enable_intd_soft_ack_mode:1; /* RW */
1012 unsigned long intd_soft_ack_timeout_period : 4; /* RW */ 1339 unsigned long intd_soft_ack_timeout_period:4; /* RW */
1013 unsigned long enable_dual_mapping_mode : 1; /* RW */ 1340 unsigned long enable_dual_mapping_mode:1; /* RW */
1014 unsigned long vga_io_port_decode_enable : 1; /* RW */ 1341 unsigned long vga_io_port_decode_enable:1; /* RW */
1015 unsigned long vga_io_port_16_bit_decode : 1; /* RW */ 1342 unsigned long vga_io_port_16_bit_decode:1; /* RW */
1016 unsigned long suppress_dest_registration : 1; /* RW */ 1343 unsigned long suppress_dest_registration:1; /* RW */
1017 unsigned long programmed_initial_priority : 3; /* RW */ 1344 unsigned long programmed_initial_priority:3; /* RW */
1018 unsigned long use_incoming_priority : 1; /* RW */ 1345 unsigned long use_incoming_priority:1; /* RW */
1019 unsigned long enable_programmed_initial_priority : 1; /* RW */ 1346 unsigned long enable_programmed_initial_priority:1;/* RW */
1020 unsigned long rsvd_29_47 : 19; /* */ 1347 unsigned long rsvd_29_47:19;
1021 unsigned long fun : 16; /* RW */ 1348 unsigned long fun:16; /* RW */
1022 } s1; 1349 } s1;
1023 struct uv2h_lb_bau_misc_control_s { 1350 struct uv2h_lb_bau_misc_control_s {
1024 unsigned long rejection_delay : 8; /* RW */ 1351 unsigned long rejection_delay:8; /* RW */
1025 unsigned long apic_mode : 1; /* RW */ 1352 unsigned long apic_mode:1; /* RW */
1026 unsigned long force_broadcast : 1; /* RW */ 1353 unsigned long force_broadcast:1; /* RW */
1027 unsigned long force_lock_nop : 1; /* RW */ 1354 unsigned long force_lock_nop:1; /* RW */
1028 unsigned long qpi_agent_presence_vector : 3; /* RW */ 1355 unsigned long qpi_agent_presence_vector:3; /* RW */
1029 unsigned long descriptor_fetch_mode : 1; /* RW */ 1356 unsigned long descriptor_fetch_mode:1; /* RW */
1030 unsigned long enable_intd_soft_ack_mode : 1; /* RW */ 1357 unsigned long enable_intd_soft_ack_mode:1; /* RW */
1031 unsigned long intd_soft_ack_timeout_period : 4; /* RW */ 1358 unsigned long intd_soft_ack_timeout_period:4; /* RW */
1032 unsigned long enable_dual_mapping_mode : 1; /* RW */ 1359 unsigned long enable_dual_mapping_mode:1; /* RW */
1033 unsigned long vga_io_port_decode_enable : 1; /* RW */ 1360 unsigned long vga_io_port_decode_enable:1; /* RW */
1034 unsigned long vga_io_port_16_bit_decode : 1; /* RW */ 1361 unsigned long vga_io_port_16_bit_decode:1; /* RW */
1035 unsigned long suppress_dest_registration : 1; /* RW */ 1362 unsigned long suppress_dest_registration:1; /* RW */
1036 unsigned long programmed_initial_priority : 3; /* RW */ 1363 unsigned long programmed_initial_priority:3; /* RW */
1037 unsigned long use_incoming_priority : 1; /* RW */ 1364 unsigned long use_incoming_priority:1; /* RW */
1038 unsigned long enable_programmed_initial_priority : 1; /* RW */ 1365 unsigned long enable_programmed_initial_priority:1;/* RW */
1039 unsigned long enable_automatic_apic_mode_selection : 1; /* RW */ 1366 unsigned long enable_automatic_apic_mode_selection:1;/* RW */
1040 unsigned long apic_mode_status : 1; /* RO */ 1367 unsigned long apic_mode_status:1; /* RO */
1041 unsigned long suppress_interrupts_to_self : 1; /* RW */ 1368 unsigned long suppress_interrupts_to_self:1; /* RW */
1042 unsigned long enable_lock_based_system_flush : 1; /* RW */ 1369 unsigned long enable_lock_based_system_flush:1;/* RW */
1043 unsigned long enable_extended_sb_status : 1; /* RW */ 1370 unsigned long enable_extended_sb_status:1; /* RW */
1044 unsigned long suppress_int_prio_udt_to_self : 1; /* RW */ 1371 unsigned long suppress_int_prio_udt_to_self:1;/* RW */
1045 unsigned long use_legacy_descriptor_formats : 1; /* RW */ 1372 unsigned long use_legacy_descriptor_formats:1;/* RW */
1046 unsigned long rsvd_36_47 : 12; /* */ 1373 unsigned long rsvd_36_47:12;
1047 unsigned long fun : 16; /* RW */ 1374 unsigned long fun:16; /* RW */
1048 } s2; 1375 } s2;
1049}; 1376};
1050 1377
1051/* ========================================================================= */ 1378/* ========================================================================= */
1052/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 1379/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */
1053/* ========================================================================= */ 1380/* ========================================================================= */
1054#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 1381#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
1055#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 1382#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
1056 1383
1057#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 1384#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
1058#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL 1385#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
1059#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 1386#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
1060#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL 1387#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
1061#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63 1388#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
1062#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL 1389#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
1063 1390
1064union uvh_lb_bau_sb_activation_control_u { 1391union uvh_lb_bau_sb_activation_control_u {
1065 unsigned long v; 1392 unsigned long v;
1066 struct uvh_lb_bau_sb_activation_control_s { 1393 struct uvh_lb_bau_sb_activation_control_s {
1067 unsigned long index : 6; /* RW */ 1394 unsigned long index:6; /* RW */
1068 unsigned long rsvd_6_61: 56; /* */ 1395 unsigned long rsvd_6_61:56;
1069 unsigned long push : 1; /* WP */ 1396 unsigned long push:1; /* WP */
1070 unsigned long init : 1; /* WP */ 1397 unsigned long init:1; /* WP */
1071 } s; 1398 } s;
1072}; 1399};
1073 1400
1074/* ========================================================================= */ 1401/* ========================================================================= */
1075/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ 1402/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */
1076/* ========================================================================= */ 1403/* ========================================================================= */
1077#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 1404#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
1078#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 1405#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
1079 1406
1080#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 1407#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
1081#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL 1408#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
1082 1409
1083union uvh_lb_bau_sb_activation_status_0_u { 1410union uvh_lb_bau_sb_activation_status_0_u {
1084 unsigned long v; 1411 unsigned long v;
1085 struct uvh_lb_bau_sb_activation_status_0_s { 1412 struct uvh_lb_bau_sb_activation_status_0_s {
1086 unsigned long status : 64; /* RW */ 1413 unsigned long status:64; /* RW */
1087 } s; 1414 } s;
1088}; 1415};
1089 1416
1090/* ========================================================================= */ 1417/* ========================================================================= */
1091/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ 1418/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */
1092/* ========================================================================= */ 1419/* ========================================================================= */
1093#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 1420#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
1094#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 1421#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
1095 1422
1096#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 1423#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
1097#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL 1424#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
1098 1425
1099union uvh_lb_bau_sb_activation_status_1_u { 1426union uvh_lb_bau_sb_activation_status_1_u {
1100 unsigned long v; 1427 unsigned long v;
1101 struct uvh_lb_bau_sb_activation_status_1_s { 1428 struct uvh_lb_bau_sb_activation_status_1_s {
1102 unsigned long status : 64; /* RW */ 1429 unsigned long status:64; /* RW */
1103 } s; 1430 } s;
1104}; 1431};
1105 1432
1106/* ========================================================================= */ 1433/* ========================================================================= */
1107/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ 1434/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */
1108/* ========================================================================= */ 1435/* ========================================================================= */
1109#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 1436#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
1110#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 1437#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
1111 1438
1112#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 1439#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
1113#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 1440#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
1114#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 1441#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
1115#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL 1442#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
1116 1443
1117union uvh_lb_bau_sb_descriptor_base_u { 1444union uvh_lb_bau_sb_descriptor_base_u {
1118 unsigned long v; 1445 unsigned long v;
1119 struct uvh_lb_bau_sb_descriptor_base_s { 1446 struct uvh_lb_bau_sb_descriptor_base_s {
1120 unsigned long rsvd_0_11 : 12; /* */ 1447 unsigned long rsvd_0_11:12;
1121 unsigned long page_address : 31; /* RW */ 1448 unsigned long page_address:31; /* RW */
1122 unsigned long rsvd_43_48 : 6; /* */ 1449 unsigned long rsvd_43_48:6;
1123 unsigned long node_id : 14; /* RW */ 1450 unsigned long node_id:14; /* RW */
1124 unsigned long rsvd_63 : 1; /* */ 1451 unsigned long rsvd_63:1;
1125 } s; 1452 } s;
1126}; 1453};
1127 1454
1128/* ========================================================================= */ 1455/* ========================================================================= */
1129/* UVH_NODE_ID */ 1456/* UVH_NODE_ID */
1130/* ========================================================================= */ 1457/* ========================================================================= */
1131#define UVH_NODE_ID 0x0UL 1458#define UVH_NODE_ID 0x0UL
1132 1459
1133#define UVH_NODE_ID_FORCE1_SHFT 0 1460#define UVH_NODE_ID_FORCE1_SHFT 0
1134#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL 1461#define UVH_NODE_ID_MANUFACTURER_SHFT 1
1135#define UVH_NODE_ID_MANUFACTURER_SHFT 1 1462#define UVH_NODE_ID_PART_NUMBER_SHFT 12
1136#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 1463#define UVH_NODE_ID_REVISION_SHFT 28
1137#define UVH_NODE_ID_PART_NUMBER_SHFT 12 1464#define UVH_NODE_ID_NODE_ID_SHFT 32
1138#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 1465#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1139#define UVH_NODE_ID_REVISION_SHFT 28 1466#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1140#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL 1467#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1141#define UVH_NODE_ID_NODE_ID_SHFT 32 1468#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1142#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 1469#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1143 1470
1144#define UV1H_NODE_ID_FORCE1_SHFT 0 1471#define UV1H_NODE_ID_FORCE1_SHFT 0
1145#define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 1472#define UV1H_NODE_ID_MANUFACTURER_SHFT 1
1146#define UV1H_NODE_ID_MANUFACTURER_SHFT 1 1473#define UV1H_NODE_ID_PART_NUMBER_SHFT 12
1147#define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 1474#define UV1H_NODE_ID_REVISION_SHFT 28
1148#define UV1H_NODE_ID_PART_NUMBER_SHFT 12 1475#define UV1H_NODE_ID_NODE_ID_SHFT 32
1149#define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 1476#define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48
1150#define UV1H_NODE_ID_REVISION_SHFT 28 1477#define UV1H_NODE_ID_NI_PORT_SHFT 56
1151#define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 1478#define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1152#define UV1H_NODE_ID_NODE_ID_SHFT 32 1479#define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1153#define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 1480#define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1154#define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48 1481#define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1155#define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL 1482#define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1156#define UV1H_NODE_ID_NI_PORT_SHFT 56 1483#define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
1157#define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL 1484#define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
1158 1485
1159#define UV2H_NODE_ID_FORCE1_SHFT 0 1486#define UV2H_NODE_ID_FORCE1_SHFT 0
1160#define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 1487#define UV2H_NODE_ID_MANUFACTURER_SHFT 1
1161#define UV2H_NODE_ID_MANUFACTURER_SHFT 1 1488#define UV2H_NODE_ID_PART_NUMBER_SHFT 12
1162#define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 1489#define UV2H_NODE_ID_REVISION_SHFT 28
1163#define UV2H_NODE_ID_PART_NUMBER_SHFT 12 1490#define UV2H_NODE_ID_NODE_ID_SHFT 32
1164#define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 1491#define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50
1165#define UV2H_NODE_ID_REVISION_SHFT 28 1492#define UV2H_NODE_ID_NI_PORT_SHFT 57
1166#define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 1493#define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1167#define UV2H_NODE_ID_NODE_ID_SHFT 32 1494#define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1168#define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 1495#define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1169#define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50 1496#define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1170#define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 1497#define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1171#define UV2H_NODE_ID_NI_PORT_SHFT 57 1498#define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL
1172#define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 1499#define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL
1173 1500
1174union uvh_node_id_u { 1501union uvh_node_id_u {
1175 unsigned long v; 1502 unsigned long v;
1176 struct uvh_node_id_s { 1503 struct uvh_node_id_s {
1177 unsigned long force1 : 1; /* RO */ 1504 unsigned long force1:1; /* RO */
1178 unsigned long manufacturer : 11; /* RO */ 1505 unsigned long manufacturer:11; /* RO */
1179 unsigned long part_number : 16; /* RO */ 1506 unsigned long part_number:16; /* RO */
1180 unsigned long revision : 4; /* RO */ 1507 unsigned long revision:4; /* RO */
1181 unsigned long node_id : 15; /* RW */ 1508 unsigned long node_id:15; /* RW */
1182 unsigned long rsvd_47_63 : 17; 1509 unsigned long rsvd_47_63:17;
1183 } s; 1510 } s;
1184 struct uv1h_node_id_s { 1511 struct uv1h_node_id_s {
1185 unsigned long force1 : 1; /* RO */ 1512 unsigned long force1:1; /* RO */
1186 unsigned long manufacturer : 11; /* RO */ 1513 unsigned long manufacturer:11; /* RO */
1187 unsigned long part_number : 16; /* RO */ 1514 unsigned long part_number:16; /* RO */
1188 unsigned long revision : 4; /* RO */ 1515 unsigned long revision:4; /* RO */
1189 unsigned long node_id : 15; /* RW */ 1516 unsigned long node_id:15; /* RW */
1190 unsigned long rsvd_47 : 1; /* */ 1517 unsigned long rsvd_47:1;
1191 unsigned long nodes_per_bit : 7; /* RW */ 1518 unsigned long nodes_per_bit:7; /* RW */
1192 unsigned long rsvd_55 : 1; /* */ 1519 unsigned long rsvd_55:1;
1193 unsigned long ni_port : 4; /* RO */ 1520 unsigned long ni_port:4; /* RO */
1194 unsigned long rsvd_60_63 : 4; /* */ 1521 unsigned long rsvd_60_63:4;
1195 } s1; 1522 } s1;
1196 struct uv2h_node_id_s { 1523 struct uv2h_node_id_s {
1197 unsigned long force1 : 1; /* RO */ 1524 unsigned long force1:1; /* RO */
1198 unsigned long manufacturer : 11; /* RO */ 1525 unsigned long manufacturer:11; /* RO */
1199 unsigned long part_number : 16; /* RO */ 1526 unsigned long part_number:16; /* RO */
1200 unsigned long revision : 4; /* RO */ 1527 unsigned long revision:4; /* RO */
1201 unsigned long node_id : 15; /* RW */ 1528 unsigned long node_id:15; /* RW */
1202 unsigned long rsvd_47_49 : 3; /* */ 1529 unsigned long rsvd_47_49:3;
1203 unsigned long nodes_per_bit : 7; /* RO */ 1530 unsigned long nodes_per_bit:7; /* RO */
1204 unsigned long ni_port : 5; /* RO */ 1531 unsigned long ni_port:5; /* RO */
1205 unsigned long rsvd_62_63 : 2; /* */ 1532 unsigned long rsvd_62_63:2;
1206 } s2; 1533 } s2;
1207}; 1534};
1208 1535
1209/* ========================================================================= */ 1536/* ========================================================================= */
1210/* UVH_NODE_PRESENT_TABLE */ 1537/* UVH_NODE_PRESENT_TABLE */
1211/* ========================================================================= */ 1538/* ========================================================================= */
1212#define UVH_NODE_PRESENT_TABLE 0x1400UL 1539#define UVH_NODE_PRESENT_TABLE 0x1400UL
1213#define UVH_NODE_PRESENT_TABLE_DEPTH 16 1540#define UVH_NODE_PRESENT_TABLE_DEPTH 16
1214 1541
1215#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 1542#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0
1216#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL 1543#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
1217 1544
1218union uvh_node_present_table_u { 1545union uvh_node_present_table_u {
1219 unsigned long v; 1546 unsigned long v;
1220 struct uvh_node_present_table_s { 1547 struct uvh_node_present_table_s {
1221 unsigned long nodes : 64; /* RW */ 1548 unsigned long nodes:64; /* RW */
1222 } s; 1549 } s;
1223}; 1550};
1224 1551
1225/* ========================================================================= */ 1552/* ========================================================================= */
1226/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */ 1553/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */
1227/* ========================================================================= */ 1554/* ========================================================================= */
1228#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 1555#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
1229 1556
1230#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 1557#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
1231#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
1232#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 1558#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
1233#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
1234#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 1559#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
1560#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
1561#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
1235#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 1562#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
1236 1563
1237union uvh_rh_gam_alias210_overlay_config_0_mmr_u { 1564union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
1238 unsigned long v; 1565 unsigned long v;
1239 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s { 1566 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
1240 unsigned long rsvd_0_23: 24; /* */ 1567 unsigned long rsvd_0_23:24;
1241 unsigned long base : 8; /* RW */ 1568 unsigned long base:8; /* RW */
1242 unsigned long rsvd_32_47: 16; /* */ 1569 unsigned long rsvd_32_47:16;
1243 unsigned long m_alias : 5; /* RW */ 1570 unsigned long m_alias:5; /* RW */
1244 unsigned long rsvd_53_62: 10; /* */ 1571 unsigned long rsvd_53_62:10;
1245 unsigned long enable : 1; /* RW */ 1572 unsigned long enable:1; /* RW */
1246 } s; 1573 } s;
1247}; 1574};
1248 1575
1249/* ========================================================================= */ 1576/* ========================================================================= */
1250/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */ 1577/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */
1251/* ========================================================================= */ 1578/* ========================================================================= */
1252#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 1579#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
1253 1580
1254#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 1581#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
1255#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
1256#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 1582#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
1257#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
1258#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 1583#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
1584#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
1585#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
1259#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 1586#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
1260 1587
1261union uvh_rh_gam_alias210_overlay_config_1_mmr_u { 1588union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
1262 unsigned long v; 1589 unsigned long v;
1263 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s { 1590 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
1264 unsigned long rsvd_0_23: 24; /* */ 1591 unsigned long rsvd_0_23:24;
1265 unsigned long base : 8; /* RW */ 1592 unsigned long base:8; /* RW */
1266 unsigned long rsvd_32_47: 16; /* */ 1593 unsigned long rsvd_32_47:16;
1267 unsigned long m_alias : 5; /* RW */ 1594 unsigned long m_alias:5; /* RW */
1268 unsigned long rsvd_53_62: 10; /* */ 1595 unsigned long rsvd_53_62:10;
1269 unsigned long enable : 1; /* RW */ 1596 unsigned long enable:1; /* RW */
1270 } s; 1597 } s;
1271}; 1598};
1272 1599
1273/* ========================================================================= */ 1600/* ========================================================================= */
1274/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */ 1601/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */
1275/* ========================================================================= */ 1602/* ========================================================================= */
1276#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 1603#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
1277 1604
1278#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 1605#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
1279#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
1280#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 1606#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
1281#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
1282#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 1607#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
1608#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
1609#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
1283#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 1610#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
1284 1611
1285union uvh_rh_gam_alias210_overlay_config_2_mmr_u { 1612union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
1286 unsigned long v; 1613 unsigned long v;
1287 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s { 1614 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
1288 unsigned long rsvd_0_23: 24; /* */ 1615 unsigned long rsvd_0_23:24;
1289 unsigned long base : 8; /* RW */ 1616 unsigned long base:8; /* RW */
1290 unsigned long rsvd_32_47: 16; /* */ 1617 unsigned long rsvd_32_47:16;
1291 unsigned long m_alias : 5; /* RW */ 1618 unsigned long m_alias:5; /* RW */
1292 unsigned long rsvd_53_62: 10; /* */ 1619 unsigned long rsvd_53_62:10;
1293 unsigned long enable : 1; /* RW */ 1620 unsigned long enable:1; /* RW */
1294 } s; 1621 } s;
1295}; 1622};
1296 1623
1297/* ========================================================================= */ 1624/* ========================================================================= */
1298/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ 1625/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
1299/* ========================================================================= */ 1626/* ========================================================================= */
1300#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 1627#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
1301 1628
1302#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 1629#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
1303#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 1630#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1304 1631
1305union uvh_rh_gam_alias210_redirect_config_0_mmr_u { 1632union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
1306 unsigned long v; 1633 unsigned long v;
1307 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { 1634 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
1308 unsigned long rsvd_0_23 : 24; /* */ 1635 unsigned long rsvd_0_23:24;
1309 unsigned long dest_base : 22; /* RW */ 1636 unsigned long dest_base:22; /* RW */
1310 unsigned long rsvd_46_63: 18; /* */ 1637 unsigned long rsvd_46_63:18;
1311 } s; 1638 } s;
1312}; 1639};
1313 1640
1314/* ========================================================================= */ 1641/* ========================================================================= */
1315/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ 1642/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
1316/* ========================================================================= */ 1643/* ========================================================================= */
1317#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 1644#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
1318 1645
1319#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 1646#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
1320#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 1647#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1321 1648
1322union uvh_rh_gam_alias210_redirect_config_1_mmr_u { 1649union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
1323 unsigned long v; 1650 unsigned long v;
1324 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { 1651 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
1325 unsigned long rsvd_0_23 : 24; /* */ 1652 unsigned long rsvd_0_23:24;
1326 unsigned long dest_base : 22; /* RW */ 1653 unsigned long dest_base:22; /* RW */
1327 unsigned long rsvd_46_63: 18; /* */ 1654 unsigned long rsvd_46_63:18;
1328 } s; 1655 } s;
1329}; 1656};
1330 1657
1331/* ========================================================================= */ 1658/* ========================================================================= */
1332/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ 1659/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
1333/* ========================================================================= */ 1660/* ========================================================================= */
1334#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 1661#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
1335 1662
1336#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 1663#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
1337#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 1664#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1338 1665
1339union uvh_rh_gam_alias210_redirect_config_2_mmr_u { 1666union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
1340 unsigned long v; 1667 unsigned long v;
1341 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { 1668 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
1342 unsigned long rsvd_0_23 : 24; /* */ 1669 unsigned long rsvd_0_23:24;
1343 unsigned long dest_base : 22; /* RW */ 1670 unsigned long dest_base:22; /* RW */
1344 unsigned long rsvd_46_63: 18; /* */ 1671 unsigned long rsvd_46_63:18;
1345 } s; 1672 } s;
1346}; 1673};
1347 1674
1348/* ========================================================================= */ 1675/* ========================================================================= */
1349/* UVH_RH_GAM_CONFIG_MMR */ 1676/* UVH_RH_GAM_CONFIG_MMR */
1350/* ========================================================================= */ 1677/* ========================================================================= */
1351#define UVH_RH_GAM_CONFIG_MMR 0x1600000UL 1678#define UVH_RH_GAM_CONFIG_MMR 0x1600000UL
1352 1679
1353#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 1680#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1354#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 1681#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1355#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 1682#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1356#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 1683#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
1357 1684
1358#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 1685#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1359#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 1686#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1360#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 1687#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12
1361#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 1688#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1362#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12 1689#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
1363#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL 1690#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL
1364 1691
1365#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 1692#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1366#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 1693#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1367#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 1694#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1368#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 1695#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
1369 1696
1370union uvh_rh_gam_config_mmr_u { 1697union uvh_rh_gam_config_mmr_u {
1371 unsigned long v; 1698 unsigned long v;
1372 struct uvh_rh_gam_config_mmr_s { 1699 struct uvh_rh_gam_config_mmr_s {
1373 unsigned long m_skt : 6; /* RW */ 1700 unsigned long m_skt:6; /* RW */
1374 unsigned long n_skt : 4; /* RW */ 1701 unsigned long n_skt:4; /* RW */
1375 unsigned long rsvd_10_63 : 54; 1702 unsigned long rsvd_10_63:54;
1376 } s; 1703 } s;
1377 struct uv1h_rh_gam_config_mmr_s { 1704 struct uv1h_rh_gam_config_mmr_s {
1378 unsigned long m_skt : 6; /* RW */ 1705 unsigned long m_skt:6; /* RW */
1379 unsigned long n_skt : 4; /* RW */ 1706 unsigned long n_skt:4; /* RW */
1380 unsigned long rsvd_10_11: 2; /* */ 1707 unsigned long rsvd_10_11:2;
1381 unsigned long mmiol_cfg : 1; /* RW */ 1708 unsigned long mmiol_cfg:1; /* RW */
1382 unsigned long rsvd_13_63: 51; /* */ 1709 unsigned long rsvd_13_63:51;
1383 } s1; 1710 } s1;
1384 struct uv2h_rh_gam_config_mmr_s { 1711 struct uv2h_rh_gam_config_mmr_s {
1385 unsigned long m_skt : 6; /* RW */ 1712 unsigned long m_skt:6; /* RW */
1386 unsigned long n_skt : 4; /* RW */ 1713 unsigned long n_skt:4; /* RW */
1387 unsigned long rsvd_10_63: 54; /* */ 1714 unsigned long rsvd_10_63:54;
1388 } s2; 1715 } s2;
1389}; 1716};
1390 1717
1391/* ========================================================================= */ 1718/* ========================================================================= */
1392/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ 1719/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
1393/* ========================================================================= */ 1720/* ========================================================================= */
1394#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 1721#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
1395 1722
1396#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 1723#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1397#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 1724#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1398 1725
1399#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 1726#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1400#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 1727#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
1401#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 1728#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
1402#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL 1729#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1403#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 1730#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1404#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 1731#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
1405#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1732#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
1406#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1733#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1407 1734
1408#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 1735#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1409#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 1736#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
1410#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 1737#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1411#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 1738#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1412#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1739#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
1413#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1740#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1414 1741
1415union uvh_rh_gam_gru_overlay_config_mmr_u { 1742union uvh_rh_gam_gru_overlay_config_mmr_u {
1416 unsigned long v; 1743 unsigned long v;
1417 struct uvh_rh_gam_gru_overlay_config_mmr_s { 1744 struct uvh_rh_gam_gru_overlay_config_mmr_s {
1418 unsigned long rsvd_0_27: 28; /* */ 1745 unsigned long rsvd_0_27:28;
1419 unsigned long base : 18; /* RW */ 1746 unsigned long base:18; /* RW */
1420 unsigned long rsvd_46_62 : 17; 1747 unsigned long rsvd_46_62:17;
1421 unsigned long enable : 1; /* RW */ 1748 unsigned long enable:1; /* RW */
1422 } s; 1749 } s;
1423 struct uv1h_rh_gam_gru_overlay_config_mmr_s { 1750 struct uv1h_rh_gam_gru_overlay_config_mmr_s {
1424 unsigned long rsvd_0_27: 28; /* */ 1751 unsigned long rsvd_0_27:28;
1425 unsigned long base : 18; /* RW */ 1752 unsigned long base:18; /* RW */
1426 unsigned long rsvd_46_47: 2; /* */ 1753 unsigned long rsvd_46_47:2;
1427 unsigned long gr4 : 1; /* RW */ 1754 unsigned long gr4:1; /* RW */
1428 unsigned long rsvd_49_51: 3; /* */ 1755 unsigned long rsvd_49_51:3;
1429 unsigned long n_gru : 4; /* RW */ 1756 unsigned long n_gru:4; /* RW */
1430 unsigned long rsvd_56_62: 7; /* */ 1757 unsigned long rsvd_56_62:7;
1431 unsigned long enable : 1; /* RW */ 1758 unsigned long enable:1; /* RW */
1432 } s1; 1759 } s1;
1433 struct uv2h_rh_gam_gru_overlay_config_mmr_s { 1760 struct uv2h_rh_gam_gru_overlay_config_mmr_s {
1434 unsigned long rsvd_0_27: 28; /* */ 1761 unsigned long rsvd_0_27:28;
1435 unsigned long base : 18; /* RW */ 1762 unsigned long base:18; /* RW */
1436 unsigned long rsvd_46_51: 6; /* */ 1763 unsigned long rsvd_46_51:6;
1437 unsigned long n_gru : 4; /* RW */ 1764 unsigned long n_gru:4; /* RW */
1438 unsigned long rsvd_56_62: 7; /* */ 1765 unsigned long rsvd_56_62:7;
1439 unsigned long enable : 1; /* RW */ 1766 unsigned long enable:1; /* RW */
1440 } s2; 1767 } s2;
1441}; 1768};
1442 1769
1443/* ========================================================================= */ 1770/* ========================================================================= */
1444/* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */ 1771/* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */
1445/* ========================================================================= */ 1772/* ========================================================================= */
1446#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 1773#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
1447 1774
1448#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 1775#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
1449#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL 1776#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1450#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 1777#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1451#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1452#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1453#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1454#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1778#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1779#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
1780#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1781#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1455#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1782#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1456 1783
1457#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27 1784#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27
1458#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL 1785#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1459#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 1786#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1460#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1461#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1462#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1463#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1787#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1788#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL
1789#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1790#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1464#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1791#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1465 1792
1466union uvh_rh_gam_mmioh_overlay_config_mmr_u { 1793union uvh_rh_gam_mmioh_overlay_config_mmr_u {
1467 unsigned long v; 1794 unsigned long v;
1468 struct uv1h_rh_gam_mmioh_overlay_config_mmr_s { 1795 struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
1469 unsigned long rsvd_0_29: 30; /* */ 1796 unsigned long rsvd_0_29:30;
1470 unsigned long base : 16; /* RW */ 1797 unsigned long base:16; /* RW */
1471 unsigned long m_io : 6; /* RW */ 1798 unsigned long m_io:6; /* RW */
1472 unsigned long n_io : 4; /* RW */ 1799 unsigned long n_io:4; /* RW */
1473 unsigned long rsvd_56_62: 7; /* */ 1800 unsigned long rsvd_56_62:7;
1474 unsigned long enable : 1; /* RW */ 1801 unsigned long enable:1; /* RW */
1475 } s1; 1802 } s1;
1476 struct uv2h_rh_gam_mmioh_overlay_config_mmr_s { 1803 struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {
1477 unsigned long rsvd_0_26: 27; /* */ 1804 unsigned long rsvd_0_26:27;
1478 unsigned long base : 19; /* RW */ 1805 unsigned long base:19; /* RW */
1479 unsigned long m_io : 6; /* RW */ 1806 unsigned long m_io:6; /* RW */
1480 unsigned long n_io : 4; /* RW */ 1807 unsigned long n_io:4; /* RW */
1481 unsigned long rsvd_56_62: 7; /* */ 1808 unsigned long rsvd_56_62:7;
1482 unsigned long enable : 1; /* RW */ 1809 unsigned long enable:1; /* RW */
1483 } s2; 1810 } s2;
1484}; 1811};
1485 1812
1486/* ========================================================================= */ 1813/* ========================================================================= */
1487/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ 1814/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
1488/* ========================================================================= */ 1815/* ========================================================================= */
1489#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 1816#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
1490 1817
1491#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 1818#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1492#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 1819#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1493 1820
1494#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 1821#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1495#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1496#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 1822#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
1823#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1824#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1497#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL 1825#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
1498#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1826#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1499#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1500 1827
1501#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 1828#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1502#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 1829#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1503#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1830#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1504#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1831#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1505 1832
1506union uvh_rh_gam_mmr_overlay_config_mmr_u { 1833union uvh_rh_gam_mmr_overlay_config_mmr_u {
1507 unsigned long v; 1834 unsigned long v;
1508 struct uvh_rh_gam_mmr_overlay_config_mmr_s { 1835 struct uvh_rh_gam_mmr_overlay_config_mmr_s {
1509 unsigned long rsvd_0_25: 26; /* */ 1836 unsigned long rsvd_0_25:26;
1510 unsigned long base : 20; /* RW */ 1837 unsigned long base:20; /* RW */
1511 unsigned long rsvd_46_62 : 17; 1838 unsigned long rsvd_46_62:17;
1512 unsigned long enable : 1; /* RW */ 1839 unsigned long enable:1; /* RW */
1513 } s; 1840 } s;
1514 struct uv1h_rh_gam_mmr_overlay_config_mmr_s { 1841 struct uv1h_rh_gam_mmr_overlay_config_mmr_s {
1515 unsigned long rsvd_0_25: 26; /* */ 1842 unsigned long rsvd_0_25:26;
1516 unsigned long base : 20; /* RW */ 1843 unsigned long base:20; /* RW */
1517 unsigned long dual_hub : 1; /* RW */ 1844 unsigned long dual_hub:1; /* RW */
1518 unsigned long rsvd_47_62: 16; /* */ 1845 unsigned long rsvd_47_62:16;
1519 unsigned long enable : 1; /* RW */ 1846 unsigned long enable:1; /* RW */
1520 } s1; 1847 } s1;
1521 struct uv2h_rh_gam_mmr_overlay_config_mmr_s { 1848 struct uv2h_rh_gam_mmr_overlay_config_mmr_s {
1522 unsigned long rsvd_0_25: 26; /* */ 1849 unsigned long rsvd_0_25:26;
1523 unsigned long base : 20; /* RW */ 1850 unsigned long base:20; /* RW */
1524 unsigned long rsvd_46_62: 17; /* */ 1851 unsigned long rsvd_46_62:17;
1525 unsigned long enable : 1; /* RW */ 1852 unsigned long enable:1; /* RW */
1526 } s2; 1853 } s2;
1527}; 1854};
1528 1855
1529/* ========================================================================= */ 1856/* ========================================================================= */
1530/* UVH_RTC */ 1857/* UVH_RTC */
1531/* ========================================================================= */ 1858/* ========================================================================= */
1532#define UVH_RTC 0x340000UL 1859#define UVH_RTC 0x340000UL
1533 1860
1534#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 1861#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
1535#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL 1862#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
1536 1863
1537union uvh_rtc_u { 1864union uvh_rtc_u {
1538 unsigned long v; 1865 unsigned long v;
1539 struct uvh_rtc_s { 1866 struct uvh_rtc_s {
1540 unsigned long real_time_clock : 56; /* RW */ 1867 unsigned long real_time_clock:56; /* RW */
1541 unsigned long rsvd_56_63 : 8; /* */ 1868 unsigned long rsvd_56_63:8;
1542 } s; 1869 } s;
1543}; 1870};
1544 1871
1545/* ========================================================================= */ 1872/* ========================================================================= */
1546/* UVH_RTC1_INT_CONFIG */ 1873/* UVH_RTC1_INT_CONFIG */
1547/* ========================================================================= */ 1874/* ========================================================================= */
1548#define UVH_RTC1_INT_CONFIG 0x615c0UL 1875#define UVH_RTC1_INT_CONFIG 0x615c0UL
1549 1876
1550#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 1877#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
1551#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL 1878#define UVH_RTC1_INT_CONFIG_DM_SHFT 8
1552#define UVH_RTC1_INT_CONFIG_DM_SHFT 8 1879#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
1553#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL 1880#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
1554#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11 1881#define UVH_RTC1_INT_CONFIG_P_SHFT 13
1555#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL 1882#define UVH_RTC1_INT_CONFIG_T_SHFT 15
1556#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12 1883#define UVH_RTC1_INT_CONFIG_M_SHFT 16
1557#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL 1884#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
1558#define UVH_RTC1_INT_CONFIG_P_SHFT 13 1885#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1559#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL 1886#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
1560#define UVH_RTC1_INT_CONFIG_T_SHFT 15 1887#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1561#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL 1888#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
1562#define UVH_RTC1_INT_CONFIG_M_SHFT 16 1889#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
1563#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL 1890#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
1564#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32 1891#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
1565#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 1892#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1566 1893
1567union uvh_rtc1_int_config_u { 1894union uvh_rtc1_int_config_u {
1568 unsigned long v; 1895 unsigned long v;
1569 struct uvh_rtc1_int_config_s { 1896 struct uvh_rtc1_int_config_s {
1570 unsigned long vector_ : 8; /* RW */ 1897 unsigned long vector_:8; /* RW */
1571 unsigned long dm : 3; /* RW */ 1898 unsigned long dm:3; /* RW */
1572 unsigned long destmode : 1; /* RW */ 1899 unsigned long destmode:1; /* RW */
1573 unsigned long status : 1; /* RO */ 1900 unsigned long status:1; /* RO */
1574 unsigned long p : 1; /* RO */ 1901 unsigned long p:1; /* RO */
1575 unsigned long rsvd_14 : 1; /* */ 1902 unsigned long rsvd_14:1;
1576 unsigned long t : 1; /* RO */ 1903 unsigned long t:1; /* RO */
1577 unsigned long m : 1; /* RW */ 1904 unsigned long m:1; /* RW */
1578 unsigned long rsvd_17_31: 15; /* */ 1905 unsigned long rsvd_17_31:15;
1579 unsigned long apic_id : 32; /* RW */ 1906 unsigned long apic_id:32; /* RW */
1580 } s; 1907 } s;
1581}; 1908};
1582 1909
1583/* ========================================================================= */ 1910/* ========================================================================= */
1584/* UVH_SCRATCH5 */ 1911/* UVH_SCRATCH5 */
1585/* ========================================================================= */ 1912/* ========================================================================= */
1586#define UVH_SCRATCH5 0x2d0200UL 1913#define UVH_SCRATCH5 0x2d0200UL
1587#define UVH_SCRATCH5_32 0x778 1914#define UVH_SCRATCH5_32 0x778
1588 1915
1589#define UVH_SCRATCH5_SCRATCH5_SHFT 0 1916#define UVH_SCRATCH5_SCRATCH5_SHFT 0
1590#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL 1917#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
1591 1918
1592union uvh_scratch5_u { 1919union uvh_scratch5_u {
1593 unsigned long v; 1920 unsigned long v;
1594 struct uvh_scratch5_s { 1921 struct uvh_scratch5_s {
1595 unsigned long scratch5 : 64; /* RW, W1CS */ 1922 unsigned long scratch5:64; /* RW, W1CS */
1596 } s; 1923 } s;
1597}; 1924};
1598 1925
1599/* ========================================================================= */ 1926/* ========================================================================= */
1600/* UV2H_EVENT_OCCURRED2 */ 1927/* UV2H_EVENT_OCCURRED2 */
1601/* ========================================================================= */ 1928/* ========================================================================= */
1602#define UV2H_EVENT_OCCURRED2 0x70100UL 1929#define UV2H_EVENT_OCCURRED2 0x70100UL
1603#define UV2H_EVENT_OCCURRED2_32 0xb68 1930#define UV2H_EVENT_OCCURRED2_32 0xb68
1604 1931
1605#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0 1932#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0
1606#define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 1933#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1
1607#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1 1934#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2
1608#define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 1935#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3
1609#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2 1936#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4
1610#define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 1937#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5
1611#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3 1938#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6
1612#define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 1939#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7
1613#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4 1940#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8
1614#define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 1941#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9
1615#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5 1942#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10
1616#define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 1943#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11
1617#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6 1944#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12
1618#define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 1945#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13
1619#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7 1946#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14
1620#define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 1947#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15
1621#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8 1948#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16
1622#define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 1949#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17
1623#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9 1950#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18
1624#define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 1951#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19
1625#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10 1952#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20
1626#define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 1953#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21
1627#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11 1954#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22
1628#define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 1955#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23
1629#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12 1956#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24
1630#define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 1957#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25
1631#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13 1958#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26
1632#define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 1959#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27
1633#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14 1960#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28
1634#define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 1961#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29
1635#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15 1962#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30
1636#define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 1963#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31
1637#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16 1964#define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL
1638#define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 1965#define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL
1639#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17 1966#define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL
1640#define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 1967#define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL
1641#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18 1968#define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL
1642#define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 1969#define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL
1643#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19 1970#define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL
1644#define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 1971#define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL
1645#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20 1972#define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL
1646#define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 1973#define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL
1647#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21 1974#define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL
1648#define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 1975#define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL
1649#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22 1976#define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL
1650#define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 1977#define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL
1651#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23 1978#define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL
1652#define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 1979#define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL
1653#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24 1980#define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL
1654#define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 1981#define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL
1655#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25 1982#define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL
1656#define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 1983#define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL
1657#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26 1984#define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL
1658#define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 1985#define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL
1659#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27 1986#define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL
1660#define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 1987#define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL
1661#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28 1988#define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL
1662#define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 1989#define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL
1663#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29 1990#define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL
1664#define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 1991#define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL
1665#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30 1992#define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL
1666#define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 1993#define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL
1667#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31 1994#define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
1668#define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 1995#define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
1669 1996
1670union uv2h_event_occurred2_u { 1997union uv2h_event_occurred2_u {
1671 unsigned long v; 1998 unsigned long v;
1672 struct uv2h_event_occurred2_s { 1999 struct uv2h_event_occurred2_s {
1673 unsigned long rtc_0 : 1; /* RW */ 2000 unsigned long rtc_0:1; /* RW */
1674 unsigned long rtc_1 : 1; /* RW */ 2001 unsigned long rtc_1:1; /* RW */
1675 unsigned long rtc_2 : 1; /* RW */ 2002 unsigned long rtc_2:1; /* RW */
1676 unsigned long rtc_3 : 1; /* RW */ 2003 unsigned long rtc_3:1; /* RW */
1677 unsigned long rtc_4 : 1; /* RW */ 2004 unsigned long rtc_4:1; /* RW */
1678 unsigned long rtc_5 : 1; /* RW */ 2005 unsigned long rtc_5:1; /* RW */
1679 unsigned long rtc_6 : 1; /* RW */ 2006 unsigned long rtc_6:1; /* RW */
1680 unsigned long rtc_7 : 1; /* RW */ 2007 unsigned long rtc_7:1; /* RW */
1681 unsigned long rtc_8 : 1; /* RW */ 2008 unsigned long rtc_8:1; /* RW */
1682 unsigned long rtc_9 : 1; /* RW */ 2009 unsigned long rtc_9:1; /* RW */
1683 unsigned long rtc_10 : 1; /* RW */ 2010 unsigned long rtc_10:1; /* RW */
1684 unsigned long rtc_11 : 1; /* RW */ 2011 unsigned long rtc_11:1; /* RW */
1685 unsigned long rtc_12 : 1; /* RW */ 2012 unsigned long rtc_12:1; /* RW */
1686 unsigned long rtc_13 : 1; /* RW */ 2013 unsigned long rtc_13:1; /* RW */
1687 unsigned long rtc_14 : 1; /* RW */ 2014 unsigned long rtc_14:1; /* RW */
1688 unsigned long rtc_15 : 1; /* RW */ 2015 unsigned long rtc_15:1; /* RW */
1689 unsigned long rtc_16 : 1; /* RW */ 2016 unsigned long rtc_16:1; /* RW */
1690 unsigned long rtc_17 : 1; /* RW */ 2017 unsigned long rtc_17:1; /* RW */
1691 unsigned long rtc_18 : 1; /* RW */ 2018 unsigned long rtc_18:1; /* RW */
1692 unsigned long rtc_19 : 1; /* RW */ 2019 unsigned long rtc_19:1; /* RW */
1693 unsigned long rtc_20 : 1; /* RW */ 2020 unsigned long rtc_20:1; /* RW */
1694 unsigned long rtc_21 : 1; /* RW */ 2021 unsigned long rtc_21:1; /* RW */
1695 unsigned long rtc_22 : 1; /* RW */ 2022 unsigned long rtc_22:1; /* RW */
1696 unsigned long rtc_23 : 1; /* RW */ 2023 unsigned long rtc_23:1; /* RW */
1697 unsigned long rtc_24 : 1; /* RW */ 2024 unsigned long rtc_24:1; /* RW */
1698 unsigned long rtc_25 : 1; /* RW */ 2025 unsigned long rtc_25:1; /* RW */
1699 unsigned long rtc_26 : 1; /* RW */ 2026 unsigned long rtc_26:1; /* RW */
1700 unsigned long rtc_27 : 1; /* RW */ 2027 unsigned long rtc_27:1; /* RW */
1701 unsigned long rtc_28 : 1; /* RW */ 2028 unsigned long rtc_28:1; /* RW */
1702 unsigned long rtc_29 : 1; /* RW */ 2029 unsigned long rtc_29:1; /* RW */
1703 unsigned long rtc_30 : 1; /* RW */ 2030 unsigned long rtc_30:1; /* RW */
1704 unsigned long rtc_31 : 1; /* RW */ 2031 unsigned long rtc_31:1; /* RW */
1705 unsigned long rsvd_32_63: 32; /* */ 2032 unsigned long rsvd_32_63:32;
1706 } s1; 2033 } s1;
1707}; 2034};
1708 2035
1709/* ========================================================================= */ 2036/* ========================================================================= */
1710/* UV2H_EVENT_OCCURRED2_ALIAS */ 2037/* UV2H_EVENT_OCCURRED2_ALIAS */
1711/* ========================================================================= */ 2038/* ========================================================================= */
1712#define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL 2039#define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL
1713#define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70 2040#define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70
1714 2041
1715/* ========================================================================= */ 2042/* ========================================================================= */
1716/* UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 */ 2043/* UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 */
1717/* ========================================================================= */ 2044/* ========================================================================= */
1718#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 2045#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
1719#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 2046#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
1720 2047
1721#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 2048#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
1722#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 2049#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
1723 2050
1724union uv2h_lb_bau_sb_activation_status_2_u { 2051union uv2h_lb_bau_sb_activation_status_2_u {
1725 unsigned long v; 2052 unsigned long v;
1726 struct uv2h_lb_bau_sb_activation_status_2_s { 2053 struct uv2h_lb_bau_sb_activation_status_2_s {
1727 unsigned long aux_error : 64; /* RW */ 2054 unsigned long aux_error:64; /* RW */
1728 } s1; 2055 } s1;
1729}; 2056};
1730 2057
1731/* ========================================================================= */ 2058/* ========================================================================= */
1732/* UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK */ 2059/* UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK */
1733/* ========================================================================= */ 2060/* ========================================================================= */
1734#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL 2061#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL
1735#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0 2062#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0
1736 2063
1737#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0 2064#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
1738#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL 2065#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
1739 2066
1740union uv1h_lb_target_physical_apic_id_mask_u { 2067union uv1h_lb_target_physical_apic_id_mask_u {
1741 unsigned long v; 2068 unsigned long v;
1742 struct uv1h_lb_target_physical_apic_id_mask_s { 2069 struct uv1h_lb_target_physical_apic_id_mask_s {
1743 unsigned long bit_enables : 32; /* RW */ 2070 unsigned long bit_enables:32; /* RW */
1744 unsigned long rsvd_32_63 : 32; /* */ 2071 unsigned long rsvd_32_63:32;
1745 } s1; 2072 } s1;
1746}; 2073};
1747 2074
1748 2075
1749#endif /* __ASM_UV_MMRS_X86_H__ */ 2076#endif /* _ASM_X86_UV_UV_MMRS_H */
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index 750c346ef50a..301e325992f6 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -519,7 +519,8 @@ static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
519 if (cfg->address < 0xFFFFFFFF) 519 if (cfg->address < 0xFFFFFFFF)
520 return 0; 520 return 0;
521 521
522 if (!strcmp(mcfg->header.oem_id, "SGI")) 522 if (!strcmp(mcfg->header.oem_id, "SGI") ||
523 !strcmp(mcfg->header.oem_id, "SGI2"))
523 return 0; 524 return 0;
524 525
525 if (mcfg->header.revision >= 1) { 526 if (mcfg->header.revision >= 1) {
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index 68e467f69fec..db8b915f54bc 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -296,14 +296,18 @@ static void bau_process_message(struct msg_desc *mdp,
296} 296}
297 297
298/* 298/*
299 * Determine the first cpu on a uvhub. 299 * Determine the first cpu on a pnode.
300 */ 300 */
301static int uvhub_to_first_cpu(int uvhub) 301static int pnode_to_first_cpu(int pnode, struct bau_control *smaster)
302{ 302{
303 int cpu; 303 int cpu;
304 for_each_present_cpu(cpu) 304 struct hub_and_pnode *hpp;
305 if (uvhub == uv_cpu_to_blade_id(cpu)) 305
306 for_each_present_cpu(cpu) {
307 hpp = &smaster->thp[cpu];
308 if (pnode == hpp->pnode)
306 return cpu; 309 return cpu;
310 }
307 return -1; 311 return -1;
308} 312}
309 313
@@ -366,28 +370,32 @@ static void do_reset(void *ptr)
366 * Use IPI to get all target uvhubs to release resources held by 370 * Use IPI to get all target uvhubs to release resources held by
367 * a given sending cpu number. 371 * a given sending cpu number.
368 */ 372 */
369static void reset_with_ipi(struct bau_targ_hubmask *distribution, int sender) 373static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp)
370{ 374{
371 int uvhub; 375 int pnode;
376 int apnode;
372 int maskbits; 377 int maskbits;
373 cpumask_t mask; 378 int sender = bcp->cpu;
379 cpumask_t *mask = bcp->uvhub_master->cpumask;
380 struct bau_control *smaster = bcp->socket_master;
374 struct reset_args reset_args; 381 struct reset_args reset_args;
375 382
376 reset_args.sender = sender; 383 reset_args.sender = sender;
377 cpus_clear(mask); 384 cpus_clear(*mask);
378 /* find a single cpu for each uvhub in this distribution mask */ 385 /* find a single cpu for each uvhub in this distribution mask */
379 maskbits = sizeof(struct bau_targ_hubmask) * BITSPERBYTE; 386 maskbits = sizeof(struct pnmask) * BITSPERBYTE;
380 for (uvhub = 0; uvhub < maskbits; uvhub++) { 387 /* each bit is a pnode relative to the partition base pnode */
388 for (pnode = 0; pnode < maskbits; pnode++) {
381 int cpu; 389 int cpu;
382 if (!bau_uvhub_isset(uvhub, distribution)) 390 if (!bau_uvhub_isset(pnode, distribution))
383 continue; 391 continue;
384 /* find a cpu for this uvhub */ 392 apnode = pnode + bcp->partition_base_pnode;
385 cpu = uvhub_to_first_cpu(uvhub); 393 cpu = pnode_to_first_cpu(apnode, smaster);
386 cpu_set(cpu, mask); 394 cpu_set(cpu, *mask);
387 } 395 }
388 396
389 /* IPI all cpus; preemption is already disabled */ 397 /* IPI all cpus; preemption is already disabled */
390 smp_call_function_many(&mask, do_reset, (void *)&reset_args, 1); 398 smp_call_function_many(mask, do_reset, (void *)&reset_args, 1);
391 return; 399 return;
392} 400}
393 401
@@ -604,7 +612,7 @@ static void destination_plugged(struct bau_desc *bau_desc,
604 quiesce_local_uvhub(hmaster); 612 quiesce_local_uvhub(hmaster);
605 613
606 spin_lock(&hmaster->queue_lock); 614 spin_lock(&hmaster->queue_lock);
607 reset_with_ipi(&bau_desc->distribution, bcp->cpu); 615 reset_with_ipi(&bau_desc->distribution, bcp);
608 spin_unlock(&hmaster->queue_lock); 616 spin_unlock(&hmaster->queue_lock);
609 617
610 end_uvhub_quiesce(hmaster); 618 end_uvhub_quiesce(hmaster);
@@ -626,7 +634,7 @@ static void destination_timeout(struct bau_desc *bau_desc,
626 quiesce_local_uvhub(hmaster); 634 quiesce_local_uvhub(hmaster);
627 635
628 spin_lock(&hmaster->queue_lock); 636 spin_lock(&hmaster->queue_lock);
629 reset_with_ipi(&bau_desc->distribution, bcp->cpu); 637 reset_with_ipi(&bau_desc->distribution, bcp);
630 spin_unlock(&hmaster->queue_lock); 638 spin_unlock(&hmaster->queue_lock);
631 639
632 end_uvhub_quiesce(hmaster); 640 end_uvhub_quiesce(hmaster);
@@ -1334,9 +1342,10 @@ static ssize_t tunables_write(struct file *file, const char __user *user,
1334 1342
1335 instr[count] = '\0'; 1343 instr[count] = '\0';
1336 1344
1337 bcp = &per_cpu(bau_control, smp_processor_id()); 1345 cpu = get_cpu();
1338 1346 bcp = &per_cpu(bau_control, cpu);
1339 ret = parse_tunables_write(bcp, instr, count); 1347 ret = parse_tunables_write(bcp, instr, count);
1348 put_cpu();
1340 if (ret) 1349 if (ret)
1341 return ret; 1350 return ret;
1342 1351
@@ -1687,6 +1696,16 @@ static void make_per_cpu_thp(struct bau_control *smaster)
1687} 1696}
1688 1697
1689/* 1698/*
1699 * Each uvhub is to get a local cpumask.
1700 */
1701static void make_per_hub_cpumask(struct bau_control *hmaster)
1702{
1703 int sz = sizeof(cpumask_t);
1704
1705 hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode);
1706}
1707
1708/*
1690 * Initialize all the per_cpu information for the cpu's on a given socket, 1709 * Initialize all the per_cpu information for the cpu's on a given socket,
1691 * given what has been gathered into the socket_desc struct. 1710 * given what has been gathered into the socket_desc struct.
1692 * And reports the chosen hub and socket masters back to the caller. 1711 * And reports the chosen hub and socket masters back to the caller.
@@ -1751,11 +1770,12 @@ static int __init summarize_uvhub_sockets(int nuvhubs,
1751 sdp = &bdp->socket[socket]; 1770 sdp = &bdp->socket[socket];
1752 if (scan_sock(sdp, bdp, &smaster, &hmaster)) 1771 if (scan_sock(sdp, bdp, &smaster, &hmaster))
1753 return 1; 1772 return 1;
1773 make_per_cpu_thp(smaster);
1754 } 1774 }
1755 socket++; 1775 socket++;
1756 socket_mask = (socket_mask >> 1); 1776 socket_mask = (socket_mask >> 1);
1757 make_per_cpu_thp(smaster);
1758 } 1777 }
1778 make_per_hub_cpumask(hmaster);
1759 } 1779 }
1760 return 0; 1780 return 0;
1761} 1781}
@@ -1777,15 +1797,20 @@ static int __init init_per_cpu(int nuvhubs, int base_part_pnode)
1777 uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL); 1797 uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
1778 1798
1779 if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask)) 1799 if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask))
1780 return 1; 1800 goto fail;
1781 1801
1782 if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask)) 1802 if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask))
1783 return 1; 1803 goto fail;
1784 1804
1785 kfree(uvhub_descs); 1805 kfree(uvhub_descs);
1786 kfree(uvhub_mask); 1806 kfree(uvhub_mask);
1787 init_per_cpu_tunables(); 1807 init_per_cpu_tunables();
1788 return 0; 1808 return 0;
1809
1810fail:
1811 kfree(uvhub_descs);
1812 kfree(uvhub_mask);
1813 return 1;
1789} 1814}
1790 1815
1791/* 1816/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 02:45:47 -0500