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authorMagnus Damm <damm@igel.co.jp>2007-07-31 04:12:34 -0400
committerPaul Mundt <lethal@linux-sh.org>2007-09-20 22:57:46 -0400
commite29bfbc44332ee2233d87d5adfd1824fd8a1c73b (patch)
tree80cb6ff95302a0817ef597f974df893fb76e2445 /arch
parenta0e23267d4c57cdaa88114c3d88e25c87ee32d84 (diff)
sh: intc - add support for SH7760
This patch converts the cpu specific interrupt setup code for sh7760 from ipr + intc2 to intc. New vectors are also added to match the information provided by the datasheet. Vectors for IRQ4-IRQ7 are enabled by default. Use plat_irq_setup_pins() if pins IRL0-3 should be used in IRLM mode. The patch also adds the SIM block to the serial port platform data. Version two of this patch fixes MMCIF problems reported by Manuel Lauss. Signed-off-by: Magnus Damm <damm@igel.co.jp> Acked-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c253
-rw-r--r--arch/sh/mm/Kconfig3
2 files changed, 147 insertions, 109 deletions
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 47fa27056253..6a6686d71fbc 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -12,6 +12,136 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <asm/sci.h> 13#include <asm/sci.h>
14 14
15enum {
16 UNUSED = 0,
17
18 /* interrupt sources */
19 IRL0, IRL1, IRL2, IRL3,
20 HUDI, GPIOI,
21 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
22 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
23 DMAC_DMAE,
24 IRQ4, IRQ5, IRQ6, IRQ7,
25 HCAN20, HCAN21,
26 SSI0, SSI1,
27 HAC0, HAC1,
28 I2C0, I2C1,
29 USB, LCDC,
30 DMABRG0, DMABRG1, DMABRG2,
31 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
32 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
33 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
34 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
35 HSPI,
36 MMCIF0, MMCIF1, MMCIF2, MMCIF3,
37 MFI, ADC, CMT,
38 TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
39 WDT,
40 REF_RCMI, REF_ROVI,
41
42 /* interrupt groups */
43 DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF,
44};
45
46static struct intc_vect vectors[] = {
47 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
48 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
49 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
50 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
51 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
52 INTC_VECT(DMAC_DMAE, 0x6c0),
53 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
54 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
55 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
56 INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
57 INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
58 INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
59 INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
60 INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
61 INTC_VECT(DMABRG2, 0xac0),
62 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
63 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
64 INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
65 INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
66 INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
67 INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
68 INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
69 INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
70 INTC_VECT(HSPI, 0xc80),
71 INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
72 INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
73 INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
74 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
75 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
76 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
77 INTC_VECT(WDT, 0x560),
78 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
79};
80
81static struct intc_group groups[] = {
82 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
83 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
84 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
85 INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
86 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
87 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
88 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
89 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
90 INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
91 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
92 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
93};
94
95static struct intc_prio priorities[] = {
96 INTC_PRIO(SCIF0, 3),
97 INTC_PRIO(SCIF1, 3),
98 INTC_PRIO(SCIF2, 3),
99 INTC_PRIO(SIM, 3),
100 INTC_PRIO(DMAC, 7),
101 INTC_PRIO(DMABRG, 13),
102};
103
104static struct intc_mask_reg mask_registers[] = {
105 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
106 { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
107 SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
108 0, DMABRG0, DMABRG1, DMABRG2,
109 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
110 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
111 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
112 { 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
113 { 0, 0, 0, 0, 0, 0, 0, 0,
114 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
115 HSPI, MMCIF0, MMCIF1, MMCIF2,
116 MMCIF3, 0, 0, 0, 0, 0, 0, 0,
117 0, MFI, 0, 0, 0, 0, ADC, CMT, } },
118};
119
120static struct intc_prio_reg prio_registers[] = {
121 { 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
122 { 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
123 { 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
124 { 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
125 { 0xfe080000, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
126 { 0xfe080004, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
127 HAC0, HAC1, I2C0, I2C1 } },
128 { 0xfe080008, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
129 SCIF1, SCIF2, SIM, HSPI } },
130 { 0xfe08000c, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
131 MFI, 0, ADC, CMT } },
132};
133
134static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
135 priorities, mask_registers, prio_registers, NULL);
136
137static struct intc_vect vectors_irq[] = {
138 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
139 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
140};
141
142static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
143 priorities, mask_registers, prio_registers, NULL);
144
15static struct plat_sci_port sci_platform_data[] = { 145static struct plat_sci_port sci_platform_data[] = {
16 { 146 {
17 .mapbase = 0xfe600000, 147 .mapbase = 0xfe600000,
@@ -29,6 +159,11 @@ static struct plat_sci_port sci_platform_data[] = {
29 .type = PORT_SCIF, 159 .type = PORT_SCIF,
30 .irqs = { 76, 77, 79, 78 }, 160 .irqs = { 76, 77, 79, 78 },
31 }, { 161 }, {
162 .mapbase = 0xfe480000,
163 .flags = UPF_BOOT_AUTOCONF,
164 .type = PORT_SCI,
165 .irqs = { 80, 81, 82, 0 },
166 }, {
32 .flags = 0, 167 .flags = 0,
33 } 168 }
34}; 169};
@@ -52,114 +187,18 @@ static int __init sh7760_devices_setup(void)
52} 187}
53__initcall(sh7760_devices_setup); 188__initcall(sh7760_devices_setup);
54 189
55static struct intc2_data intc2_irq_table[] = { 190void __init plat_irq_setup_pins(int mode)
56 {48, 0, 28, 0, 31, 3}, /* IRQ 4 */ 191{
57 {49, 0, 24, 0, 30, 3}, /* IRQ 3 */ 192 switch (mode) {
58 {50, 0, 20, 0, 29, 3}, /* IRQ 2 */ 193 case IRQ_MODE_IRQ:
59 {51, 0, 16, 0, 28, 3}, /* IRQ 1 */ 194 register_intc_controller(&intc_desc_irq);
60 {56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */ 195 break;
61 {57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */ 196 default:
62 {58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */ 197 BUG();
63 {59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */ 198 }
64 {60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */ 199}
65 {61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
66 {62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
67 {63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
68 {52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
69 {53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
70 {54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
71 {55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
72 {64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
73 {65, 8, 24, 0, 16, 3}, /* LCDC */
74 {68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
75 {69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
76 {70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
77 {72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
78 {73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
79 {74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
80 {75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
81 {76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
82 {77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
83 {78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
84 {79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
85 {80, 8, 4, 4, 23, 3}, /* SIM_ERI */
86 {81, 8, 4, 4, 22, 3}, /* SIM_RXI */
87 {82, 8, 4, 4, 21, 3}, /* SIM_TXI */
88 {83, 8, 4, 4, 20, 3}, /* SIM_TEI */
89 {84, 8, 0, 4, 19, 3}, /* HSPII */
90 {88, 12, 20, 4, 18, 3}, /* MMCI0 */
91 {89, 12, 20, 4, 17, 3}, /* MMCI1 */
92 {90, 12, 20, 4, 16, 3}, /* MMCI2 */
93 {91, 12, 20, 4, 15, 3}, /* MMCI3 */
94 {92, 12, 12, 4, 6, 3}, /* MFI */
95 {108,12, 4, 4, 1, 3}, /* ADC */
96 {109,12, 0, 4, 0, 3}, /* CMTI */
97};
98
99static struct intc2_desc intc2_irq_desc __read_mostly = {
100 .prio_base = 0xfe080000,
101 .msk_base = 0xfe080040,
102 .mskclr_base = 0xfe080060,
103
104 .intc2_data = intc2_irq_table,
105 .nr_irqs = ARRAY_SIZE(intc2_irq_table),
106
107 .chip = {
108 .name = "INTC2-sh7760",
109 },
110};
111
112static struct ipr_data ipr_irq_table[] = {
113 /* IRQ, IPR-idx, shift, priority */
114 { 16, 0, 12, 2 }, /* TMU0 TUNI*/
115 { 17, 0, 8, 2 }, /* TMU1 TUNI */
116 { 18, 0, 4, 2 }, /* TMU2 TUNI */
117 { 19, 0, 4, 2 }, /* TMU2 TIPCI */
118 { 27, 1, 12, 2 }, /* WDT ITI */
119 { 28, 1, 8, 2 }, /* REF RCMI */
120 { 29, 1, 8, 2 }, /* REF ROVI */
121 { 32, 2, 0, 7 }, /* HUDI */
122 { 33, 2, 12, 7 }, /* GPIOI */
123 { 34, 2, 8, 7 }, /* DMAC DMTE0 */
124 { 35, 2, 8, 7 }, /* DMAC DMTE1 */
125 { 36, 2, 8, 7 }, /* DMAC DMTE2 */
126 { 37, 2, 8, 7 }, /* DMAC DMTE3 */
127 { 38, 2, 8, 7 }, /* DMAC DMAE */
128 { 44, 2, 8, 7 }, /* DMAC DMTE4 */
129 { 45, 2, 8, 7 }, /* DMAC DMTE5 */
130 { 46, 2, 8, 7 }, /* DMAC DMTE6 */
131 { 47, 2, 8, 7 }, /* DMAC DMTE7 */
132/* these here are only valid if INTC_ICR bit 7 is set to 1!
133 * XXX: maybe CONFIG_SH_IRLMODE symbol? SH7751 could use it too */
134#if 0
135 { 2, 3, 12, 3 }, /* IRL0 */
136 { 5, 3, 8, 3 }, /* IRL1 */
137 { 8, 3, 4, 3 }, /* IRL2 */
138 { 11, 3, 0, 3 }, /* IRL3 */
139#endif
140};
141
142static unsigned long ipr_offsets[] = {
143 0xffd00004UL, /* 0: IPRA */
144 0xffd00008UL, /* 1: IPRB */
145 0xffd0000cUL, /* 2: IPRC */
146 0xffd00010UL, /* 3: IPRD */
147};
148
149static struct ipr_desc ipr_irq_desc = {
150 .ipr_offsets = ipr_offsets,
151 .nr_offsets = ARRAY_SIZE(ipr_offsets),
152
153 .ipr_data = ipr_irq_table,
154 .nr_irqs = ARRAY_SIZE(ipr_irq_table),
155
156 .chip = {
157 .name = "IPR-sh7760",
158 },
159};
160 200
161void __init plat_irq_setup(void) 201void __init plat_irq_setup(void)
162{ 202{
163 register_intc2_controller(&intc2_irq_desc); 203 register_intc_controller(&intc_desc);
164 register_ipr_controller(&ipr_irq_desc);
165} 204}
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 99aebecc5701..c35ba72a4002 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -155,8 +155,7 @@ config CPU_SUBTYPE_SH7751R
155config CPU_SUBTYPE_SH7760 155config CPU_SUBTYPE_SH7760
156 bool "Support SH7760 processor" 156 bool "Support SH7760 processor"
157 select CPU_SH4 157 select CPU_SH4
158 select CPU_HAS_INTC2_IRQ 158 select CPU_HAS_INTC_IRQ
159 select CPU_HAS_IPR_IRQ
160 159
161config CPU_SUBTYPE_SH4_202 160config CPU_SUBTYPE_SH4_202
162 bool "Support SH4-202 processor" 161 bool "Support SH4-202 processor"
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 01:11:12 -0500