diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2011-03-24 08:25:22 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2011-03-29 08:47:57 -0400 |
commit | 6845664a6a7d443f03883db59d10749d38d98b8e (patch) | |
tree | 4b4499f4d41f24152190220d93ea186fbf991fca /arch | |
parent | 25a5662a13e604d86b0a9fd71703582a7393d8ec (diff) |
arm: Cleanup the irq namespace
Convert to the new function names. Automated with coccinelle.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch')
140 files changed, 626 insertions, 610 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 90919d5391c8..50d5b20d5c93 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c | |||
@@ -213,8 +213,8 @@ static int gic_set_wake(struct irq_data *d, unsigned int on) | |||
213 | 213 | ||
214 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) | 214 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
215 | { | 215 | { |
216 | struct gic_chip_data *chip_data = get_irq_data(irq); | 216 | struct gic_chip_data *chip_data = irq_get_handler_data(irq); |
217 | struct irq_chip *chip = get_irq_chip(irq); | 217 | struct irq_chip *chip = irq_get_chip(irq); |
218 | unsigned int cascade_irq, gic_irq; | 218 | unsigned int cascade_irq, gic_irq; |
219 | unsigned long status; | 219 | unsigned long status; |
220 | 220 | ||
@@ -257,9 +257,9 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) | |||
257 | { | 257 | { |
258 | if (gic_nr >= MAX_GIC_NR) | 258 | if (gic_nr >= MAX_GIC_NR) |
259 | BUG(); | 259 | BUG(); |
260 | if (set_irq_data(irq, &gic_data[gic_nr]) != 0) | 260 | if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) |
261 | BUG(); | 261 | BUG(); |
262 | set_irq_chained_handler(irq, gic_handle_cascade_irq); | 262 | irq_set_chained_handler(irq, gic_handle_cascade_irq); |
263 | } | 263 | } |
264 | 264 | ||
265 | static void __init gic_dist_init(struct gic_chip_data *gic, | 265 | static void __init gic_dist_init(struct gic_chip_data *gic, |
@@ -319,9 +319,9 @@ static void __init gic_dist_init(struct gic_chip_data *gic, | |||
319 | * Setup the Linux IRQ subsystem. | 319 | * Setup the Linux IRQ subsystem. |
320 | */ | 320 | */ |
321 | for (i = irq_start; i < irq_limit; i++) { | 321 | for (i = irq_start; i < irq_limit; i++) { |
322 | set_irq_chip(i, &gic_chip); | 322 | irq_set_chip(i, &gic_chip); |
323 | set_irq_chip_data(i, gic); | 323 | irq_set_chip_data(i, gic); |
324 | set_irq_handler(i, handle_level_irq); | 324 | irq_set_handler(i, handle_level_irq); |
325 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 325 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
326 | } | 326 | } |
327 | 327 | ||
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index fcddd48fe9da..c815d00eb349 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c | |||
@@ -88,8 +88,8 @@ void it8152_init_irq(void) | |||
88 | __raw_writel((0), IT8152_INTC_LDCNIRR); | 88 | __raw_writel((0), IT8152_INTC_LDCNIRR); |
89 | 89 | ||
90 | for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { | 90 | for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { |
91 | set_irq_chip(irq, &it8152_irq_chip); | 91 | irq_set_chip(irq, &it8152_irq_chip); |
92 | set_irq_handler(irq, handle_level_irq); | 92 | irq_set_handler(irq, handle_level_irq); |
93 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 93 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
94 | } | 94 | } |
95 | } | 95 | } |
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index a026a6bf4892..ea18b351f205 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c | |||
@@ -140,7 +140,7 @@ static struct locomo_dev_info locomo_devices[] = { | |||
140 | 140 | ||
141 | static void locomo_handler(unsigned int irq, struct irq_desc *desc) | 141 | static void locomo_handler(unsigned int irq, struct irq_desc *desc) |
142 | { | 142 | { |
143 | struct locomo *lchip = get_irq_chip_data(irq); | 143 | struct locomo *lchip = irq_get_chip_data(irq); |
144 | int req, i; | 144 | int req, i; |
145 | 145 | ||
146 | /* Acknowledge the parent IRQ */ | 146 | /* Acknowledge the parent IRQ */ |
@@ -197,15 +197,15 @@ static void locomo_setup_irq(struct locomo *lchip) | |||
197 | /* | 197 | /* |
198 | * Install handler for IRQ_LOCOMO_HW. | 198 | * Install handler for IRQ_LOCOMO_HW. |
199 | */ | 199 | */ |
200 | set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); | 200 | irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); |
201 | set_irq_chip_data(lchip->irq, lchip); | 201 | irq_set_chip_data(lchip->irq, lchip); |
202 | set_irq_chained_handler(lchip->irq, locomo_handler); | 202 | irq_set_chained_handler(lchip->irq, locomo_handler); |
203 | 203 | ||
204 | /* Install handlers for IRQ_LOCOMO_* */ | 204 | /* Install handlers for IRQ_LOCOMO_* */ |
205 | for ( ; irq <= lchip->irq_base + 3; irq++) { | 205 | for ( ; irq <= lchip->irq_base + 3; irq++) { |
206 | set_irq_chip(irq, &locomo_chip); | 206 | irq_set_chip(irq, &locomo_chip); |
207 | set_irq_chip_data(irq, lchip); | 207 | irq_set_chip_data(irq, lchip); |
208 | set_irq_handler(irq, handle_level_irq); | 208 | irq_set_handler(irq, handle_level_irq); |
209 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 209 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
210 | } | 210 | } |
211 | } | 211 | } |
@@ -476,8 +476,8 @@ static void __locomo_remove(struct locomo *lchip) | |||
476 | device_for_each_child(lchip->dev, NULL, locomo_remove_child); | 476 | device_for_each_child(lchip->dev, NULL, locomo_remove_child); |
477 | 477 | ||
478 | if (lchip->irq != NO_IRQ) { | 478 | if (lchip->irq != NO_IRQ) { |
479 | set_irq_chained_handler(lchip->irq, NULL); | 479 | irq_set_chained_handler(lchip->irq, NULL); |
480 | set_irq_data(lchip->irq, NULL); | 480 | irq_set_handler_data(lchip->irq, NULL); |
481 | } | 481 | } |
482 | 482 | ||
483 | iounmap(lchip->base); | 483 | iounmap(lchip->base); |
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index eb9796b0dab2..11ab3c24103c 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c | |||
@@ -202,7 +202,7 @@ static void | |||
202 | sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) | 202 | sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) |
203 | { | 203 | { |
204 | unsigned int stat0, stat1, i; | 204 | unsigned int stat0, stat1, i; |
205 | struct sa1111 *sachip = get_irq_data(irq); | 205 | struct sa1111 *sachip = irq_get_handler_data(irq); |
206 | void __iomem *mapbase = sachip->base + SA1111_INTC; | 206 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
207 | 207 | ||
208 | stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); | 208 | stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); |
@@ -472,25 +472,25 @@ static void sa1111_setup_irq(struct sa1111 *sachip) | |||
472 | sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); | 472 | sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); |
473 | 473 | ||
474 | for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { | 474 | for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { |
475 | set_irq_chip(irq, &sa1111_low_chip); | 475 | irq_set_chip(irq, &sa1111_low_chip); |
476 | set_irq_chip_data(irq, sachip); | 476 | irq_set_chip_data(irq, sachip); |
477 | set_irq_handler(irq, handle_edge_irq); | 477 | irq_set_handler(irq, handle_edge_irq); |
478 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 478 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
479 | } | 479 | } |
480 | 480 | ||
481 | for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { | 481 | for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { |
482 | set_irq_chip(irq, &sa1111_high_chip); | 482 | irq_set_chip(irq, &sa1111_high_chip); |
483 | set_irq_chip_data(irq, sachip); | 483 | irq_set_chip_data(irq, sachip); |
484 | set_irq_handler(irq, handle_edge_irq); | 484 | irq_set_handler(irq, handle_edge_irq); |
485 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 485 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
486 | } | 486 | } |
487 | 487 | ||
488 | /* | 488 | /* |
489 | * Register SA1111 interrupt | 489 | * Register SA1111 interrupt |
490 | */ | 490 | */ |
491 | set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); | 491 | irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); |
492 | set_irq_data(sachip->irq, sachip); | 492 | irq_set_handler_data(sachip->irq, sachip); |
493 | set_irq_chained_handler(sachip->irq, sa1111_irq_handler); | 493 | irq_set_chained_handler(sachip->irq, sa1111_irq_handler); |
494 | } | 494 | } |
495 | 495 | ||
496 | /* | 496 | /* |
@@ -815,8 +815,8 @@ static void __sa1111_remove(struct sa1111 *sachip) | |||
815 | clk_disable(sachip->clk); | 815 | clk_disable(sachip->clk); |
816 | 816 | ||
817 | if (sachip->irq != NO_IRQ) { | 817 | if (sachip->irq != NO_IRQ) { |
818 | set_irq_chained_handler(sachip->irq, NULL); | 818 | irq_set_chained_handler(sachip->irq, NULL); |
819 | set_irq_data(sachip->irq, NULL); | 819 | irq_set_handler_data(sachip->irq, NULL); |
820 | 820 | ||
821 | release_mem_region(sachip->phys + SA1111_INTC, 512); | 821 | release_mem_region(sachip->phys + SA1111_INTC, 512); |
822 | } | 822 | } |
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index ae5fe7292e0d..297078b4dd30 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c | |||
@@ -305,9 +305,9 @@ static void __init vic_set_irq_sources(void __iomem *base, | |||
305 | if (vic_sources & (1 << i)) { | 305 | if (vic_sources & (1 << i)) { |
306 | unsigned int irq = irq_start + i; | 306 | unsigned int irq = irq_start + i; |
307 | 307 | ||
308 | set_irq_chip(irq, &vic_chip); | 308 | irq_set_chip(irq, &vic_chip); |
309 | set_irq_chip_data(irq, base); | 309 | irq_set_chip_data(irq, base); |
310 | set_irq_handler(irq, handle_level_irq); | 310 | irq_set_handler(irq, handle_level_irq); |
311 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 311 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
312 | } | 312 | } |
313 | } | 313 | } |
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index 2ad62df37730..a9690f1c28e2 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c | |||
@@ -1043,8 +1043,8 @@ ecard_probe(int slot, card_type_t type) | |||
1043 | */ | 1043 | */ |
1044 | if (slot < 8) { | 1044 | if (slot < 8) { |
1045 | ec->irq = 32 + slot; | 1045 | ec->irq = 32 + slot; |
1046 | set_irq_chip(ec->irq, &ecard_chip); | 1046 | irq_set_chip(ec->irq, &ecard_chip); |
1047 | set_irq_handler(ec->irq, handle_level_irq); | 1047 | irq_set_handler(ec->irq, handle_level_irq); |
1048 | set_irq_flags(ec->irq, IRQF_VALID); | 1048 | set_irq_flags(ec->irq, IRQF_VALID); |
1049 | } | 1049 | } |
1050 | 1050 | ||
@@ -1103,7 +1103,7 @@ static int __init ecard_init(void) | |||
1103 | 1103 | ||
1104 | irqhw = ecard_probeirqhw(); | 1104 | irqhw = ecard_probeirqhw(); |
1105 | 1105 | ||
1106 | set_irq_chained_handler(IRQ_EXPANSIONCARD, | 1106 | irq_set_chained_handler(IRQ_EXPANSIONCARD, |
1107 | irqhw ? ecard_irqexp_handler : ecard_irq_handler); | 1107 | irqhw ? ecard_irqexp_handler : ecard_irq_handler); |
1108 | 1108 | ||
1109 | ecard_proc_init(); | 1109 | ecard_proc_init(); |
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c index d1f775e86353..9ffbf3a2dfea 100644 --- a/arch/arm/mach-at91/at91cap9_devices.c +++ b/arch/arm/mach-at91/at91cap9_devices.c | |||
@@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) | |||
72 | return; | 72 | return; |
73 | 73 | ||
74 | if (cpu_is_at91cap9_revB()) | 74 | if (cpu_is_at91cap9_revB()) |
75 | set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); | 75 | irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); |
76 | 76 | ||
77 | /* Enable VBus control for UHP ports */ | 77 | /* Enable VBus control for UHP ports */ |
78 | for (i = 0; i < data->ports; i++) { | 78 | for (i = 0; i < data->ports; i++) { |
@@ -157,7 +157,7 @@ static struct platform_device at91_usba_udc_device = { | |||
157 | void __init at91_add_device_usba(struct usba_platform_data *data) | 157 | void __init at91_add_device_usba(struct usba_platform_data *data) |
158 | { | 158 | { |
159 | if (cpu_is_at91cap9_revB()) { | 159 | if (cpu_is_at91cap9_revB()) { |
160 | set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); | 160 | irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); |
161 | at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS | | 161 | at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS | |
162 | AT91_MATRIX_UDPHS_BYPASS_LOCK); | 162 | AT91_MATRIX_UDPHS_BYPASS_LOCK); |
163 | } | 163 | } |
@@ -861,7 +861,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) | |||
861 | return; | 861 | return; |
862 | 862 | ||
863 | if (cpu_is_at91cap9_revB()) | 863 | if (cpu_is_at91cap9_revB()) |
864 | set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); | 864 | irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); |
865 | 865 | ||
866 | at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ | 866 | at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ |
867 | at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ | 867 | at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ |
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index 6fd82480756c..8512b796e653 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c | |||
@@ -287,7 +287,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state) | |||
287 | else | 287 | else |
288 | wakeups[bank] &= ~mask; | 288 | wakeups[bank] &= ~mask; |
289 | 289 | ||
290 | set_irq_wake(gpio_chip[bank].bank->id, state); | 290 | irq_set_irq_wake(gpio_chip[bank].bank->id, state); |
291 | 291 | ||
292 | return 0; | 292 | return 0; |
293 | } | 293 | } |
@@ -511,8 +511,8 @@ void __init at91_gpio_irq_setup(void) | |||
511 | * Can use the "simple" and not "edge" handler since it's | 511 | * Can use the "simple" and not "edge" handler since it's |
512 | * shorter, and the AIC handles interrupts sanely. | 512 | * shorter, and the AIC handles interrupts sanely. |
513 | */ | 513 | */ |
514 | set_irq_chip(pin, &gpio_irqchip); | 514 | irq_set_chip(pin, &gpio_irqchip); |
515 | set_irq_handler(pin, handle_simple_irq); | 515 | irq_set_handler(pin, handle_simple_irq); |
516 | set_irq_flags(pin, IRQF_VALID); | 516 | set_irq_flags(pin, IRQF_VALID); |
517 | } | 517 | } |
518 | 518 | ||
@@ -523,8 +523,8 @@ void __init at91_gpio_irq_setup(void) | |||
523 | if (prev && prev->next == this) | 523 | if (prev && prev->next == this) |
524 | continue; | 524 | continue; |
525 | 525 | ||
526 | set_irq_chip_data(id, this); | 526 | irq_set_chip_data(id, this); |
527 | set_irq_chained_handler(id, gpio_irq_handler); | 527 | irq_set_chained_handler(id, gpio_irq_handler); |
528 | } | 528 | } |
529 | pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); | 529 | pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); |
530 | } | 530 | } |
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c index b56d6b3a4087..566cec1d9073 100644 --- a/arch/arm/mach-at91/irq.c +++ b/arch/arm/mach-at91/irq.c | |||
@@ -143,8 +143,8 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) | |||
143 | /* Active Low interrupt, with the specified priority */ | 143 | /* Active Low interrupt, with the specified priority */ |
144 | at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); | 144 | at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); |
145 | 145 | ||
146 | set_irq_chip(i, &at91_aic_chip); | 146 | irq_set_chip(i, &at91_aic_chip); |
147 | set_irq_handler(i, handle_level_irq); | 147 | irq_set_handler(i, handle_level_irq); |
148 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 148 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
149 | 149 | ||
150 | /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ | 150 | /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ |
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c index 84dcda0d1d9a..c48feaf4e8e9 100644 --- a/arch/arm/mach-bcmring/irq.c +++ b/arch/arm/mach-bcmring/irq.c | |||
@@ -93,11 +93,11 @@ static void vic_init(void __iomem *base, struct irq_chip *chip, | |||
93 | unsigned int i; | 93 | unsigned int i; |
94 | for (i = 0; i < 32; i++) { | 94 | for (i = 0; i < 32; i++) { |
95 | unsigned int irq = irq_start + i; | 95 | unsigned int irq = irq_start + i; |
96 | set_irq_chip(irq, chip); | 96 | irq_set_chip(irq, chip); |
97 | set_irq_chip_data(irq, base); | 97 | irq_set_chip_data(irq, base); |
98 | 98 | ||
99 | if (vic_sources & (1 << i)) { | 99 | if (vic_sources & (1 << i)) { |
100 | set_irq_handler(irq, handle_level_irq); | 100 | irq_set_handler(irq, handle_level_irq); |
101 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 101 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
102 | } | 102 | } |
103 | } | 103 | } |
@@ -119,9 +119,9 @@ void __init bcmring_init_irq(void) | |||
119 | 119 | ||
120 | /* special cases */ | 120 | /* special cases */ |
121 | if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) { | 121 | if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) { |
122 | set_irq_handler(IRQ_GPIO0, handle_simple_irq); | 122 | irq_set_handler(IRQ_GPIO0, handle_simple_irq); |
123 | } | 123 | } |
124 | if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) { | 124 | if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) { |
125 | set_irq_handler(IRQ_GPIO1, handle_simple_irq); | 125 | irq_set_handler(IRQ_GPIO1, handle_simple_irq); |
126 | } | 126 | } |
127 | } | 127 | } |
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c index 86da7a1b2bbe..5c5ec01d8972 100644 --- a/arch/arm/mach-clps711x/irq.c +++ b/arch/arm/mach-clps711x/irq.c | |||
@@ -112,13 +112,13 @@ void __init clps711x_init_irq(void) | |||
112 | 112 | ||
113 | for (i = 0; i < NR_IRQS; i++) { | 113 | for (i = 0; i < NR_IRQS; i++) { |
114 | if (INT1_IRQS & (1 << i)) { | 114 | if (INT1_IRQS & (1 << i)) { |
115 | set_irq_handler(i, handle_level_irq); | 115 | irq_set_handler(i, handle_level_irq); |
116 | set_irq_chip(i, &int1_chip); | 116 | irq_set_chip(i, &int1_chip); |
117 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 117 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
118 | } | 118 | } |
119 | if (INT2_IRQS & (1 << i)) { | 119 | if (INT2_IRQS & (1 << i)) { |
120 | set_irq_handler(i, handle_level_irq); | 120 | irq_set_handler(i, handle_level_irq); |
121 | set_irq_chip(i, &int2_chip); | 121 | irq_set_chip(i, &int2_chip); |
122 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 122 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
123 | } | 123 | } |
124 | } | 124 | } |
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index 9abc80a86a22..f83152d643c5 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c | |||
@@ -167,9 +167,9 @@ void __init cp_intc_init(void) | |||
167 | 167 | ||
168 | /* Set up genirq dispatching for cp_intc */ | 168 | /* Set up genirq dispatching for cp_intc */ |
169 | for (i = 0; i < num_irq; i++) { | 169 | for (i = 0; i < num_irq; i++) { |
170 | set_irq_chip(i, &cp_intc_irq_chip); | 170 | irq_set_chip(i, &cp_intc_irq_chip); |
171 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 171 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
172 | set_irq_handler(i, handle_edge_irq); | 172 | irq_set_handler(i, handle_edge_irq); |
173 | } | 173 | } |
174 | 174 | ||
175 | /* Enable global interrupt */ | 175 | /* Enable global interrupt */ |
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index f33d4380e367..a0b838894ac9 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c | |||
@@ -62,7 +62,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) | |||
62 | { | 62 | { |
63 | struct davinci_gpio_regs __iomem *g; | 63 | struct davinci_gpio_regs __iomem *g; |
64 | 64 | ||
65 | g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq); | 65 | g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); |
66 | 66 | ||
67 | return g; | 67 | return g; |
68 | } | 68 | } |
@@ -208,7 +208,7 @@ pure_initcall(davinci_gpio_setup); | |||
208 | static void gpio_irq_disable(struct irq_data *d) | 208 | static void gpio_irq_disable(struct irq_data *d) |
209 | { | 209 | { |
210 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); | 210 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
211 | u32 mask = (u32) irq_data_get_irq_data(d); | 211 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
212 | 212 | ||
213 | __raw_writel(mask, &g->clr_falling); | 213 | __raw_writel(mask, &g->clr_falling); |
214 | __raw_writel(mask, &g->clr_rising); | 214 | __raw_writel(mask, &g->clr_rising); |
@@ -217,7 +217,7 @@ static void gpio_irq_disable(struct irq_data *d) | |||
217 | static void gpio_irq_enable(struct irq_data *d) | 217 | static void gpio_irq_enable(struct irq_data *d) |
218 | { | 218 | { |
219 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); | 219 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
220 | u32 mask = (u32) irq_data_get_irq_data(d); | 220 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
221 | unsigned status = irqd_get_trigger_type(d); | 221 | unsigned status = irqd_get_trigger_type(d); |
222 | 222 | ||
223 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | 223 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
@@ -233,7 +233,7 @@ static void gpio_irq_enable(struct irq_data *d) | |||
233 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) | 233 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
234 | { | 234 | { |
235 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); | 235 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
236 | u32 mask = (u32) irq_data_get_irq_data(d); | 236 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
237 | 237 | ||
238 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 238 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
239 | return -EINVAL; | 239 | return -EINVAL; |
@@ -276,7 +276,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
276 | status >>= 16; | 276 | status >>= 16; |
277 | 277 | ||
278 | /* now demux them to the right lowlevel handler */ | 278 | /* now demux them to the right lowlevel handler */ |
279 | n = (int)get_irq_data(irq); | 279 | n = (int)irq_get_handler_data(irq); |
280 | while (status) { | 280 | while (status) { |
281 | res = ffs(status); | 281 | res = ffs(status); |
282 | n += res; | 282 | n += res; |
@@ -314,7 +314,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |||
314 | static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) | 314 | static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) |
315 | { | 315 | { |
316 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); | 316 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
317 | u32 mask = (u32) irq_data_get_irq_data(d); | 317 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
318 | 318 | ||
319 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 319 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
320 | return -EINVAL; | 320 | return -EINVAL; |
@@ -397,9 +397,9 @@ static int __init davinci_gpio_irq_setup(void) | |||
397 | 397 | ||
398 | /* set the direct IRQs up to use that irqchip */ | 398 | /* set the direct IRQs up to use that irqchip */ |
399 | for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { | 399 | for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { |
400 | set_irq_chip(irq, &gpio_irqchip_unbanked); | 400 | irq_set_chip(irq, &gpio_irqchip_unbanked); |
401 | set_irq_data(irq, (void *) __gpio_mask(gpio)); | 401 | irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); |
402 | set_irq_chip_data(irq, (__force void *) g); | 402 | irq_set_chip_data(irq, (__force void *)g); |
403 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); | 403 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); |
404 | } | 404 | } |
405 | 405 | ||
@@ -421,15 +421,15 @@ static int __init davinci_gpio_irq_setup(void) | |||
421 | __raw_writel(~0, &g->clr_rising); | 421 | __raw_writel(~0, &g->clr_rising); |
422 | 422 | ||
423 | /* set up all irqs in this bank */ | 423 | /* set up all irqs in this bank */ |
424 | set_irq_chained_handler(bank_irq, gpio_irq_handler); | 424 | irq_set_chained_handler(bank_irq, gpio_irq_handler); |
425 | set_irq_chip_data(bank_irq, (__force void *) g); | 425 | irq_set_chip_data(bank_irq, (__force void *)g); |
426 | set_irq_data(bank_irq, (void *) irq); | 426 | irq_set_handler_data(bank_irq, (void *)irq); |
427 | 427 | ||
428 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { | 428 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { |
429 | set_irq_chip(irq, &gpio_irqchip); | 429 | irq_set_chip(irq, &gpio_irqchip); |
430 | set_irq_chip_data(irq, (__force void *) g); | 430 | irq_set_chip_data(irq, (__force void *)g); |
431 | set_irq_data(irq, (void *) __gpio_mask(gpio)); | 431 | irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); |
432 | set_irq_handler(irq, handle_simple_irq); | 432 | irq_set_handler(irq, handle_simple_irq); |
433 | set_irq_flags(irq, IRQF_VALID); | 433 | set_irq_flags(irq, IRQF_VALID); |
434 | } | 434 | } |
435 | 435 | ||
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index 5e05c9b64e1f..e6269a6e0014 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c | |||
@@ -154,11 +154,11 @@ void __init davinci_irq_init(void) | |||
154 | 154 | ||
155 | /* set up genirq dispatch for ARM INTC */ | 155 | /* set up genirq dispatch for ARM INTC */ |
156 | for (i = 0; i < davinci_soc_info.intc_irq_num; i++) { | 156 | for (i = 0; i < davinci_soc_info.intc_irq_num; i++) { |
157 | set_irq_chip(i, &davinci_irq_chip_0); | 157 | irq_set_chip(i, &davinci_irq_chip_0); |
158 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 158 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
159 | if (i != IRQ_TINT1_TINT34) | 159 | if (i != IRQ_TINT1_TINT34) |
160 | set_irq_handler(i, handle_edge_irq); | 160 | irq_set_handler(i, handle_edge_irq); |
161 | else | 161 | else |
162 | set_irq_handler(i, handle_level_irq); | 162 | irq_set_handler(i, handle_level_irq); |
163 | } | 163 | } |
164 | } | 164 | } |
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index aac6e23763e0..f038a19f4c6e 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c | |||
@@ -102,14 +102,14 @@ void __init dove_init_irq(void) | |||
102 | */ | 102 | */ |
103 | orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, | 103 | orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, |
104 | IRQ_DOVE_GPIO_START); | 104 | IRQ_DOVE_GPIO_START); |
105 | set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); | 105 | irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); |
106 | set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); | 106 | irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); |
107 | set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); | 107 | irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); |
108 | set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); | 108 | irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); |
109 | 109 | ||
110 | orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, | 110 | orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, |
111 | IRQ_DOVE_GPIO_START + 32); | 111 | IRQ_DOVE_GPIO_START + 32); |
112 | set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); | 112 | irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); |
113 | 113 | ||
114 | orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0, | 114 | orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0, |
115 | IRQ_DOVE_GPIO_START + 64); | 115 | IRQ_DOVE_GPIO_START + 64); |
@@ -121,10 +121,10 @@ void __init dove_init_irq(void) | |||
121 | writel(0, PMU_INTERRUPT_CAUSE); | 121 | writel(0, PMU_INTERRUPT_CAUSE); |
122 | 122 | ||
123 | for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { | 123 | for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { |
124 | set_irq_chip(i, &pmu_irq_chip); | 124 | irq_set_chip(i, &pmu_irq_chip); |
125 | set_irq_handler(i, handle_level_irq); | 125 | irq_set_handler(i, handle_level_irq); |
126 | irq_set_status_flags(i, IRQ_LEVEL); | 126 | irq_set_status_flags(i, IRQ_LEVEL); |
127 | set_irq_flags(i, IRQF_VALID); | 127 | set_irq_flags(i, IRQF_VALID); |
128 | } | 128 | } |
129 | set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); | 129 | irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); |
130 | } | 130 | } |
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c index 7df083f37fa7..caf6cbac33e0 100644 --- a/arch/arm/mach-ebsa110/core.c +++ b/arch/arm/mach-ebsa110/core.c | |||
@@ -66,8 +66,8 @@ static void __init ebsa110_init_irq(void) | |||
66 | local_irq_restore(flags); | 66 | local_irq_restore(flags); |
67 | 67 | ||
68 | for (irq = 0; irq < NR_IRQS; irq++) { | 68 | for (irq = 0; irq < NR_IRQS; irq++) { |
69 | set_irq_chip(irq, &ebsa110_irq_chip); | 69 | irq_set_chip(irq, &ebsa110_irq_chip); |
70 | set_irq_handler(irq, handle_level_irq); | 70 | irq_set_handler(irq, handle_level_irq); |
71 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 71 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
72 | } | 72 | } |
73 | } | 73 | } |
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c index 6e7bbf72b36b..7da0a5cefa5f 100644 --- a/arch/arm/mach-ep93xx/gpio.c +++ b/arch/arm/mach-ep93xx/gpio.c | |||
@@ -231,20 +231,29 @@ void __init ep93xx_gpio_init_irq(void) | |||
231 | 231 | ||
232 | for (gpio_irq = gpio_to_irq(0); | 232 | for (gpio_irq = gpio_to_irq(0); |
233 | gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { | 233 | gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { |
234 | set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip); | 234 | irq_set_chip(gpio_irq, &ep93xx_gpio_irq_chip); |
235 | set_irq_handler(gpio_irq, handle_level_irq); | 235 | irq_set_handler(gpio_irq, handle_level_irq); |
236 | set_irq_flags(gpio_irq, IRQF_VALID); | 236 | set_irq_flags(gpio_irq, IRQF_VALID); |
237 | } | 237 | } |
238 | 238 | ||
239 | set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); | 239 | irq_set_chained_handler(IRQ_EP93XX_GPIO_AB, |
240 | set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler); | 240 | ep93xx_gpio_ab_irq_handler); |
241 | set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler); | 241 | irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX, |
242 | set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler); | 242 | ep93xx_gpio_f_irq_handler); |
243 | set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler); | 243 | irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX, |
244 | set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler); | 244 | ep93xx_gpio_f_irq_handler); |
245 | set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler); | 245 | irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX, |
246 | set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler); | 246 | ep93xx_gpio_f_irq_handler); |
247 | set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler); | 247 | irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX, |
248 | ep93xx_gpio_f_irq_handler); | ||
249 | irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX, | ||
250 | ep93xx_gpio_f_irq_handler); | ||
251 | irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX, | ||
252 | ep93xx_gpio_f_irq_handler); | ||
253 | irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX, | ||
254 | ep93xx_gpio_f_irq_handler); | ||
255 | irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX, | ||
256 | ep93xx_gpio_f_irq_handler); | ||
248 | } | 257 | } |
249 | 258 | ||
250 | 259 | ||
diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c index 31618d91ce15..0c180800c8a7 100644 --- a/arch/arm/mach-exynos4/irq-combiner.c +++ b/arch/arm/mach-exynos4/irq-combiner.c | |||
@@ -54,8 +54,8 @@ static void combiner_unmask_irq(struct irq_data *data) | |||
54 | 54 | ||
55 | static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) | 55 | static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
56 | { | 56 | { |
57 | struct combiner_chip_data *chip_data = get_irq_data(irq); | 57 | struct combiner_chip_data *chip_data = irq_get_handler_data(irq); |
58 | struct irq_chip *chip = get_irq_chip(irq); | 58 | struct irq_chip *chip = irq_get_chip(irq); |
59 | unsigned int cascade_irq, combiner_irq; | 59 | unsigned int cascade_irq, combiner_irq; |
60 | unsigned long status; | 60 | unsigned long status; |
61 | 61 | ||
@@ -93,9 +93,9 @@ void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) | |||
93 | { | 93 | { |
94 | if (combiner_nr >= MAX_COMBINER_NR) | 94 | if (combiner_nr >= MAX_COMBINER_NR) |
95 | BUG(); | 95 | BUG(); |
96 | if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0) | 96 | if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) |
97 | BUG(); | 97 | BUG(); |
98 | set_irq_chained_handler(irq, combiner_handle_cascade_irq); | 98 | irq_set_chained_handler(irq, combiner_handle_cascade_irq); |
99 | } | 99 | } |
100 | 100 | ||
101 | void __init combiner_init(unsigned int combiner_nr, void __iomem *base, | 101 | void __init combiner_init(unsigned int combiner_nr, void __iomem *base, |
@@ -119,9 +119,9 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base, | |||
119 | 119 | ||
120 | for (i = irq_start; i < combiner_data[combiner_nr].irq_offset | 120 | for (i = irq_start; i < combiner_data[combiner_nr].irq_offset |
121 | + MAX_IRQ_IN_COMBINER; i++) { | 121 | + MAX_IRQ_IN_COMBINER; i++) { |
122 | set_irq_chip(i, &combiner_chip); | 122 | irq_set_chip(i, &combiner_chip); |
123 | set_irq_chip_data(i, &combiner_data[combiner_nr]); | 123 | irq_set_chip_data(i, &combiner_data[combiner_nr]); |
124 | set_irq_handler(i, handle_level_irq); | 124 | irq_set_handler(i, handle_level_irq); |
125 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 125 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
126 | } | 126 | } |
127 | } | 127 | } |
diff --git a/arch/arm/mach-exynos4/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c index 4f7ad4a796e4..0441dfc7c924 100644 --- a/arch/arm/mach-exynos4/irq-eint.c +++ b/arch/arm/mach-exynos4/irq-eint.c | |||
@@ -190,8 +190,8 @@ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) | |||
190 | 190 | ||
191 | static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) | 191 | static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) |
192 | { | 192 | { |
193 | u32 *irq_data = get_irq_data(irq); | 193 | u32 *irq_data = irq_get_handler_data(irq); |
194 | struct irq_chip *chip = get_irq_chip(irq); | 194 | struct irq_chip *chip = irq_get_chip(irq); |
195 | 195 | ||
196 | chip->irq_mask(&desc->irq_data); | 196 | chip->irq_mask(&desc->irq_data); |
197 | 197 | ||
@@ -208,18 +208,19 @@ int __init exynos4_init_irq_eint(void) | |||
208 | int irq; | 208 | int irq; |
209 | 209 | ||
210 | for (irq = 0 ; irq <= 31 ; irq++) { | 210 | for (irq = 0 ; irq <= 31 ; irq++) { |
211 | set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint); | 211 | irq_set_chip(IRQ_EINT(irq), &exynos4_irq_eint); |
212 | set_irq_handler(IRQ_EINT(irq), handle_level_irq); | 212 | irq_set_handler(IRQ_EINT(irq), handle_level_irq); |
213 | set_irq_flags(IRQ_EINT(irq), IRQF_VALID); | 213 | set_irq_flags(IRQ_EINT(irq), IRQF_VALID); |
214 | } | 214 | } |
215 | 215 | ||
216 | set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); | 216 | irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); |
217 | 217 | ||
218 | for (irq = 0 ; irq <= 15 ; irq++) { | 218 | for (irq = 0 ; irq <= 15 ; irq++) { |
219 | eint0_15_data[irq] = IRQ_EINT(irq); | 219 | eint0_15_data[irq] = IRQ_EINT(irq); |
220 | 220 | ||
221 | set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]); | 221 | irq_set_handler_data(exynos4_get_irq_nr(irq), |
222 | set_irq_chained_handler(exynos4_get_irq_nr(irq), | 222 | &eint0_15_data[irq]); |
223 | irq_set_chained_handler(exynos4_get_irq_nr(irq), | ||
223 | exynos4_irq_eint0_15); | 224 | exynos4_irq_eint0_15); |
224 | } | 225 | } |
225 | 226 | ||
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 84c5f258f2d8..06239f9a7afb 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c | |||
@@ -102,8 +102,8 @@ static void __init __fb_init_irq(void) | |||
102 | *CSR_FIQ_DISABLE = -1; | 102 | *CSR_FIQ_DISABLE = -1; |
103 | 103 | ||
104 | for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { | 104 | for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { |
105 | set_irq_chip(irq, &fb_chip); | 105 | irq_set_chip(irq, &fb_chip); |
106 | set_irq_handler(irq, handle_level_irq); | 106 | irq_set_handler(irq, handle_level_irq); |
107 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 107 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
108 | } | 108 | } |
109 | } | 109 | } |
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c index de7a5cb5dbe1..0bc528e6cb23 100644 --- a/arch/arm/mach-footbridge/isa-irq.c +++ b/arch/arm/mach-footbridge/isa-irq.c | |||
@@ -151,14 +151,14 @@ void __init isa_init_irq(unsigned int host_irq) | |||
151 | 151 | ||
152 | if (host_irq != (unsigned int)-1) { | 152 | if (host_irq != (unsigned int)-1) { |
153 | for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { | 153 | for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { |
154 | set_irq_chip(irq, &isa_lo_chip); | 154 | irq_set_chip(irq, &isa_lo_chip); |
155 | set_irq_handler(irq, handle_level_irq); | 155 | irq_set_handler(irq, handle_level_irq); |
156 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 156 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
157 | } | 157 | } |
158 | 158 | ||
159 | for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { | 159 | for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { |
160 | set_irq_chip(irq, &isa_hi_chip); | 160 | irq_set_chip(irq, &isa_hi_chip); |
161 | set_irq_handler(irq, handle_level_irq); | 161 | irq_set_handler(irq, handle_level_irq); |
162 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 162 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
163 | } | 163 | } |
164 | 164 | ||
@@ -166,7 +166,7 @@ void __init isa_init_irq(unsigned int host_irq) | |||
166 | request_resource(&ioport_resource, &pic2_resource); | 166 | request_resource(&ioport_resource, &pic2_resource); |
167 | setup_irq(IRQ_ISA_CASCADE, &irq_cascade); | 167 | setup_irq(IRQ_ISA_CASCADE, &irq_cascade); |
168 | 168 | ||
169 | set_irq_chained_handler(host_irq, isa_irq_handler); | 169 | irq_set_chained_handler(host_irq, isa_irq_handler); |
170 | 170 | ||
171 | /* | 171 | /* |
172 | * On the NetWinder, don't automatically | 172 | * On the NetWinder, don't automatically |
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c index c999b16c815f..0e7b56ea6295 100644 --- a/arch/arm/mach-gemini/gpio.c +++ b/arch/arm/mach-gemini/gpio.c | |||
@@ -217,13 +217,13 @@ void __init gemini_gpio_init(void) | |||
217 | 217 | ||
218 | for (j = GPIO_IRQ_BASE + i * 32; | 218 | for (j = GPIO_IRQ_BASE + i * 32; |
219 | j < GPIO_IRQ_BASE + (i + 1) * 32; j++) { | 219 | j < GPIO_IRQ_BASE + (i + 1) * 32; j++) { |
220 | set_irq_chip(j, &gpio_irq_chip); | 220 | irq_set_chip(j, &gpio_irq_chip); |
221 | set_irq_handler(j, handle_edge_irq); | 221 | irq_set_handler(j, handle_edge_irq); |
222 | set_irq_flags(j, IRQF_VALID); | 222 | set_irq_flags(j, IRQF_VALID); |
223 | } | 223 | } |
224 | 224 | ||
225 | set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler); | 225 | irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler); |
226 | set_irq_data(IRQ_GPIO(i), (void *)i); | 226 | irq_set_handler_data(IRQ_GPIO(i), (void *)i); |
227 | } | 227 | } |
228 | 228 | ||
229 | BUG_ON(gpiochip_add(&gemini_gpio_chip)); | 229 | BUG_ON(gpiochip_add(&gemini_gpio_chip)); |
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c index 96bc227dd849..9485a8fdf851 100644 --- a/arch/arm/mach-gemini/irq.c +++ b/arch/arm/mach-gemini/irq.c | |||
@@ -81,13 +81,13 @@ void __init gemini_init_irq(void) | |||
81 | request_resource(&iomem_resource, &irq_resource); | 81 | request_resource(&iomem_resource, &irq_resource); |
82 | 82 | ||
83 | for (i = 0; i < NR_IRQS; i++) { | 83 | for (i = 0; i < NR_IRQS; i++) { |
84 | set_irq_chip(i, &gemini_irq_chip); | 84 | irq_set_chip(i, &gemini_irq_chip); |
85 | if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { | 85 | if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { |
86 | set_irq_handler(i, handle_edge_irq); | 86 | irq_set_handler(i, handle_edge_irq); |
87 | mode |= 1 << i; | 87 | mode |= 1 << i; |
88 | level |= 1 << i; | 88 | level |= 1 << i; |
89 | } else { | 89 | } else { |
90 | set_irq_handler(i, handle_level_irq); | 90 | irq_set_handler(i, handle_level_irq); |
91 | } | 91 | } |
92 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 92 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
93 | } | 93 | } |
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c index 1f28c90932c7..f118182a99ca 100644 --- a/arch/arm/mach-h720x/common.c +++ b/arch/arm/mach-h720x/common.c | |||
@@ -199,29 +199,29 @@ void __init h720x_init_irq (void) | |||
199 | 199 | ||
200 | /* Initialize global IRQ's, fast path */ | 200 | /* Initialize global IRQ's, fast path */ |
201 | for (irq = 0; irq < NR_GLBL_IRQS; irq++) { | 201 | for (irq = 0; irq < NR_GLBL_IRQS; irq++) { |
202 | set_irq_chip(irq, &h720x_global_chip); | 202 | irq_set_chip(irq, &h720x_global_chip); |
203 | set_irq_handler(irq, handle_level_irq); | 203 | irq_set_handler(irq, handle_level_irq); |
204 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 204 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
205 | } | 205 | } |
206 | 206 | ||
207 | /* Initialize multiplexed IRQ's, slow path */ | 207 | /* Initialize multiplexed IRQ's, slow path */ |
208 | for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { | 208 | for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { |
209 | set_irq_chip(irq, &h720x_gpio_chip); | 209 | irq_set_chip(irq, &h720x_gpio_chip); |
210 | set_irq_handler(irq, handle_edge_irq); | 210 | irq_set_handler(irq, handle_edge_irq); |
211 | set_irq_flags(irq, IRQF_VALID ); | 211 | set_irq_flags(irq, IRQF_VALID ); |
212 | } | 212 | } |
213 | set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); | 213 | irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); |
214 | set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); | 214 | irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); |
215 | set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); | 215 | irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); |
216 | set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); | 216 | irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); |
217 | 217 | ||
218 | #ifdef CONFIG_CPU_H7202 | 218 | #ifdef CONFIG_CPU_H7202 |
219 | for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { | 219 | for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { |
220 | set_irq_chip(irq, &h720x_gpio_chip); | 220 | irq_set_chip(irq, &h720x_gpio_chip); |
221 | set_irq_handler(irq, handle_edge_irq); | 221 | irq_set_handler(irq, handle_edge_irq); |
222 | set_irq_flags(irq, IRQF_VALID ); | 222 | set_irq_flags(irq, IRQF_VALID ); |
223 | } | 223 | } |
224 | set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); | 224 | irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); |
225 | #endif | 225 | #endif |
226 | 226 | ||
227 | /* Enable multiplexed irq's */ | 227 | /* Enable multiplexed irq's */ |
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c index bcf91a517278..dd5c72a75dad 100644 --- a/arch/arm/mach-h720x/cpu-h7202.c +++ b/arch/arm/mach-h720x/cpu-h7202.c | |||
@@ -202,11 +202,11 @@ void __init h7202_init_irq (void) | |||
202 | for (irq = IRQ_TIMER1; | 202 | for (irq = IRQ_TIMER1; |
203 | irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { | 203 | irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { |
204 | __mask_timerx_irq(irq); | 204 | __mask_timerx_irq(irq); |
205 | set_irq_chip(irq, &h7202_timerx_chip); | 205 | irq_set_chip(irq, &h7202_timerx_chip); |
206 | set_irq_handler(irq, handle_edge_irq); | 206 | irq_set_handler(irq, handle_edge_irq); |
207 | set_irq_flags(irq, IRQF_VALID ); | 207 | set_irq_flags(irq, IRQF_VALID ); |
208 | } | 208 | } |
209 | set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); | 209 | irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); |
210 | 210 | ||
211 | h720x_init_irq(); | 211 | h720x_init_irq(); |
212 | } | 212 | } |
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index a233470dd10c..bc739701c301 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c | |||
@@ -224,15 +224,15 @@ void __init iop13xx_init_irq(void) | |||
224 | 224 | ||
225 | for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { | 225 | for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { |
226 | if (i < 32) | 226 | if (i < 32) |
227 | set_irq_chip(i, &iop13xx_irqchip1); | 227 | irq_set_chip(i, &iop13xx_irqchip1); |
228 | else if (i < 64) | 228 | else if (i < 64) |
229 | set_irq_chip(i, &iop13xx_irqchip2); | 229 | irq_set_chip(i, &iop13xx_irqchip2); |
230 | else if (i < 96) | 230 | else if (i < 96) |
231 | set_irq_chip(i, &iop13xx_irqchip3); | 231 | irq_set_chip(i, &iop13xx_irqchip3); |
232 | else | 232 | else |
233 | set_irq_chip(i, &iop13xx_irqchip4); | 233 | irq_set_chip(i, &iop13xx_irqchip4); |
234 | 234 | ||
235 | set_irq_handler(i, handle_level_irq); | 235 | irq_set_handler(i, handle_level_irq); |
236 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 236 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
237 | } | 237 | } |
238 | 238 | ||
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c index c9c02e3698bc..560d5b2dec22 100644 --- a/arch/arm/mach-iop13xx/msi.c +++ b/arch/arm/mach-iop13xx/msi.c | |||
@@ -118,7 +118,7 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) | |||
118 | 118 | ||
119 | void __init iop13xx_msi_init(void) | 119 | void __init iop13xx_msi_init(void) |
120 | { | 120 | { |
121 | set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); | 121 | irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); |
122 | } | 122 | } |
123 | 123 | ||
124 | /* | 124 | /* |
@@ -178,7 +178,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |||
178 | if (irq < 0) | 178 | if (irq < 0) |
179 | return irq; | 179 | return irq; |
180 | 180 | ||
181 | set_irq_msi(irq, desc); | 181 | irq_set_msi_desc(irq, desc); |
182 | 182 | ||
183 | msg.address_hi = 0x0; | 183 | msg.address_hi = 0x0; |
184 | msg.address_lo = IOP13XX_MU_MIMR_PCI; | 184 | msg.address_lo = IOP13XX_MU_MIMR_PCI; |
@@ -187,7 +187,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |||
187 | msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); | 187 | msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); |
188 | 188 | ||
189 | write_msi_msg(irq, &msg); | 189 | write_msi_msg(irq, &msg); |
190 | set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); | 190 | irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); |
191 | 191 | ||
192 | return 0; | 192 | return 0; |
193 | } | 193 | } |
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index d3426a120599..226604633d66 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c | |||
@@ -68,8 +68,8 @@ void __init iop32x_init_irq(void) | |||
68 | *IOP3XX_PCIIRSR = 0x0f; | 68 | *IOP3XX_PCIIRSR = 0x0f; |
69 | 69 | ||
70 | for (i = 0; i < NR_IRQS; i++) { | 70 | for (i = 0; i < NR_IRQS; i++) { |
71 | set_irq_chip(i, &ext_chip); | 71 | irq_set_chip(i, &ext_chip); |
72 | set_irq_handler(i, handle_level_irq); | 72 | irq_set_handler(i, handle_level_irq); |
73 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 73 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
74 | } | 74 | } |
75 | } | 75 | } |
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index 0ff2f74363a5..7b205e990298 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c | |||
@@ -110,8 +110,9 @@ void __init iop33x_init_irq(void) | |||
110 | *IOP3XX_PCIIRSR = 0x0f; | 110 | *IOP3XX_PCIIRSR = 0x0f; |
111 | 111 | ||
112 | for (i = 0; i < NR_IRQS; i++) { | 112 | for (i = 0; i < NR_IRQS; i++) { |
113 | set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2); | 113 | irq_set_chip(i, |
114 | set_irq_handler(i, handle_level_irq); | 114 | (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2); |
115 | irq_set_handler(i, handle_level_irq); | ||
115 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 116 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
116 | } | 117 | } |
117 | } | 118 | } |
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c index 5fc4e064b650..98956a136b94 100644 --- a/arch/arm/mach-ixp2000/core.c +++ b/arch/arm/mach-ixp2000/core.c | |||
@@ -476,8 +476,8 @@ void __init ixp2000_init_irq(void) | |||
476 | */ | 476 | */ |
477 | for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { | 477 | for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { |
478 | if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { | 478 | if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { |
479 | set_irq_chip(irq, &ixp2000_irq_chip); | 479 | irq_set_chip(irq, &ixp2000_irq_chip); |
480 | set_irq_handler(irq, handle_level_irq); | 480 | irq_set_handler(irq, handle_level_irq); |
481 | set_irq_flags(irq, IRQF_VALID); | 481 | set_irq_flags(irq, IRQF_VALID); |
482 | } else set_irq_flags(irq, 0); | 482 | } else set_irq_flags(irq, 0); |
483 | } | 483 | } |
@@ -485,21 +485,21 @@ void __init ixp2000_init_irq(void) | |||
485 | for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { | 485 | for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { |
486 | if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & | 486 | if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & |
487 | IXP2000_VALID_ERR_IRQ_MASK) { | 487 | IXP2000_VALID_ERR_IRQ_MASK) { |
488 | set_irq_chip(irq, &ixp2000_err_irq_chip); | 488 | irq_set_chip(irq, &ixp2000_err_irq_chip); |
489 | set_irq_handler(irq, handle_level_irq); | 489 | irq_set_handler(irq, handle_level_irq); |
490 | set_irq_flags(irq, IRQF_VALID); | 490 | set_irq_flags(irq, IRQF_VALID); |
491 | } | 491 | } |
492 | else | 492 | else |
493 | set_irq_flags(irq, 0); | 493 | set_irq_flags(irq, 0); |
494 | } | 494 | } |
495 | set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); | 495 | irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); |
496 | 496 | ||
497 | for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { | 497 | for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { |
498 | set_irq_chip(irq, &ixp2000_GPIO_irq_chip); | 498 | irq_set_chip(irq, &ixp2000_GPIO_irq_chip); |
499 | set_irq_handler(irq, handle_level_irq); | 499 | irq_set_handler(irq, handle_level_irq); |
500 | set_irq_flags(irq, IRQF_VALID); | 500 | set_irq_flags(irq, IRQF_VALID); |
501 | } | 501 | } |
502 | set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); | 502 | irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); |
503 | 503 | ||
504 | /* | 504 | /* |
505 | * Enable PCI irqs. The actual PCI[AB] decoding is done in | 505 | * Enable PCI irqs. The actual PCI[AB] decoding is done in |
@@ -508,8 +508,8 @@ void __init ixp2000_init_irq(void) | |||
508 | */ | 508 | */ |
509 | ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); | 509 | ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); |
510 | for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { | 510 | for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { |
511 | set_irq_chip(irq, &ixp2000_pci_irq_chip); | 511 | irq_set_chip(irq, &ixp2000_pci_irq_chip); |
512 | set_irq_handler(irq, handle_level_irq); | 512 | irq_set_handler(irq, handle_level_irq); |
513 | set_irq_flags(irq, IRQF_VALID); | 513 | set_irq_flags(irq, IRQF_VALID); |
514 | } | 514 | } |
515 | } | 515 | } |
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c index 7d90d3f13ee8..52f88648522f 100644 --- a/arch/arm/mach-ixp2000/ixdp2x00.c +++ b/arch/arm/mach-ixp2000/ixdp2x00.c | |||
@@ -158,13 +158,13 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne | |||
158 | *board_irq_mask = 0xffffffff; | 158 | *board_irq_mask = 0xffffffff; |
159 | 159 | ||
160 | for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { | 160 | for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { |
161 | set_irq_chip(irq, &ixdp2x00_cpld_irq_chip); | 161 | irq_set_chip(irq, &ixdp2x00_cpld_irq_chip); |
162 | set_irq_handler(irq, handle_level_irq); | 162 | irq_set_handler(irq, handle_level_irq); |
163 | set_irq_flags(irq, IRQF_VALID); | 163 | set_irq_flags(irq, IRQF_VALID); |
164 | } | 164 | } |
165 | 165 | ||
166 | /* Hook into PCI interrupt */ | 166 | /* Hook into PCI interrupt */ |
167 | set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); | 167 | irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); |
168 | } | 168 | } |
169 | 169 | ||
170 | /************************************************************************* | 170 | /************************************************************************* |
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c index 34b1b2af37c8..f1ff50ba6c9a 100644 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ b/arch/arm/mach-ixp2000/ixdp2x01.c | |||
@@ -115,8 +115,8 @@ void __init ixdp2x01_init_irq(void) | |||
115 | 115 | ||
116 | for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { | 116 | for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { |
117 | if (irq & valid_irq_mask) { | 117 | if (irq & valid_irq_mask) { |
118 | set_irq_chip(irq, &ixdp2x01_irq_chip); | 118 | irq_set_chip(irq, &ixdp2x01_irq_chip); |
119 | set_irq_handler(irq, handle_level_irq); | 119 | irq_set_handler(irq, handle_level_irq); |
120 | set_irq_flags(irq, IRQF_VALID); | 120 | set_irq_flags(irq, IRQF_VALID); |
121 | } else { | 121 | } else { |
122 | set_irq_flags(irq, 0); | 122 | set_irq_flags(irq, 0); |
@@ -124,7 +124,7 @@ void __init ixdp2x01_init_irq(void) | |||
124 | } | 124 | } |
125 | 125 | ||
126 | /* Hook into PCI interrupts */ | 126 | /* Hook into PCI interrupts */ |
127 | set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); | 127 | irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); |
128 | } | 128 | } |
129 | 129 | ||
130 | 130 | ||
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c index 9c8a33903216..f2039722bace 100644 --- a/arch/arm/mach-ixp23xx/core.c +++ b/arch/arm/mach-ixp23xx/core.c | |||
@@ -289,12 +289,12 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type) | |||
289 | { | 289 | { |
290 | switch (type) { | 290 | switch (type) { |
291 | case IXP23XX_IRQ_LEVEL: | 291 | case IXP23XX_IRQ_LEVEL: |
292 | set_irq_chip(irq, &ixp23xx_irq_level_chip); | 292 | irq_set_chip(irq, &ixp23xx_irq_level_chip); |
293 | set_irq_handler(irq, handle_level_irq); | 293 | irq_set_handler(irq, handle_level_irq); |
294 | break; | 294 | break; |
295 | case IXP23XX_IRQ_EDGE: | 295 | case IXP23XX_IRQ_EDGE: |
296 | set_irq_chip(irq, &ixp23xx_irq_edge_chip); | 296 | irq_set_chip(irq, &ixp23xx_irq_edge_chip); |
297 | set_irq_handler(irq, handle_edge_irq); | 297 | irq_set_handler(irq, handle_edge_irq); |
298 | break; | 298 | break; |
299 | } | 299 | } |
300 | set_irq_flags(irq, IRQF_VALID); | 300 | set_irq_flags(irq, IRQF_VALID); |
@@ -324,12 +324,12 @@ void __init ixp23xx_init_irq(void) | |||
324 | } | 324 | } |
325 | 325 | ||
326 | for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { | 326 | for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { |
327 | set_irq_chip(irq, &ixp23xx_pci_irq_chip); | 327 | irq_set_chip(irq, &ixp23xx_pci_irq_chip); |
328 | set_irq_handler(irq, handle_level_irq); | 328 | irq_set_handler(irq, handle_level_irq); |
329 | set_irq_flags(irq, IRQF_VALID); | 329 | set_irq_flags(irq, IRQF_VALID); |
330 | } | 330 | } |
331 | 331 | ||
332 | set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); | 332 | irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); |
333 | } | 333 | } |
334 | 334 | ||
335 | 335 | ||
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c index 181116aa6591..720befb0a402 100644 --- a/arch/arm/mach-ixp23xx/ixdp2351.c +++ b/arch/arm/mach-ixp23xx/ixdp2351.c | |||
@@ -136,8 +136,8 @@ void __init ixdp2351_init_irq(void) | |||
136 | irq++) { | 136 | irq++) { |
137 | if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { | 137 | if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { |
138 | set_irq_flags(irq, IRQF_VALID); | 138 | set_irq_flags(irq, IRQF_VALID); |
139 | set_irq_handler(irq, handle_level_irq); | 139 | irq_set_handler(irq, handle_level_irq); |
140 | set_irq_chip(irq, &ixdp2351_inta_chip); | 140 | irq_set_chip(irq, &ixdp2351_inta_chip); |
141 | } | 141 | } |
142 | } | 142 | } |
143 | 143 | ||
@@ -147,13 +147,13 @@ void __init ixdp2351_init_irq(void) | |||
147 | irq++) { | 147 | irq++) { |
148 | if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { | 148 | if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { |
149 | set_irq_flags(irq, IRQF_VALID); | 149 | set_irq_flags(irq, IRQF_VALID); |
150 | set_irq_handler(irq, handle_level_irq); | 150 | irq_set_handler(irq, handle_level_irq); |
151 | set_irq_chip(irq, &ixdp2351_intb_chip); | 151 | irq_set_chip(irq, &ixdp2351_intb_chip); |
152 | } | 152 | } |
153 | } | 153 | } |
154 | 154 | ||
155 | set_irq_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); | 155 | irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); |
156 | set_irq_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); | 156 | irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); |
157 | } | 157 | } |
158 | 158 | ||
159 | /* | 159 | /* |
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c index 76c61ba73218..8fe0c6273262 100644 --- a/arch/arm/mach-ixp23xx/roadrunner.c +++ b/arch/arm/mach-ixp23xx/roadrunner.c | |||
@@ -110,8 +110,8 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) | |||
110 | 110 | ||
111 | static void __init roadrunner_pci_preinit(void) | 111 | static void __init roadrunner_pci_preinit(void) |
112 | { | 112 | { |
113 | set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | 113 | irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); |
114 | set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); | 114 | irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); |
115 | 115 | ||
116 | ixp23xx_pci_preinit(); | 116 | ixp23xx_pci_preinit(); |
117 | } | 117 | } |
diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c index 845e1b500548..162043ff29ff 100644 --- a/arch/arm/mach-ixp4xx/avila-pci.c +++ b/arch/arm/mach-ixp4xx/avila-pci.c | |||
@@ -39,10 +39,10 @@ | |||
39 | 39 | ||
40 | void __init avila_pci_preinit(void) | 40 | void __init avila_pci_preinit(void) |
41 | { | 41 | { |
42 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 42 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
43 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 43 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
44 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | 44 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
45 | set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | 45 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); |
46 | ixp4xx_pci_preinit(); | 46 | ixp4xx_pci_preinit(); |
47 | } | 47 | } |
48 | 48 | ||
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 9fd894271d5d..eca559071185 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c | |||
@@ -252,8 +252,8 @@ void __init ixp4xx_init_irq(void) | |||
252 | 252 | ||
253 | /* Default to all level triggered */ | 253 | /* Default to all level triggered */ |
254 | for(i = 0; i < NR_IRQS; i++) { | 254 | for(i = 0; i < NR_IRQS; i++) { |
255 | set_irq_chip(i, &ixp4xx_irq_chip); | 255 | irq_set_chip(i, &ixp4xx_irq_chip); |
256 | set_irq_handler(i, handle_level_irq); | 256 | irq_set_handler(i, handle_level_irq); |
257 | set_irq_flags(i, IRQF_VALID); | 257 | set_irq_flags(i, IRQF_VALID); |
258 | } | 258 | } |
259 | } | 259 | } |
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index b978ea8bd6f0..37fda7d6e83d 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c | |||
@@ -32,8 +32,8 @@ | |||
32 | 32 | ||
33 | void __init coyote_pci_preinit(void) | 33 | void __init coyote_pci_preinit(void) |
34 | { | 34 | { |
35 | set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); | 35 | irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); |
36 | set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); | 36 | irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); |
37 | ixp4xx_pci_preinit(); | 37 | ixp4xx_pci_preinit(); |
38 | } | 38 | } |
39 | 39 | ||
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c index fa70fed462ba..c7612010b3fc 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-pci.c +++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c | |||
@@ -35,12 +35,12 @@ | |||
35 | 35 | ||
36 | void __init dsmg600_pci_preinit(void) | 36 | void __init dsmg600_pci_preinit(void) |
37 | { | 37 | { |
38 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 38 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
39 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 39 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
40 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | 40 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
41 | set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | 41 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); |
42 | set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); | 42 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); |
43 | set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); | 43 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); |
44 | ixp4xx_pci_preinit(); | 44 | ixp4xx_pci_preinit(); |
45 | } | 45 | } |
46 | 46 | ||
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c index 5a810c930624..44ccde9d4879 100644 --- a/arch/arm/mach-ixp4xx/fsg-pci.c +++ b/arch/arm/mach-ixp4xx/fsg-pci.c | |||
@@ -32,9 +32,9 @@ | |||
32 | 32 | ||
33 | void __init fsg_pci_preinit(void) | 33 | void __init fsg_pci_preinit(void) |
34 | { | 34 | { |
35 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 35 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
36 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 36 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
37 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | 37 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
38 | ixp4xx_pci_preinit(); | 38 | ixp4xx_pci_preinit(); |
39 | } | 39 | } |
40 | 40 | ||
diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c index 7e93a0975c4d..fc1124168874 100644 --- a/arch/arm/mach-ixp4xx/gateway7001-pci.c +++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c | |||
@@ -29,8 +29,8 @@ | |||
29 | 29 | ||
30 | void __init gateway7001_pci_preinit(void) | 30 | void __init gateway7001_pci_preinit(void) |
31 | { | 31 | { |
32 | set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); | 32 | irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); |
33 | set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); | 33 | irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); |
34 | 34 | ||
35 | ixp4xx_pci_preinit(); | 35 | ixp4xx_pci_preinit(); |
36 | } | 36 | } |
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c index d0e4861ac03d..3e8c0e33b59c 100644 --- a/arch/arm/mach-ixp4xx/goramo_mlr.c +++ b/arch/arm/mach-ixp4xx/goramo_mlr.c | |||
@@ -420,8 +420,8 @@ static void __init gmlr_init(void) | |||
420 | gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); | 420 | gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); |
421 | gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); | 421 | gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); |
422 | gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); | 422 | gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); |
423 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); | 423 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); |
424 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); | 424 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); |
425 | 425 | ||
426 | set_control(CONTROL_HSS0_DTR_N, 1); | 426 | set_control(CONTROL_HSS0_DTR_N, 1); |
427 | set_control(CONTROL_HSS1_DTR_N, 1); | 427 | set_control(CONTROL_HSS1_DTR_N, 1); |
@@ -441,10 +441,10 @@ static void __init gmlr_init(void) | |||
441 | #ifdef CONFIG_PCI | 441 | #ifdef CONFIG_PCI |
442 | static void __init gmlr_pci_preinit(void) | 442 | static void __init gmlr_pci_preinit(void) |
443 | { | 443 | { |
444 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); | 444 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); |
445 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); | 445 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); |
446 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); | 446 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); |
447 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); | 447 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); |
448 | ixp4xx_pci_preinit(); | 448 | ixp4xx_pci_preinit(); |
449 | } | 449 | } |
450 | 450 | ||
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index 25d2c333c204..38cc0725dbd8 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c | |||
@@ -43,8 +43,8 @@ | |||
43 | */ | 43 | */ |
44 | void __init gtwx5715_pci_preinit(void) | 44 | void __init gtwx5715_pci_preinit(void) |
45 | { | 45 | { |
46 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 46 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
47 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 47 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
48 | ixp4xx_pci_preinit(); | 48 | ixp4xx_pci_preinit(); |
49 | } | 49 | } |
50 | 50 | ||
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index 1ba165a6edac..58f400417eaf 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c | |||
@@ -36,10 +36,10 @@ | |||
36 | 36 | ||
37 | void __init ixdp425_pci_preinit(void) | 37 | void __init ixdp425_pci_preinit(void) |
38 | { | 38 | { |
39 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 39 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
40 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 40 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
41 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | 41 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
42 | set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | 42 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); |
43 | ixp4xx_pci_preinit(); | 43 | ixp4xx_pci_preinit(); |
44 | } | 44 | } |
45 | 45 | ||
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index 4ed7ac614920..e64f6d041488 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c | |||
@@ -25,8 +25,8 @@ | |||
25 | 25 | ||
26 | void __init ixdpg425_pci_preinit(void) | 26 | void __init ixdpg425_pci_preinit(void) |
27 | { | 27 | { |
28 | set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); | 28 | irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); |
29 | set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); | 29 | irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); |
30 | 30 | ||
31 | ixp4xx_pci_preinit(); | 31 | ixp4xx_pci_preinit(); |
32 | } | 32 | } |
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c index d0cea34cf61e..428d1202b799 100644 --- a/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/arch/arm/mach-ixp4xx/nas100d-pci.c | |||
@@ -33,11 +33,11 @@ | |||
33 | 33 | ||
34 | void __init nas100d_pci_preinit(void) | 34 | void __init nas100d_pci_preinit(void) |
35 | { | 35 | { |
36 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 36 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
37 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 37 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
38 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | 38 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
39 | set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | 39 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); |
40 | set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); | 40 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); |
41 | ixp4xx_pci_preinit(); | 41 | ixp4xx_pci_preinit(); |
42 | } | 42 | } |
43 | 43 | ||
diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c index 1eb5a90470bc..2e85f76b950d 100644 --- a/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/arch/arm/mach-ixp4xx/nslu2-pci.c | |||
@@ -32,9 +32,9 @@ | |||
32 | 32 | ||
33 | void __init nslu2_pci_preinit(void) | 33 | void __init nslu2_pci_preinit(void) |
34 | { | 34 | { |
35 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 35 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
36 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 36 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
37 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | 37 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
38 | ixp4xx_pci_preinit(); | 38 | ixp4xx_pci_preinit(); |
39 | } | 39 | } |
40 | 40 | ||
diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c index f3111c6840ef..03bdec5140a7 100644 --- a/arch/arm/mach-ixp4xx/vulcan-pci.c +++ b/arch/arm/mach-ixp4xx/vulcan-pci.c | |||
@@ -38,8 +38,8 @@ void __init vulcan_pci_preinit(void) | |||
38 | pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", | 38 | pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", |
39 | (int)(pci_cardbus_mem_size >> 20)); | 39 | (int)(pci_cardbus_mem_size >> 20)); |
40 | #endif | 40 | #endif |
41 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 41 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
42 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 42 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
43 | ixp4xx_pci_preinit(); | 43 | ixp4xx_pci_preinit(); |
44 | } | 44 | } |
45 | 45 | ||
diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c index 9b59ed03b151..17f3cf59a31b 100644 --- a/arch/arm/mach-ixp4xx/wg302v2-pci.c +++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c | |||
@@ -29,8 +29,8 @@ | |||
29 | 29 | ||
30 | void __init wg302v2_pci_preinit(void) | 30 | void __init wg302v2_pci_preinit(void) |
31 | { | 31 | { |
32 | set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); | 32 | irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); |
33 | set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); | 33 | irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); |
34 | 34 | ||
35 | ixp4xx_pci_preinit(); | 35 | ixp4xx_pci_preinit(); |
36 | } | 36 | } |
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c index cbdb5863d13b..05d193a25b25 100644 --- a/arch/arm/mach-kirkwood/irq.c +++ b/arch/arm/mach-kirkwood/irq.c | |||
@@ -35,14 +35,15 @@ void __init kirkwood_init_irq(void) | |||
35 | */ | 35 | */ |
36 | orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0, | 36 | orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0, |
37 | IRQ_KIRKWOOD_GPIO_START); | 37 | IRQ_KIRKWOOD_GPIO_START); |
38 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); | 38 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); |
39 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); | 39 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); |
40 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); | 40 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); |
41 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); | 41 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); |
42 | 42 | ||
43 | orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0, | 43 | orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0, |
44 | IRQ_KIRKWOOD_GPIO_START + 32); | 44 | IRQ_KIRKWOOD_GPIO_START + 32); |
45 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); | 45 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); |
46 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); | 46 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); |
47 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler); | 47 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, |
48 | gpio_irq_handler); | ||
48 | } | 49 | } |
diff --git a/arch/arm/mach-ks8695/gpio.c b/arch/arm/mach-ks8695/gpio.c index 55fbf7111a5b..31e456508a6f 100644 --- a/arch/arm/mach-ks8695/gpio.c +++ b/arch/arm/mach-ks8695/gpio.c | |||
@@ -80,7 +80,7 @@ int ks8695_gpio_interrupt(unsigned int pin, unsigned int type) | |||
80 | local_irq_restore(flags); | 80 | local_irq_restore(flags); |
81 | 81 | ||
82 | /* Set IRQ triggering type */ | 82 | /* Set IRQ triggering type */ |
83 | set_irq_type(gpio_irq[pin], type); | 83 | irq_set_irq_type(gpio_irq[pin], type); |
84 | 84 | ||
85 | /* enable interrupt mode */ | 85 | /* enable interrupt mode */ |
86 | ks8695_gpio_mode(pin, 0); | 86 | ks8695_gpio_mode(pin, 0); |
diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c index 7998ccaa6333..da54a5d19237 100644 --- a/arch/arm/mach-ks8695/irq.c +++ b/arch/arm/mach-ks8695/irq.c | |||
@@ -115,12 +115,12 @@ static int ks8695_irq_set_type(struct irq_data *d, unsigned int type) | |||
115 | } | 115 | } |
116 | 116 | ||
117 | if (level_triggered) { | 117 | if (level_triggered) { |
118 | set_irq_chip(d->irq, &ks8695_irq_level_chip); | 118 | irq_set_chip(d->irq, &ks8695_irq_level_chip); |
119 | set_irq_handler(d->irq, handle_level_irq); | 119 | irq_set_handler(d->irq, handle_level_irq); |
120 | } | 120 | } |
121 | else { | 121 | else { |
122 | set_irq_chip(d->irq, &ks8695_irq_edge_chip); | 122 | irq_set_chip(d->irq, &ks8695_irq_edge_chip); |
123 | set_irq_handler(d->irq, handle_edge_irq); | 123 | irq_set_handler(d->irq, handle_edge_irq); |
124 | } | 124 | } |
125 | 125 | ||
126 | __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); | 126 | __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); |
@@ -158,16 +158,16 @@ void __init ks8695_init_irq(void) | |||
158 | case KS8695_IRQ_UART_RX: | 158 | case KS8695_IRQ_UART_RX: |
159 | case KS8695_IRQ_COMM_TX: | 159 | case KS8695_IRQ_COMM_TX: |
160 | case KS8695_IRQ_COMM_RX: | 160 | case KS8695_IRQ_COMM_RX: |
161 | set_irq_chip(irq, &ks8695_irq_level_chip); | 161 | irq_set_chip(irq, &ks8695_irq_level_chip); |
162 | set_irq_handler(irq, handle_level_irq); | 162 | irq_set_handler(irq, handle_level_irq); |
163 | break; | 163 | break; |
164 | 164 | ||
165 | /* Edge-triggered interrupts */ | 165 | /* Edge-triggered interrupts */ |
166 | default: | 166 | default: |
167 | /* clear pending bit */ | 167 | /* clear pending bit */ |
168 | ks8695_irq_ack(irq_get_irq_data(irq)); | 168 | ks8695_irq_ack(irq_get_irq_data(irq)); |
169 | set_irq_chip(irq, &ks8695_irq_edge_chip); | 169 | irq_set_chip(irq, &ks8695_irq_edge_chip); |
170 | set_irq_handler(irq, handle_edge_irq); | 170 | irq_set_handler(irq, handle_edge_irq); |
171 | } | 171 | } |
172 | 172 | ||
173 | set_irq_flags(irq, IRQF_VALID); | 173 | set_irq_flags(irq, IRQF_VALID); |
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index 316ecbf6c586..3088ca328666 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c | |||
@@ -290,7 +290,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) | |||
290 | } | 290 | } |
291 | 291 | ||
292 | /* Ok to use the level handler for all types */ | 292 | /* Ok to use the level handler for all types */ |
293 | set_irq_handler(d->irq, handle_level_irq); | 293 | irq_set_handler(d->irq, handle_level_irq); |
294 | 294 | ||
295 | return 0; | 295 | return 0; |
296 | } | 296 | } |
@@ -390,8 +390,8 @@ void __init lpc32xx_init_irq(void) | |||
390 | 390 | ||
391 | /* Configure supported IRQ's */ | 391 | /* Configure supported IRQ's */ |
392 | for (i = 0; i < NR_IRQS; i++) { | 392 | for (i = 0; i < NR_IRQS; i++) { |
393 | set_irq_chip(i, &lpc32xx_irq_chip); | 393 | irq_set_chip(i, &lpc32xx_irq_chip); |
394 | set_irq_handler(i, handle_level_irq); | 394 | irq_set_handler(i, handle_level_irq); |
395 | set_irq_flags(i, IRQF_VALID); | 395 | set_irq_flags(i, IRQF_VALID); |
396 | } | 396 | } |
397 | 397 | ||
@@ -406,8 +406,8 @@ void __init lpc32xx_init_irq(void) | |||
406 | __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); | 406 | __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); |
407 | 407 | ||
408 | /* MIC SUBIRQx interrupts will route handling to the chain handlers */ | 408 | /* MIC SUBIRQx interrupts will route handling to the chain handlers */ |
409 | set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); | 409 | irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); |
410 | set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); | 410 | irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); |
411 | 411 | ||
412 | /* Initially disable all wake events */ | 412 | /* Initially disable all wake events */ |
413 | __raw_writel(0, LPC32XX_CLKPWR_P01_ER); | 413 | __raw_writel(0, LPC32XX_CLKPWR_P01_ER); |
diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c index fa037038e7b8..d21c5441a3d0 100644 --- a/arch/arm/mach-mmp/irq-mmp2.c +++ b/arch/arm/mach-mmp/irq-mmp2.c | |||
@@ -110,9 +110,9 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num) | |||
110 | if (chip->irq_ack) | 110 | if (chip->irq_ack) |
111 | chip->irq_ack(d); | 111 | chip->irq_ack(d); |
112 | 112 | ||
113 | set_irq_chip(irq, chip); | 113 | irq_set_chip(irq, chip); |
114 | set_irq_flags(irq, IRQF_VALID); | 114 | set_irq_flags(irq, IRQF_VALID); |
115 | set_irq_handler(irq, handle_level_irq); | 115 | irq_set_handler(irq, handle_level_irq); |
116 | } | 116 | } |
117 | } | 117 | } |
118 | 118 | ||
@@ -122,7 +122,7 @@ void __init mmp2_init_icu(void) | |||
122 | 122 | ||
123 | for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { | 123 | for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { |
124 | icu_mask_irq(irq_get_irq_data(irq)); | 124 | icu_mask_irq(irq_get_irq_data(irq)); |
125 | set_irq_chip(irq, &icu_irq_chip); | 125 | irq_set_chip(irq, &icu_irq_chip); |
126 | set_irq_flags(irq, IRQF_VALID); | 126 | set_irq_flags(irq, IRQF_VALID); |
127 | 127 | ||
128 | switch (irq) { | 128 | switch (irq) { |
@@ -133,7 +133,7 @@ void __init mmp2_init_icu(void) | |||
133 | case IRQ_MMP2_SSP_MUX: | 133 | case IRQ_MMP2_SSP_MUX: |
134 | break; | 134 | break; |
135 | default: | 135 | default: |
136 | set_irq_handler(irq, handle_level_irq); | 136 | irq_set_handler(irq, handle_level_irq); |
137 | break; | 137 | break; |
138 | } | 138 | } |
139 | } | 139 | } |
@@ -149,9 +149,9 @@ void __init mmp2_init_icu(void) | |||
149 | init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); | 149 | init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); |
150 | init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); | 150 | init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); |
151 | 151 | ||
152 | set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); | 152 | irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); |
153 | set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); | 153 | irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); |
154 | set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); | 154 | irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); |
155 | set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); | 155 | irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); |
156 | set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); | 156 | irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); |
157 | } | 157 | } |
diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c index f86b450cb93c..6a8676205e6e 100644 --- a/arch/arm/mach-mmp/irq-pxa168.c +++ b/arch/arm/mach-mmp/irq-pxa168.c | |||
@@ -48,8 +48,8 @@ void __init icu_init_irq(void) | |||
48 | 48 | ||
49 | for (irq = 0; irq < 64; irq++) { | 49 | for (irq = 0; irq < 64; irq++) { |
50 | icu_mask_irq(irq_get_irq_data(irq)); | 50 | icu_mask_irq(irq_get_irq_data(irq)); |
51 | set_irq_chip(irq, &icu_irq_chip); | 51 | irq_set_chip(irq, &icu_irq_chip); |
52 | set_irq_handler(irq, handle_level_irq); | 52 | irq_set_handler(irq, handle_level_irq); |
53 | set_irq_flags(irq, IRQF_VALID); | 53 | set_irq_flags(irq, IRQF_VALID); |
54 | } | 54 | } |
55 | } | 55 | } |
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c index 1993721d472e..35c7ceeb3f29 100644 --- a/arch/arm/mach-msm/board-msm8960.c +++ b/arch/arm/mach-msm/board-msm8960.c | |||
@@ -53,7 +53,7 @@ static void __init msm8960_init_irq(void) | |||
53 | */ | 53 | */ |
54 | for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { | 54 | for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { |
55 | if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) | 55 | if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) |
56 | set_irq_handler(i, handle_percpu_irq); | 56 | irq_set_handler(i, handle_percpu_irq); |
57 | } | 57 | } |
58 | } | 58 | } |
59 | 59 | ||
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index b3c55f138fce..1163b6fd05d2 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c | |||
@@ -56,7 +56,7 @@ static void __init msm8x60_init_irq(void) | |||
56 | */ | 56 | */ |
57 | for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { | 57 | for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { |
58 | if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) | 58 | if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) |
59 | set_irq_handler(i, handle_percpu_irq); | 59 | irq_set_handler(i, handle_percpu_irq); |
60 | } | 60 | } |
61 | } | 61 | } |
62 | 62 | ||
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c index 31117a4499c4..ffcd4f3c63ee 100644 --- a/arch/arm/mach-msm/board-trout-gpio.c +++ b/arch/arm/mach-msm/board-trout-gpio.c | |||
@@ -214,17 +214,17 @@ int __init trout_init_gpio(void) | |||
214 | { | 214 | { |
215 | int i; | 215 | int i; |
216 | for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) { | 216 | for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) { |
217 | set_irq_chip(i, &trout_gpio_irq_chip); | 217 | irq_set_chip(i, &trout_gpio_irq_chip); |
218 | set_irq_handler(i, handle_edge_irq); | 218 | irq_set_handler(i, handle_edge_irq); |
219 | set_irq_flags(i, IRQF_VALID); | 219 | set_irq_flags(i, IRQF_VALID); |
220 | } | 220 | } |
221 | 221 | ||
222 | for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) | 222 | for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) |
223 | gpiochip_add(&msm_gpio_banks[i].chip); | 223 | gpiochip_add(&msm_gpio_banks[i].chip); |
224 | 224 | ||
225 | set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); | 225 | irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); |
226 | set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); | 226 | irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); |
227 | set_irq_wake(MSM_GPIO_TO_INT(17), 1); | 227 | irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1); |
228 | 228 | ||
229 | return 0; | 229 | return 0; |
230 | } | 230 | } |
diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout-mmc.c index 44be8464657b..f7a9724788b0 100644 --- a/arch/arm/mach-msm/board-trout-mmc.c +++ b/arch/arm/mach-msm/board-trout-mmc.c | |||
@@ -174,7 +174,7 @@ int __init trout_init_mmc(unsigned int sys_rev) | |||
174 | if (IS_ERR(vreg_sdslot)) | 174 | if (IS_ERR(vreg_sdslot)) |
175 | return PTR_ERR(vreg_sdslot); | 175 | return PTR_ERR(vreg_sdslot); |
176 | 176 | ||
177 | set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); | 177 | irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); |
178 | 178 | ||
179 | if (!opt_disable_sdcard) | 179 | if (!opt_disable_sdcard) |
180 | msm_add_sdcc(2, &trout_sdslot_data, | 180 | msm_add_sdcc(2, &trout_sdslot_data, |
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c index e00e4dee4274..997ded1270bf 100644 --- a/arch/arm/mach-msm/gpio-v2.c +++ b/arch/arm/mach-msm/gpio-v2.c | |||
@@ -328,12 +328,12 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |||
328 | 328 | ||
329 | if (on) { | 329 | if (on) { |
330 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) | 330 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) |
331 | set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); | 331 | irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); |
332 | set_bit(gpio, msm_gpio.wake_irqs); | 332 | set_bit(gpio, msm_gpio.wake_irqs); |
333 | } else { | 333 | } else { |
334 | clear_bit(gpio, msm_gpio.wake_irqs); | 334 | clear_bit(gpio, msm_gpio.wake_irqs); |
335 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) | 335 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) |
336 | set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); | 336 | irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); |
337 | } | 337 | } |
338 | 338 | ||
339 | return 0; | 339 | return 0; |
@@ -362,12 +362,12 @@ static int __devinit msm_gpio_probe(struct platform_device *dev) | |||
362 | 362 | ||
363 | for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { | 363 | for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { |
364 | irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); | 364 | irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); |
365 | set_irq_chip(irq, &msm_gpio_irq_chip); | 365 | irq_set_chip(irq, &msm_gpio_irq_chip); |
366 | set_irq_handler(irq, handle_level_irq); | 366 | irq_set_handler(irq, handle_level_irq); |
367 | set_irq_flags(irq, IRQF_VALID); | 367 | set_irq_flags(irq, IRQF_VALID); |
368 | } | 368 | } |
369 | 369 | ||
370 | set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, | 370 | irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ, |
371 | msm_summary_irq_handler); | 371 | msm_summary_irq_handler); |
372 | return 0; | 372 | return 0; |
373 | } | 373 | } |
@@ -379,7 +379,7 @@ static int __devexit msm_gpio_remove(struct platform_device *dev) | |||
379 | if (ret < 0) | 379 | if (ret < 0) |
380 | return ret; | 380 | return ret; |
381 | 381 | ||
382 | set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); | 382 | irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); |
383 | 383 | ||
384 | return 0; | 384 | return 0; |
385 | } | 385 | } |
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index 448f2677051b..c9e0c616545c 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c | |||
@@ -354,9 +354,9 @@ static int __init msm_init_gpio(void) | |||
354 | msm_gpio_chips[j].chip.base + | 354 | msm_gpio_chips[j].chip.base + |
355 | msm_gpio_chips[j].chip.ngpio) | 355 | msm_gpio_chips[j].chip.ngpio) |
356 | j++; | 356 | j++; |
357 | set_irq_chip_data(i, &msm_gpio_chips[j]); | 357 | irq_set_chip_data(i, &msm_gpio_chips[j]); |
358 | set_irq_chip(i, &msm_gpio_irq_chip); | 358 | irq_set_chip(i, &msm_gpio_irq_chip); |
359 | set_irq_handler(i, handle_edge_irq); | 359 | irq_set_handler(i, handle_edge_irq); |
360 | set_irq_flags(i, IRQF_VALID); | 360 | set_irq_flags(i, IRQF_VALID); |
361 | } | 361 | } |
362 | 362 | ||
@@ -366,10 +366,10 @@ static int __init msm_init_gpio(void) | |||
366 | gpiochip_add(&msm_gpio_chips[i].chip); | 366 | gpiochip_add(&msm_gpio_chips[i].chip); |
367 | } | 367 | } |
368 | 368 | ||
369 | set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); | 369 | irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); |
370 | set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); | 370 | irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); |
371 | set_irq_wake(INT_GPIO_GROUP1, 1); | 371 | irq_set_irq_wake(INT_GPIO_GROUP1, 1); |
372 | set_irq_wake(INT_GPIO_GROUP2, 2); | 372 | irq_set_irq_wake(INT_GPIO_GROUP2, 2); |
373 | return 0; | 373 | return 0; |
374 | } | 374 | } |
375 | 375 | ||
diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c index 84b8103b4686..7a805bec32af 100644 --- a/arch/arm/mach-msm/irq-vic.c +++ b/arch/arm/mach-msm/irq-vic.c | |||
@@ -357,8 +357,8 @@ void __init msm_init_irq(void) | |||
357 | writel(3, VIC_INT_MASTEREN); | 357 | writel(3, VIC_INT_MASTEREN); |
358 | 358 | ||
359 | for (n = 0; n < NR_MSM_IRQS; n++) { | 359 | for (n = 0; n < NR_MSM_IRQS; n++) { |
360 | set_irq_chip(n, &msm_irq_chip); | 360 | irq_set_chip(n, &msm_irq_chip); |
361 | set_irq_handler(n, handle_level_irq); | 361 | irq_set_handler(n, handle_level_irq); |
362 | set_irq_flags(n, IRQF_VALID); | 362 | set_irq_flags(n, IRQF_VALID); |
363 | } | 363 | } |
364 | } | 364 | } |
diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c index 8033c6aab974..782e8054539e 100644 --- a/arch/arm/mach-msm/irq.c +++ b/arch/arm/mach-msm/irq.c | |||
@@ -145,8 +145,8 @@ void __init msm_init_irq(void) | |||
145 | writel(1, VIC_INT_MASTEREN); | 145 | writel(1, VIC_INT_MASTEREN); |
146 | 146 | ||
147 | for (n = 0; n < NR_MSM_IRQS; n++) { | 147 | for (n = 0; n < NR_MSM_IRQS; n++) { |
148 | set_irq_chip(n, &msm_irq_chip); | 148 | irq_set_chip(n, &msm_irq_chip); |
149 | set_irq_handler(n, handle_level_irq); | 149 | irq_set_handler(n, handle_level_irq); |
150 | set_irq_flags(n, IRQF_VALID); | 150 | set_irq_flags(n, IRQF_VALID); |
151 | } | 151 | } |
152 | } | 152 | } |
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c index cfab1c472fbc..276f91899ff3 100644 --- a/arch/arm/mach-msm/sirc.c +++ b/arch/arm/mach-msm/sirc.c | |||
@@ -158,15 +158,15 @@ void __init msm_init_sirc(void) | |||
158 | wake_enable = 0; | 158 | wake_enable = 0; |
159 | 159 | ||
160 | for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) { | 160 | for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) { |
161 | set_irq_chip(i, &sirc_irq_chip); | 161 | irq_set_chip(i, &sirc_irq_chip); |
162 | set_irq_handler(i, handle_edge_irq); | 162 | irq_set_handler(i, handle_edge_irq); |
163 | set_irq_flags(i, IRQF_VALID); | 163 | set_irq_flags(i, IRQF_VALID); |
164 | } | 164 | } |
165 | 165 | ||
166 | for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) { | 166 | for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) { |
167 | set_irq_chained_handler(sirc_reg_table[i].cascade_irq, | 167 | irq_set_chained_handler(sirc_reg_table[i].cascade_irq, |
168 | sirc_irq_handler); | 168 | sirc_irq_handler); |
169 | set_irq_wake(sirc_reg_table[i].cascade_irq, 1); | 169 | irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1); |
170 | } | 170 | } |
171 | return; | 171 | return; |
172 | } | 172 | } |
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 08da497c39c2..3e24431bb5ea 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c | |||
@@ -38,8 +38,8 @@ void __init mv78xx0_init_irq(void) | |||
38 | orion_gpio_init(0, 32, GPIO_VIRT_BASE, | 38 | orion_gpio_init(0, 32, GPIO_VIRT_BASE, |
39 | mv78xx0_core_index() ? 0x18 : 0, | 39 | mv78xx0_core_index() ? 0x18 : 0, |
40 | IRQ_MV78XX0_GPIO_START); | 40 | IRQ_MV78XX0_GPIO_START); |
41 | set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); | 41 | irq_set_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); |
42 | set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); | 42 | irq_set_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); |
43 | set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); | 43 | irq_set_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); |
44 | set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); | 44 | irq_set_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); |
45 | } | 45 | } |
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index 4e4b780c481d..de494525ec7e 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c | |||
@@ -199,12 +199,12 @@ static void __init mx31ads_init_expio(void) | |||
199 | __raw_writew(0xFFFF, PBC_INTSTATUS_REG); | 199 | __raw_writew(0xFFFF, PBC_INTSTATUS_REG); |
200 | for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); | 200 | for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); |
201 | i++) { | 201 | i++) { |
202 | set_irq_chip(i, &expio_irq_chip); | 202 | irq_set_chip(i, &expio_irq_chip); |
203 | set_irq_handler(i, handle_level_irq); | 203 | irq_set_handler(i, handle_level_irq); |
204 | set_irq_flags(i, IRQF_VALID); | 204 | set_irq_flags(i, IRQF_VALID); |
205 | } | 205 | } |
206 | set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); | 206 | irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); |
207 | set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); | 207 | irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); |
208 | } | 208 | } |
209 | 209 | ||
210 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 | 210 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 |
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index e83ffadb65f8..4a8550529b04 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c | |||
@@ -212,7 +212,7 @@ void __init eukrea_mbimx51_baseboard_init(void) | |||
212 | 212 | ||
213 | gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); | 213 | gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); |
214 | gpio_direction_input(MBIMX51_TSC2007_GPIO); | 214 | gpio_direction_input(MBIMX51_TSC2007_GPIO); |
215 | set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); | 215 | irq_set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); |
216 | i2c_register_board_info(1, mbimx51_i2c_devices, | 216 | i2c_register_board_info(1, mbimx51_i2c_devices, |
217 | ARRAY_SIZE(mbimx51_i2c_devices)); | 217 | ARRAY_SIZE(mbimx51_i2c_devices)); |
218 | 218 | ||
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c index 56fa2ed15222..a1e01dd4a4ff 100644 --- a/arch/arm/mach-mxs/gpio.c +++ b/arch/arm/mach-mxs/gpio.c | |||
@@ -136,7 +136,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type) | |||
136 | static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) | 136 | static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) |
137 | { | 137 | { |
138 | u32 irq_stat; | 138 | u32 irq_stat; |
139 | struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq); | 139 | struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq); |
140 | u32 gpio_irq_no_base = port->virtual_irq_start; | 140 | u32 gpio_irq_no_base = port->virtual_irq_start; |
141 | 141 | ||
142 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 142 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
@@ -265,14 +265,14 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt) | |||
265 | 265 | ||
266 | for (j = port[i].virtual_irq_start; | 266 | for (j = port[i].virtual_irq_start; |
267 | j < port[i].virtual_irq_start + 32; j++) { | 267 | j < port[i].virtual_irq_start + 32; j++) { |
268 | set_irq_chip(j, &gpio_irq_chip); | 268 | irq_set_chip(j, &gpio_irq_chip); |
269 | set_irq_handler(j, handle_level_irq); | 269 | irq_set_handler(j, handle_level_irq); |
270 | set_irq_flags(j, IRQF_VALID); | 270 | set_irq_flags(j, IRQF_VALID); |
271 | } | 271 | } |
272 | 272 | ||
273 | /* setup one handler for each entry */ | 273 | /* setup one handler for each entry */ |
274 | set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler); | 274 | irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler); |
275 | set_irq_data(port[i].irq, &port[i]); | 275 | irq_set_handler_data(port[i].irq, &port[i]); |
276 | 276 | ||
277 | /* register gpio chip */ | 277 | /* register gpio chip */ |
278 | port[i].chip.direction_input = mxs_gpio_direction_input; | 278 | port[i].chip.direction_input = mxs_gpio_direction_input; |
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c index 0f4c120fc169..ae8a0d98f995 100644 --- a/arch/arm/mach-mxs/icoll.c +++ b/arch/arm/mach-mxs/icoll.c | |||
@@ -74,8 +74,8 @@ void __init icoll_init_irq(void) | |||
74 | mxs_reset_block(icoll_base + HW_ICOLL_CTRL); | 74 | mxs_reset_block(icoll_base + HW_ICOLL_CTRL); |
75 | 75 | ||
76 | for (i = 0; i < MXS_INTERNAL_IRQS; i++) { | 76 | for (i = 0; i < MXS_INTERNAL_IRQS; i++) { |
77 | set_irq_chip(i, &mxs_icoll_chip); | 77 | irq_set_chip(i, &mxs_icoll_chip); |
78 | set_irq_handler(i, handle_level_irq); | 78 | irq_set_handler(i, handle_level_irq); |
79 | set_irq_flags(i, IRQF_VALID); | 79 | set_irq_flags(i, IRQF_VALID); |
80 | } | 80 | } |
81 | } | 81 | } |
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c index 29ffa750fbe6..783e327892dc 100644 --- a/arch/arm/mach-netx/generic.c +++ b/arch/arm/mach-netx/generic.c | |||
@@ -171,13 +171,13 @@ void __init netx_init_irq(void) | |||
171 | vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); | 171 | vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); |
172 | 172 | ||
173 | for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { | 173 | for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { |
174 | set_irq_chip(irq, &netx_hif_chip); | 174 | irq_set_chip(irq, &netx_hif_chip); |
175 | set_irq_handler(irq, handle_level_irq); | 175 | irq_set_handler(irq, handle_level_irq); |
176 | set_irq_flags(irq, IRQF_VALID); | 176 | set_irq_flags(irq, IRQF_VALID); |
177 | } | 177 | } |
178 | 178 | ||
179 | writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); | 179 | writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); |
180 | set_irq_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler); | 180 | irq_set_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler); |
181 | } | 181 | } |
182 | 182 | ||
183 | static int __init netx_init(void) | 183 | static int __init netx_init(void) |
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c index 0c0d5248c368..7e29e4ae03ee 100644 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c | |||
@@ -107,8 +107,8 @@ void __init board_a9m9750dev_init_irq(void) | |||
107 | __func__); | 107 | __func__); |
108 | 108 | ||
109 | for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { | 109 | for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { |
110 | set_irq_chip(i, &a9m9750dev_fpga_chip); | 110 | irq_set_chip(i, &a9m9750dev_fpga_chip); |
111 | set_irq_handler(i, handle_level_irq); | 111 | irq_set_handler(i, handle_level_irq); |
112 | set_irq_flags(i, IRQF_VALID); | 112 | set_irq_flags(i, IRQF_VALID); |
113 | } | 113 | } |
114 | 114 | ||
@@ -118,8 +118,8 @@ void __init board_a9m9750dev_init_irq(void) | |||
118 | REGSET(eic, SYS_EIC, LVEDG, LEVEL); | 118 | REGSET(eic, SYS_EIC, LVEDG, LEVEL); |
119 | __raw_writel(eic, SYS_EIC(2)); | 119 | __raw_writel(eic, SYS_EIC(2)); |
120 | 120 | ||
121 | set_irq_chained_handler(IRQ_NS9XXX_EXT2, | 121 | irq_set_chained_handler(IRQ_NS9XXX_EXT2, |
122 | a9m9750dev_fpga_demux_handler); | 122 | a9m9750dev_fpga_demux_handler); |
123 | } | 123 | } |
124 | 124 | ||
125 | void __init board_a9m9750dev_init_machine(void) | 125 | void __init board_a9m9750dev_init_machine(void) |
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c index bf0fd48cbd80..14997e9fdb7a 100644 --- a/arch/arm/mach-ns9xxx/irq.c +++ b/arch/arm/mach-ns9xxx/irq.c | |||
@@ -67,8 +67,8 @@ void __init ns9xxx_init_irq(void) | |||
67 | __raw_writel(prio2irq(i), SYS_IVA(i)); | 67 | __raw_writel(prio2irq(i), SYS_IVA(i)); |
68 | 68 | ||
69 | for (i = 0; i <= 31; ++i) { | 69 | for (i = 0; i <= 31; ++i) { |
70 | set_irq_chip(i, &ns9xxx_chip); | 70 | irq_set_chip(i, &ns9xxx_chip); |
71 | set_irq_handler(i, handle_fasteoi_irq); | 71 | irq_set_handler(i, handle_fasteoi_irq); |
72 | set_irq_flags(i, IRQF_VALID); | 72 | set_irq_flags(i, IRQF_VALID); |
73 | irq_set_status_flags(i, IRQ_LEVEL); | 73 | irq_set_status_flags(i, IRQ_LEVEL); |
74 | } | 74 | } |
diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c index 1f8a05a22834..fcf1212d9706 100644 --- a/arch/arm/mach-nuc93x/irq.c +++ b/arch/arm/mach-nuc93x/irq.c | |||
@@ -59,8 +59,8 @@ void __init nuc93x_init_irq(void) | |||
59 | __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); | 59 | __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); |
60 | 60 | ||
61 | for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) { | 61 | for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) { |
62 | set_irq_chip(irqno, &nuc93x_irq_chip); | 62 | irq_set_chip(irqno, &nuc93x_irq_chip); |
63 | set_irq_handler(irqno, handle_level_irq); | 63 | irq_set_handler(irqno, handle_level_irq); |
64 | set_irq_flags(irqno, IRQF_VALID); | 64 | set_irq_flags(irqno, IRQF_VALID); |
65 | } | 65 | } |
66 | } | 66 | } |
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 7c5e2112c776..e68dfde1918e 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
@@ -276,7 +276,7 @@ static void __init osk_init_cf(void) | |||
276 | return; | 276 | return; |
277 | } | 277 | } |
278 | /* the CF I/O IRQ is really active-low */ | 278 | /* the CF I/O IRQ is really active-low */ |
279 | set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); | 279 | irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); |
280 | } | 280 | } |
281 | 281 | ||
282 | static void __init osk_init_irq(void) | 282 | static void __init osk_init_irq(void) |
@@ -482,7 +482,7 @@ static void __init osk_mistral_init(void) | |||
482 | omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ | 482 | omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ |
483 | gpio_request(4, "ts_int"); | 483 | gpio_request(4, "ts_int"); |
484 | gpio_direction_input(4); | 484 | gpio_direction_input(4); |
485 | set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); | 485 | irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); |
486 | 486 | ||
487 | spi_register_board_info(mistral_boardinfo, | 487 | spi_register_board_info(mistral_boardinfo, |
488 | ARRAY_SIZE(mistral_boardinfo)); | 488 | ARRAY_SIZE(mistral_boardinfo)); |
@@ -500,7 +500,7 @@ static void __init osk_mistral_init(void) | |||
500 | int irq = gpio_to_irq(OMAP_MPUIO(2)); | 500 | int irq = gpio_to_irq(OMAP_MPUIO(2)); |
501 | 501 | ||
502 | gpio_direction_input(OMAP_MPUIO(2)); | 502 | gpio_direction_input(OMAP_MPUIO(2)); |
503 | set_irq_type(irq, IRQ_TYPE_EDGE_RISING); | 503 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); |
504 | #ifdef CONFIG_PM | 504 | #ifdef CONFIG_PM |
505 | /* share the IRQ in case someone wants to use the | 505 | /* share the IRQ in case someone wants to use the |
506 | * button for more than wakeup from system sleep. | 506 | * button for more than wakeup from system sleep. |
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index d7bbbe721a75..45f01d2c3a7a 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c | |||
@@ -256,12 +256,12 @@ palmz71_powercable(int irq, void *dev_id) | |||
256 | { | 256 | { |
257 | if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) { | 257 | if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) { |
258 | printk(KERN_INFO "PM: Power cable connected\n"); | 258 | printk(KERN_INFO "PM: Power cable connected\n"); |
259 | set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), | 259 | irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), |
260 | IRQ_TYPE_EDGE_FALLING); | 260 | IRQ_TYPE_EDGE_FALLING); |
261 | } else { | 261 | } else { |
262 | printk(KERN_INFO "PM: Power cable disconnected\n"); | 262 | printk(KERN_INFO "PM: Power cable disconnected\n"); |
263 | set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), | 263 | irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), |
264 | IRQ_TYPE_EDGE_RISING); | 264 | IRQ_TYPE_EDGE_RISING); |
265 | } | 265 | } |
266 | return IRQ_HANDLED; | 266 | return IRQ_HANDLED; |
267 | } | 267 | } |
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index bdc0ac8dc21f..65d24204937a 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c | |||
@@ -279,10 +279,10 @@ static void __init voiceblue_init(void) | |||
279 | gpio_request(13, "16C554 irq"); | 279 | gpio_request(13, "16C554 irq"); |
280 | gpio_request(14, "16C554 irq"); | 280 | gpio_request(14, "16C554 irq"); |
281 | gpio_request(15, "16C554 irq"); | 281 | gpio_request(15, "16C554 irq"); |
282 | set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); | 282 | irq_set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); |
283 | set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); | 283 | irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); |
284 | set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); | 284 | irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); |
285 | set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); | 285 | irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); |
286 | 286 | ||
287 | platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); | 287 | platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); |
288 | omap_board_config = voiceblue_config; | 288 | omap_board_config = voiceblue_config; |
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 0ace7998aaa5..cddbf8b089ce 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c | |||
@@ -156,17 +156,17 @@ void omap1510_fpga_init_irq(void) | |||
156 | * The touchscreen interrupt is level-sensitive, so | 156 | * The touchscreen interrupt is level-sensitive, so |
157 | * we'll use the regular mask_ack routine for it. | 157 | * we'll use the regular mask_ack routine for it. |
158 | */ | 158 | */ |
159 | set_irq_chip(i, &omap_fpga_irq_ack); | 159 | irq_set_chip(i, &omap_fpga_irq_ack); |
160 | } | 160 | } |
161 | else { | 161 | else { |
162 | /* | 162 | /* |
163 | * All FPGA interrupts except the touchscreen are | 163 | * All FPGA interrupts except the touchscreen are |
164 | * edge-sensitive, so we won't mask them. | 164 | * edge-sensitive, so we won't mask them. |
165 | */ | 165 | */ |
166 | set_irq_chip(i, &omap_fpga_irq); | 166 | irq_set_chip(i, &omap_fpga_irq); |
167 | } | 167 | } |
168 | 168 | ||
169 | set_irq_handler(i, handle_edge_irq); | 169 | irq_set_handler(i, handle_edge_irq); |
170 | set_irq_flags(i, IRQF_VALID); | 170 | set_irq_flags(i, IRQF_VALID); |
171 | } | 171 | } |
172 | 172 | ||
@@ -183,6 +183,6 @@ void omap1510_fpga_init_irq(void) | |||
183 | return; | 183 | return; |
184 | } | 184 | } |
185 | gpio_direction_input(13); | 185 | gpio_direction_input(13); |
186 | set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); | 186 | irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); |
187 | set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); | 187 | irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); |
188 | } | 188 | } |
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 731dd33bff51..53dbb5d7efdc 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c | |||
@@ -230,8 +230,8 @@ void __init omap_init_irq(void) | |||
230 | irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); | 230 | irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); |
231 | omap_irq_set_cfg(j, 0, 0, irq_trigger); | 231 | omap_irq_set_cfg(j, 0, 0, irq_trigger); |
232 | 232 | ||
233 | set_irq_chip(j, &omap_irq_chip); | 233 | irq_set_chip(j, &omap_irq_chip); |
234 | set_irq_handler(j, handle_level_irq); | 234 | irq_set_handler(j, handle_level_irq); |
235 | set_irq_flags(j, IRQF_VALID); | 235 | set_irq_flags(j, IRQF_VALID); |
236 | } | 236 | } |
237 | } | 237 | } |
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 493505c3b2f5..130034bf01d5 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
@@ -743,7 +743,7 @@ static int __init gpmc_init(void) | |||
743 | /* initalize the irq_chained */ | 743 | /* initalize the irq_chained */ |
744 | irq = OMAP_GPMC_IRQ_BASE; | 744 | irq = OMAP_GPMC_IRQ_BASE; |
745 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | 745 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { |
746 | set_irq_chip_and_handler(irq, &dummy_irq_chip, | 746 | irq_set_chip_and_handler(irq, &dummy_irq_chip, |
747 | handle_simple_irq); | 747 | handle_simple_irq); |
748 | set_irq_flags(irq, IRQF_VALID); | 748 | set_irq_flags(irq, IRQF_VALID); |
749 | irq++; | 749 | irq++; |
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index bc524b94fd59..4fff5e3270d8 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c | |||
@@ -223,8 +223,8 @@ void __init omap_init_irq(void) | |||
223 | nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); | 223 | nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); |
224 | 224 | ||
225 | for (i = 0; i < nr_of_irqs; i++) { | 225 | for (i = 0; i < nr_of_irqs; i++) { |
226 | set_irq_chip(i, &omap_irq_chip); | 226 | irq_set_chip(i, &omap_irq_chip); |
227 | set_irq_handler(i, handle_level_irq); | 227 | irq_set_handler(i, handle_level_irq); |
228 | set_irq_flags(i, IRQF_VALID); | 228 | set_irq_flags(i, IRQF_VALID); |
229 | } | 229 | } |
230 | } | 230 | } |
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index c10a11715376..b7d4591214e0 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c | |||
@@ -213,7 +213,7 @@ void __init db88f5281_pci_preinit(void) | |||
213 | pin = DB88F5281_PCI_SLOT0_IRQ_PIN; | 213 | pin = DB88F5281_PCI_SLOT0_IRQ_PIN; |
214 | if (gpio_request(pin, "PCI Int1") == 0) { | 214 | if (gpio_request(pin, "PCI Int1") == 0) { |
215 | if (gpio_direction_input(pin) == 0) { | 215 | if (gpio_direction_input(pin) == 0) { |
216 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 216 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
217 | } else { | 217 | } else { |
218 | printk(KERN_ERR "db88f5281_pci_preinit faield to " | 218 | printk(KERN_ERR "db88f5281_pci_preinit faield to " |
219 | "set_irq_type pin %d\n", pin); | 219 | "set_irq_type pin %d\n", pin); |
@@ -226,7 +226,7 @@ void __init db88f5281_pci_preinit(void) | |||
226 | pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; | 226 | pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; |
227 | if (gpio_request(pin, "PCI Int2") == 0) { | 227 | if (gpio_request(pin, "PCI Int2") == 0) { |
228 | if (gpio_direction_input(pin) == 0) { | 228 | if (gpio_direction_input(pin) == 0) { |
229 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 229 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
230 | } else { | 230 | } else { |
231 | printk(KERN_ERR "db88f5281_pci_preinit faield " | 231 | printk(KERN_ERR "db88f5281_pci_preinit faield " |
232 | "to set_irq_type pin %d\n", pin); | 232 | "to set_irq_type pin %d\n", pin); |
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index ed85891f8699..43cf8bc9767b 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c | |||
@@ -34,8 +34,8 @@ void __init orion5x_init_irq(void) | |||
34 | * Initialize gpiolib for GPIOs 0-31. | 34 | * Initialize gpiolib for GPIOs 0-31. |
35 | */ | 35 | */ |
36 | orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START); | 36 | orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START); |
37 | set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); | 37 | irq_set_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); |
38 | set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); | 38 | irq_set_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); |
39 | set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); | 39 | irq_set_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); |
40 | set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); | 40 | irq_set_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); |
41 | } | 41 | } |
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 67ec6959b267..4fc46772a087 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c | |||
@@ -148,7 +148,7 @@ void __init rd88f5182_pci_preinit(void) | |||
148 | pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; | 148 | pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; |
149 | if (gpio_request(pin, "PCI IntA") == 0) { | 149 | if (gpio_request(pin, "PCI IntA") == 0) { |
150 | if (gpio_direction_input(pin) == 0) { | 150 | if (gpio_direction_input(pin) == 0) { |
151 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 151 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
152 | } else { | 152 | } else { |
153 | printk(KERN_ERR "rd88f5182_pci_preinit faield to " | 153 | printk(KERN_ERR "rd88f5182_pci_preinit faield to " |
154 | "set_irq_type pin %d\n", pin); | 154 | "set_irq_type pin %d\n", pin); |
@@ -161,7 +161,7 @@ void __init rd88f5182_pci_preinit(void) | |||
161 | pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; | 161 | pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; |
162 | if (gpio_request(pin, "PCI IntB") == 0) { | 162 | if (gpio_request(pin, "PCI IntB") == 0) { |
163 | if (gpio_direction_input(pin) == 0) { | 163 | if (gpio_direction_input(pin) == 0) { |
164 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 164 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
165 | } else { | 165 | } else { |
166 | printk(KERN_ERR "rd88f5182_pci_preinit faield to " | 166 | printk(KERN_ERR "rd88f5182_pci_preinit faield to " |
167 | "set_irq_type pin %d\n", pin); | 167 | "set_irq_type pin %d\n", pin); |
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index 5653ee6c71d8..616004143912 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c | |||
@@ -88,7 +88,7 @@ void __init tsp2_pci_preinit(void) | |||
88 | pin = TSP2_PCI_SLOT0_IRQ_PIN; | 88 | pin = TSP2_PCI_SLOT0_IRQ_PIN; |
89 | if (gpio_request(pin, "PCI Int1") == 0) { | 89 | if (gpio_request(pin, "PCI Int1") == 0) { |
90 | if (gpio_direction_input(pin) == 0) { | 90 | if (gpio_direction_input(pin) == 0) { |
91 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 91 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
92 | } else { | 92 | } else { |
93 | printk(KERN_ERR "tsp2_pci_preinit failed " | 93 | printk(KERN_ERR "tsp2_pci_preinit failed " |
94 | "to set_irq_type pin %d\n", pin); | 94 | "to set_irq_type pin %d\n", pin); |
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 8bbd27ea6735..f0f43e13ac87 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c | |||
@@ -117,7 +117,7 @@ void __init qnap_ts209_pci_preinit(void) | |||
117 | pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; | 117 | pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; |
118 | if (gpio_request(pin, "PCI Int1") == 0) { | 118 | if (gpio_request(pin, "PCI Int1") == 0) { |
119 | if (gpio_direction_input(pin) == 0) { | 119 | if (gpio_direction_input(pin) == 0) { |
120 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 120 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
121 | } else { | 121 | } else { |
122 | printk(KERN_ERR "qnap_ts209_pci_preinit failed to " | 122 | printk(KERN_ERR "qnap_ts209_pci_preinit failed to " |
123 | "set_irq_type pin %d\n", pin); | 123 | "set_irq_type pin %d\n", pin); |
@@ -131,7 +131,7 @@ void __init qnap_ts209_pci_preinit(void) | |||
131 | pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; | 131 | pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; |
132 | if (gpio_request(pin, "PCI Int2") == 0) { | 132 | if (gpio_request(pin, "PCI Int2") == 0) { |
133 | if (gpio_direction_input(pin) == 0) { | 133 | if (gpio_direction_input(pin) == 0) { |
134 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 134 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
135 | } else { | 135 | } else { |
136 | printk(KERN_ERR "qnap_ts209_pci_preinit failed " | 136 | printk(KERN_ERR "qnap_ts209_pci_preinit failed " |
137 | "to set_irq_type pin %d\n", pin); | 137 | "to set_irq_type pin %d\n", pin); |
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c index c69c180aec76..7608c7a288cf 100644 --- a/arch/arm/mach-pnx4008/irq.c +++ b/arch/arm/mach-pnx4008/irq.c | |||
@@ -58,22 +58,22 @@ static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type) | |||
58 | case IRQ_TYPE_EDGE_RISING: | 58 | case IRQ_TYPE_EDGE_RISING: |
59 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ | 59 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ |
60 | __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ | 60 | __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ |
61 | set_irq_handler(d->irq, handle_edge_irq); | 61 | irq_set_handler(d->irq, handle_edge_irq); |
62 | break; | 62 | break; |
63 | case IRQ_TYPE_EDGE_FALLING: | 63 | case IRQ_TYPE_EDGE_FALLING: |
64 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ | 64 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ |
65 | __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */ | 65 | __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */ |
66 | set_irq_handler(d->irq, handle_edge_irq); | 66 | irq_set_handler(d->irq, handle_edge_irq); |
67 | break; | 67 | break; |
68 | case IRQ_TYPE_LEVEL_LOW: | 68 | case IRQ_TYPE_LEVEL_LOW: |
69 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ | 69 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ |
70 | __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ | 70 | __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ |
71 | set_irq_handler(d->irq, handle_level_irq); | 71 | irq_set_handler(d->irq, handle_level_irq); |
72 | break; | 72 | break; |
73 | case IRQ_TYPE_LEVEL_HIGH: | 73 | case IRQ_TYPE_LEVEL_HIGH: |
74 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ | 74 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ |
75 | __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */ | 75 | __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */ |
76 | set_irq_handler(d->irq, handle_level_irq); | 76 | irq_set_handler(d->irq, handle_level_irq); |
77 | break; | 77 | break; |
78 | 78 | ||
79 | /* IRQ_TYPE_EDGE_BOTH is not supported */ | 79 | /* IRQ_TYPE_EDGE_BOTH is not supported */ |
@@ -98,7 +98,7 @@ void __init pnx4008_init_irq(void) | |||
98 | /* configure IRQ's */ | 98 | /* configure IRQ's */ |
99 | for (i = 0; i < NR_IRQS; i++) { | 99 | for (i = 0; i < NR_IRQS; i++) { |
100 | set_irq_flags(i, IRQF_VALID); | 100 | set_irq_flags(i, IRQF_VALID); |
101 | set_irq_chip(i, &pnx4008_irq_chip); | 101 | irq_set_chip(i, &pnx4008_irq_chip); |
102 | pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]); | 102 | pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]); |
103 | } | 103 | } |
104 | 104 | ||
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index d2af73321dae..a773b730e432 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c | |||
@@ -527,13 +527,13 @@ static void __init balloon3_init_irq(void) | |||
527 | pxa27x_init_irq(); | 527 | pxa27x_init_irq(); |
528 | /* setup extra Balloon3 irqs */ | 528 | /* setup extra Balloon3 irqs */ |
529 | for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) { | 529 | for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) { |
530 | set_irq_chip(irq, &balloon3_irq_chip); | 530 | irq_set_chip(irq, &balloon3_irq_chip); |
531 | set_irq_handler(irq, handle_level_irq); | 531 | irq_set_handler(irq, handle_level_irq); |
532 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 532 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
533 | } | 533 | } |
534 | 534 | ||
535 | set_irq_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); | 535 | irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); |
536 | set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING); | 536 | irq_set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING); |
537 | 537 | ||
538 | pr_debug("%s: chained handler installed - irq %d automatically " | 538 | pr_debug("%s: chained handler installed - irq %d automatically " |
539 | "enabled\n", __func__, BALLOON3_AUX_NIRQ); | 539 | "enabled\n", __func__, BALLOON3_AUX_NIRQ); |
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index a2380cd76f80..8b1a30959fae 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c | |||
@@ -70,9 +70,10 @@ void __cmx2xx_pci_init_irq(int irq_gpio) | |||
70 | 70 | ||
71 | cmx2xx_it8152_irq_gpio = irq_gpio; | 71 | cmx2xx_it8152_irq_gpio = irq_gpio; |
72 | 72 | ||
73 | set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); | 73 | irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); |
74 | 74 | ||
75 | set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx2xx_it8152_irq_demux); | 75 | irq_set_chained_handler(gpio_to_irq(irq_gpio), |
76 | cmx2xx_it8152_irq_demux); | ||
76 | } | 77 | } |
77 | 78 | ||
78 | #ifdef CONFIG_PM | 79 | #ifdef CONFIG_PM |
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index bfca7ed2fea3..06d0a03f462d 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c | |||
@@ -765,7 +765,7 @@ static void __init cm_x300_init_da9030(void) | |||
765 | { | 765 | { |
766 | pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info); | 766 | pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info); |
767 | i2c_register_board_info(1, &cm_x300_pmic_info, 1); | 767 | i2c_register_board_info(1, &cm_x300_pmic_info, 1); |
768 | set_irq_wake(IRQ_WAKEUP0, 1); | 768 | irq_set_irq_wake(IRQ_WAKEUP0, 1); |
769 | } | 769 | } |
770 | 770 | ||
771 | static void __init cm_x300_init_wi2wi(void) | 771 | static void __init cm_x300_init_wi2wi(void) |
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 2693e3c3776f..cc7bfc3428c8 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
@@ -137,9 +137,9 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn) | |||
137 | GEDR0 = 0x3; | 137 | GEDR0 = 0x3; |
138 | 138 | ||
139 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | 139 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { |
140 | set_irq_chip(irq, &pxa_low_gpio_chip); | 140 | irq_set_chip(irq, &pxa_low_gpio_chip); |
141 | set_irq_chip_data(irq, irq_base(0)); | 141 | irq_set_chip_data(irq, irq_base(0)); |
142 | set_irq_handler(irq, handle_edge_irq); | 142 | irq_set_handler(irq, handle_edge_irq); |
143 | set_irq_flags(irq, IRQF_VALID); | 143 | set_irq_flags(irq, IRQF_VALID); |
144 | } | 144 | } |
145 | 145 | ||
@@ -165,9 +165,9 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) | |||
165 | __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); | 165 | __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); |
166 | 166 | ||
167 | irq = PXA_IRQ(i); | 167 | irq = PXA_IRQ(i); |
168 | set_irq_chip(irq, &pxa_internal_irq_chip); | 168 | irq_set_chip(irq, &pxa_internal_irq_chip); |
169 | set_irq_chip_data(irq, base); | 169 | irq_set_chip_data(irq, base); |
170 | set_irq_handler(irq, handle_level_irq); | 170 | irq_set_handler(irq, handle_level_irq); |
171 | set_irq_flags(irq, IRQF_VALID); | 171 | set_irq_flags(irq, IRQF_VALID); |
172 | } | 172 | } |
173 | } | 173 | } |
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index c9a3e775c2de..a1b094223e31 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c | |||
@@ -149,12 +149,12 @@ static void __init lpd270_init_irq(void) | |||
149 | 149 | ||
150 | /* setup extra LogicPD PXA270 irqs */ | 150 | /* setup extra LogicPD PXA270 irqs */ |
151 | for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { | 151 | for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { |
152 | set_irq_chip(irq, &lpd270_irq_chip); | 152 | irq_set_chip(irq, &lpd270_irq_chip); |
153 | set_irq_handler(irq, handle_level_irq); | 153 | irq_set_handler(irq, handle_level_irq); |
154 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 154 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
155 | } | 155 | } |
156 | set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); | 156 | irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); |
157 | set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); | 157 | irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); |
158 | } | 158 | } |
159 | 159 | ||
160 | 160 | ||
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index dca20de306bb..061d01b50094 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c | |||
@@ -165,13 +165,13 @@ static void __init lubbock_init_irq(void) | |||
165 | 165 | ||
166 | /* setup extra lubbock irqs */ | 166 | /* setup extra lubbock irqs */ |
167 | for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { | 167 | for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { |
168 | set_irq_chip(irq, &lubbock_irq_chip); | 168 | irq_set_chip(irq, &lubbock_irq_chip); |
169 | set_irq_handler(irq, handle_level_irq); | 169 | irq_set_handler(irq, handle_level_irq); |
170 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 170 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
171 | } | 171 | } |
172 | 172 | ||
173 | set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); | 173 | irq_set_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); |
174 | set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); | 174 | irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); |
175 | } | 175 | } |
176 | 176 | ||
177 | #ifdef CONFIG_PM | 177 | #ifdef CONFIG_PM |
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index f9542220595a..9ee703225ab8 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c | |||
@@ -166,8 +166,8 @@ static void __init mainstone_init_irq(void) | |||
166 | 166 | ||
167 | /* setup extra Mainstone irqs */ | 167 | /* setup extra Mainstone irqs */ |
168 | for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { | 168 | for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { |
169 | set_irq_chip(irq, &mainstone_irq_chip); | 169 | irq_set_chip(irq, &mainstone_irq_chip); |
170 | set_irq_handler(irq, handle_level_irq); | 170 | irq_set_handler(irq, handle_level_irq); |
171 | if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) | 171 | if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) |
172 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); | 172 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); |
173 | else | 173 | else |
@@ -179,8 +179,8 @@ static void __init mainstone_init_irq(void) | |||
179 | MST_INTMSKENA = 0; | 179 | MST_INTMSKENA = 0; |
180 | MST_INTSETCLR = 0; | 180 | MST_INTSETCLR = 0; |
181 | 181 | ||
182 | set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); | 182 | irq_set_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); |
183 | set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); | 183 | irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); |
184 | } | 184 | } |
185 | 185 | ||
186 | #ifdef CONFIG_PM | 186 | #ifdef CONFIG_PM |
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 9dbf3ccd4150..6c02b589d143 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c | |||
@@ -281,16 +281,16 @@ static void __init pcm990_init_irq(void) | |||
281 | 281 | ||
282 | /* setup extra PCM990 irqs */ | 282 | /* setup extra PCM990 irqs */ |
283 | for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) { | 283 | for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) { |
284 | set_irq_chip(irq, &pcm990_irq_chip); | 284 | irq_set_chip(irq, &pcm990_irq_chip); |
285 | set_irq_handler(irq, handle_level_irq); | 285 | irq_set_handler(irq, handle_level_irq); |
286 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 286 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
287 | } | 287 | } |
288 | 288 | ||
289 | PCM990_INTMSKENA = 0x00; /* disable all Interrupts */ | 289 | PCM990_INTMSKENA = 0x00; /* disable all Interrupts */ |
290 | PCM990_INTSETCLR = 0xFF; | 290 | PCM990_INTSETCLR = 0xFF; |
291 | 291 | ||
292 | set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler); | 292 | irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler); |
293 | set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE); | 293 | irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE); |
294 | } | 294 | } |
295 | 295 | ||
296 | static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int, | 296 | static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int, |
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index f374247b8466..8abe93f4e519 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
@@ -362,8 +362,8 @@ static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) | |||
362 | int irq; | 362 | int irq; |
363 | 363 | ||
364 | for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { | 364 | for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { |
365 | set_irq_chip(irq, &pxa_ext_wakeup_chip); | 365 | irq_set_chip(irq, &pxa_ext_wakeup_chip); |
366 | set_irq_handler(irq, handle_edge_irq); | 366 | irq_set_handler(irq, handle_edge_irq); |
367 | set_irq_flags(irq, IRQF_VALID); | 367 | set_irq_flags(irq, IRQF_VALID); |
368 | } | 368 | } |
369 | 369 | ||
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 12279214c875..26facf1cef65 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c | |||
@@ -310,14 +310,14 @@ static void __init viper_init_irq(void) | |||
310 | /* setup ISA IRQs */ | 310 | /* setup ISA IRQs */ |
311 | for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) { | 311 | for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) { |
312 | isa_irq = viper_bit_to_irq(level); | 312 | isa_irq = viper_bit_to_irq(level); |
313 | set_irq_chip(isa_irq, &viper_irq_chip); | 313 | irq_set_chip(isa_irq, &viper_irq_chip); |
314 | set_irq_handler(isa_irq, handle_edge_irq); | 314 | irq_set_handler(isa_irq, handle_edge_irq); |
315 | set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); | 315 | set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); |
316 | } | 316 | } |
317 | 317 | ||
318 | set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), | 318 | irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), |
319 | viper_irq_handler); | 319 | viper_irq_handler); |
320 | set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); | 320 | irq_set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); |
321 | } | 321 | } |
322 | 322 | ||
323 | /* Flat Panel */ | 323 | /* Flat Panel */ |
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 730f51e57c17..a7cdc4a83d40 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c | |||
@@ -136,22 +136,23 @@ static void __init zeus_init_irq(void) | |||
136 | 136 | ||
137 | /* Peripheral IRQs. It would be nice to move those inside driver | 137 | /* Peripheral IRQs. It would be nice to move those inside driver |
138 | configuration, but it is not supported at the moment. */ | 138 | configuration, but it is not supported at the moment. */ |
139 | set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); | 139 | irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); |
140 | set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); | 140 | irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); |
141 | set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); | 141 | irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); |
142 | set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING); | 142 | irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), |
143 | set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); | 143 | IRQ_TYPE_EDGE_FALLING); |
144 | irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); | ||
144 | 145 | ||
145 | /* Setup ISA IRQs */ | 146 | /* Setup ISA IRQs */ |
146 | for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { | 147 | for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { |
147 | isa_irq = zeus_bit_to_irq(level); | 148 | isa_irq = zeus_bit_to_irq(level); |
148 | set_irq_chip(isa_irq, &zeus_irq_chip); | 149 | irq_set_chip(isa_irq, &zeus_irq_chip); |
149 | set_irq_handler(isa_irq, handle_edge_irq); | 150 | irq_set_handler(isa_irq, handle_edge_irq); |
150 | set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); | 151 | set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); |
151 | } | 152 | } |
152 | 153 | ||
153 | set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); | 154 | irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); |
154 | set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); | 155 | irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); |
155 | } | 156 | } |
156 | 157 | ||
157 | 158 | ||
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c index d29cd9b737fc..49fb9886f56c 100644 --- a/arch/arm/mach-rpc/irq.c +++ b/arch/arm/mach-rpc/irq.c | |||
@@ -133,25 +133,25 @@ void __init rpc_init_irq(void) | |||
133 | 133 | ||
134 | switch (irq) { | 134 | switch (irq) { |
135 | case 0 ... 7: | 135 | case 0 ... 7: |
136 | set_irq_chip(irq, &iomd_a_chip); | 136 | irq_set_chip(irq, &iomd_a_chip); |
137 | set_irq_handler(irq, handle_level_irq); | 137 | irq_set_handler(irq, handle_level_irq); |
138 | set_irq_flags(irq, flags); | 138 | set_irq_flags(irq, flags); |
139 | break; | 139 | break; |
140 | 140 | ||
141 | case 8 ... 15: | 141 | case 8 ... 15: |
142 | set_irq_chip(irq, &iomd_b_chip); | 142 | irq_set_chip(irq, &iomd_b_chip); |
143 | set_irq_handler(irq, handle_level_irq); | 143 | irq_set_handler(irq, handle_level_irq); |
144 | set_irq_flags(irq, flags); | 144 | set_irq_flags(irq, flags); |
145 | break; | 145 | break; |
146 | 146 | ||
147 | case 16 ... 21: | 147 | case 16 ... 21: |
148 | set_irq_chip(irq, &iomd_dma_chip); | 148 | irq_set_chip(irq, &iomd_dma_chip); |
149 | set_irq_handler(irq, handle_level_irq); | 149 | irq_set_handler(irq, handle_level_irq); |
150 | set_irq_flags(irq, flags); | 150 | set_irq_flags(irq, flags); |
151 | break; | 151 | break; |
152 | 152 | ||
153 | case 64 ... 71: | 153 | case 64 ... 71: |
154 | set_irq_chip(irq, &iomd_fiq_chip); | 154 | irq_set_chip(irq, &iomd_fiq_chip); |
155 | set_irq_flags(irq, IRQF_VALID); | 155 | set_irq_flags(irq, IRQF_VALID); |
156 | break; | 156 | break; |
157 | } | 157 | } |
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c index 606cb6b1cc47..4139f5f0b418 100644 --- a/arch/arm/mach-s3c2410/bast-irq.c +++ b/arch/arm/mach-s3c2410/bast-irq.c | |||
@@ -147,15 +147,15 @@ static __init int bast_irq_init(void) | |||
147 | 147 | ||
148 | __raw_writeb(0x0, BAST_VA_PC104_IRQMASK); | 148 | __raw_writeb(0x0, BAST_VA_PC104_IRQMASK); |
149 | 149 | ||
150 | set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux); | 150 | irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux); |
151 | 151 | ||
152 | /* register our IRQs */ | 152 | /* register our IRQs */ |
153 | 153 | ||
154 | for (i = 0; i < 4; i++) { | 154 | for (i = 0; i < 4; i++) { |
155 | unsigned int irqno = bast_pc104_irqs[i]; | 155 | unsigned int irqno = bast_pc104_irqs[i]; |
156 | 156 | ||
157 | set_irq_chip(irqno, &bast_pc104_chip); | 157 | irq_set_chip(irqno, &bast_pc104_chip); |
158 | set_irq_handler(irqno, handle_level_irq); | 158 | irq_set_handler(irqno, handle_level_irq); |
159 | set_irq_flags(irqno, IRQF_VALID); | 159 | set_irq_flags(irqno, IRQF_VALID); |
160 | } | 160 | } |
161 | } | 161 | } |
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c index eddb52ba5b65..30f79ae03289 100644 --- a/arch/arm/mach-s3c2412/irq.c +++ b/arch/arm/mach-s3c2412/irq.c | |||
@@ -175,18 +175,18 @@ static int s3c2412_irq_add(struct sys_device *sysdev) | |||
175 | unsigned int irqno; | 175 | unsigned int irqno; |
176 | 176 | ||
177 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { | 177 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { |
178 | set_irq_chip(irqno, &s3c2412_irq_eint0t4); | 178 | irq_set_chip(irqno, &s3c2412_irq_eint0t4); |
179 | set_irq_handler(irqno, handle_edge_irq); | 179 | irq_set_handler(irqno, handle_edge_irq); |
180 | set_irq_flags(irqno, IRQF_VALID); | 180 | set_irq_flags(irqno, IRQF_VALID); |
181 | } | 181 | } |
182 | 182 | ||
183 | /* add demux support for CF/SDI */ | 183 | /* add demux support for CF/SDI */ |
184 | 184 | ||
185 | set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); | 185 | irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); |
186 | 186 | ||
187 | for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { | 187 | for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { |
188 | set_irq_chip(irqno, &s3c2412_irq_cfsdi); | 188 | irq_set_chip(irqno, &s3c2412_irq_cfsdi); |
189 | set_irq_handler(irqno, handle_level_irq); | 189 | irq_set_handler(irqno, handle_level_irq); |
190 | set_irq_flags(irqno, IRQF_VALID); | 190 | set_irq_flags(irqno, IRQF_VALID); |
191 | } | 191 | } |
192 | 192 | ||
@@ -195,7 +195,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev) | |||
195 | s3c2412_irq_rtc_chip = s3c_irq_chip; | 195 | s3c2412_irq_rtc_chip = s3c_irq_chip; |
196 | s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake; | 196 | s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake; |
197 | 197 | ||
198 | set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); | 198 | irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); |
199 | 199 | ||
200 | return 0; | 200 | return 0; |
201 | } | 201 | } |
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c index 680fe386aca5..de21c841b56d 100644 --- a/arch/arm/mach-s3c2416/irq.c +++ b/arch/arm/mach-s3c2416/irq.c | |||
@@ -202,13 +202,13 @@ static int __init s3c2416_add_sub(unsigned int base, | |||
202 | { | 202 | { |
203 | unsigned int irqno; | 203 | unsigned int irqno; |
204 | 204 | ||
205 | set_irq_chip(base, &s3c_irq_level_chip); | 205 | irq_set_chip(base, &s3c_irq_level_chip); |
206 | set_irq_handler(base, handle_level_irq); | 206 | irq_set_handler(base, handle_level_irq); |
207 | set_irq_chained_handler(base, demux); | 207 | irq_set_chained_handler(base, demux); |
208 | 208 | ||
209 | for (irqno = start; irqno <= end; irqno++) { | 209 | for (irqno = start; irqno <= end; irqno++) { |
210 | set_irq_chip(irqno, chip); | 210 | irq_set_chip(irqno, chip); |
211 | set_irq_handler(irqno, handle_level_irq); | 211 | irq_set_handler(irqno, handle_level_irq); |
212 | set_irq_flags(irqno, IRQF_VALID); | 212 | set_irq_flags(irqno, IRQF_VALID); |
213 | } | 213 | } |
214 | 214 | ||
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c index acad4428bef0..0c564b149a46 100644 --- a/arch/arm/mach-s3c2440/irq.c +++ b/arch/arm/mach-s3c2440/irq.c | |||
@@ -100,13 +100,13 @@ static int s3c2440_irq_add(struct sys_device *sysdev) | |||
100 | 100 | ||
101 | /* add new chained handler for wdt, ac7 */ | 101 | /* add new chained handler for wdt, ac7 */ |
102 | 102 | ||
103 | set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); | 103 | irq_set_chip(IRQ_WDT, &s3c_irq_level_chip); |
104 | set_irq_handler(IRQ_WDT, handle_level_irq); | 104 | irq_set_handler(IRQ_WDT, handle_level_irq); |
105 | set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); | 105 | irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); |
106 | 106 | ||
107 | for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { | 107 | for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { |
108 | set_irq_chip(irqno, &s3c_irq_wdtac97); | 108 | irq_set_chip(irqno, &s3c_irq_wdtac97); |
109 | set_irq_handler(irqno, handle_level_irq); | 109 | irq_set_handler(irqno, handle_level_irq); |
110 | set_irq_flags(irqno, IRQF_VALID); | 110 | set_irq_flags(irqno, IRQF_VALID); |
111 | } | 111 | } |
112 | 112 | ||
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c index 83daf4ece764..5a48881c4508 100644 --- a/arch/arm/mach-s3c2440/s3c244x-irq.c +++ b/arch/arm/mach-s3c2440/s3c244x-irq.c | |||
@@ -95,19 +95,19 @@ static int s3c244x_irq_add(struct sys_device *sysdev) | |||
95 | { | 95 | { |
96 | unsigned int irqno; | 96 | unsigned int irqno; |
97 | 97 | ||
98 | set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); | 98 | irq_set_chip(IRQ_NFCON, &s3c_irq_level_chip); |
99 | set_irq_handler(IRQ_NFCON, handle_level_irq); | 99 | irq_set_handler(IRQ_NFCON, handle_level_irq); |
100 | set_irq_flags(IRQ_NFCON, IRQF_VALID); | 100 | set_irq_flags(IRQ_NFCON, IRQF_VALID); |
101 | 101 | ||
102 | /* add chained handler for camera */ | 102 | /* add chained handler for camera */ |
103 | 103 | ||
104 | set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); | 104 | irq_set_chip(IRQ_CAM, &s3c_irq_level_chip); |
105 | set_irq_handler(IRQ_CAM, handle_level_irq); | 105 | irq_set_handler(IRQ_CAM, handle_level_irq); |
106 | set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); | 106 | irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam); |
107 | 107 | ||
108 | for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { | 108 | for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { |
109 | set_irq_chip(irqno, &s3c_irq_cam); | 109 | irq_set_chip(irqno, &s3c_irq_cam); |
110 | set_irq_handler(irqno, handle_level_irq); | 110 | irq_set_handler(irqno, handle_level_irq); |
111 | set_irq_flags(irqno, IRQF_VALID); | 111 | set_irq_flags(irqno, IRQF_VALID); |
112 | } | 112 | } |
113 | 113 | ||
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c index c7820f9c1352..b12431fae263 100644 --- a/arch/arm/mach-s3c2443/irq.c +++ b/arch/arm/mach-s3c2443/irq.c | |||
@@ -230,13 +230,13 @@ static int __init s3c2443_add_sub(unsigned int base, | |||
230 | { | 230 | { |
231 | unsigned int irqno; | 231 | unsigned int irqno; |
232 | 232 | ||
233 | set_irq_chip(base, &s3c_irq_level_chip); | 233 | irq_set_chip(base, &s3c_irq_level_chip); |
234 | set_irq_handler(base, handle_level_irq); | 234 | irq_set_handler(base, handle_level_irq); |
235 | set_irq_chained_handler(base, demux); | 235 | irq_set_chained_handler(base, demux); |
236 | 236 | ||
237 | for (irqno = start; irqno <= end; irqno++) { | 237 | for (irqno = start; irqno <= end; irqno++) { |
238 | set_irq_chip(irqno, chip); | 238 | irq_set_chip(irqno, chip); |
239 | set_irq_handler(irqno, handle_level_irq); | 239 | irq_set_handler(irqno, handle_level_irq); |
240 | set_irq_flags(irqno, IRQF_VALID); | 240 | set_irq_flags(irqno, IRQF_VALID); |
241 | } | 241 | } |
242 | 242 | ||
diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c index 2ead8189da74..9a4c7aeab5c5 100644 --- a/arch/arm/mach-s3c64xx/irq-eint.c +++ b/arch/arm/mach-s3c64xx/irq-eint.c | |||
@@ -197,16 +197,16 @@ static int __init s3c64xx_init_irq_eint(void) | |||
197 | int irq; | 197 | int irq; |
198 | 198 | ||
199 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { | 199 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { |
200 | set_irq_chip(irq, &s3c_irq_eint); | 200 | irq_set_chip(irq, &s3c_irq_eint); |
201 | set_irq_chip_data(irq, (void *)eint_irq_to_bit(irq)); | 201 | irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); |
202 | set_irq_handler(irq, handle_level_irq); | 202 | irq_set_handler(irq, handle_level_irq); |
203 | set_irq_flags(irq, IRQF_VALID); | 203 | set_irq_flags(irq, IRQF_VALID); |
204 | } | 204 | } |
205 | 205 | ||
206 | set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); | 206 | irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); |
207 | set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); | 207 | irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); |
208 | set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); | 208 | irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); |
209 | set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); | 209 | irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); |
210 | 210 | ||
211 | return 0; | 211 | return 0; |
212 | } | 212 | } |
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c index 98d780608c7e..7f3da4b11ec9 100644 --- a/arch/arm/mach-sa1100/cerf.c +++ b/arch/arm/mach-sa1100/cerf.c | |||
@@ -96,7 +96,7 @@ static struct resource cerf_flash_resource = { | |||
96 | static void __init cerf_init_irq(void) | 96 | static void __init cerf_init_irq(void) |
97 | { | 97 | { |
98 | sa1100_init_irq(); | 98 | sa1100_init_irq(); |
99 | set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); | 99 | irq_set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); |
100 | } | 100 | } |
101 | 101 | ||
102 | static struct map_desc cerf_io_desc[] __initdata = { | 102 | static struct map_desc cerf_io_desc[] __initdata = { |
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 3d85dfad9c1f..0f109e179cbb 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c | |||
@@ -323,28 +323,28 @@ void __init sa1100_init_irq(void) | |||
323 | ICCR = 1; | 323 | ICCR = 1; |
324 | 324 | ||
325 | for (irq = 0; irq <= 10; irq++) { | 325 | for (irq = 0; irq <= 10; irq++) { |
326 | set_irq_chip(irq, &sa1100_low_gpio_chip); | 326 | irq_set_chip(irq, &sa1100_low_gpio_chip); |
327 | set_irq_handler(irq, handle_edge_irq); | 327 | irq_set_handler(irq, handle_edge_irq); |
328 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 328 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
329 | } | 329 | } |
330 | 330 | ||
331 | for (irq = 12; irq <= 31; irq++) { | 331 | for (irq = 12; irq <= 31; irq++) { |
332 | set_irq_chip(irq, &sa1100_normal_chip); | 332 | irq_set_chip(irq, &sa1100_normal_chip); |
333 | set_irq_handler(irq, handle_level_irq); | 333 | irq_set_handler(irq, handle_level_irq); |
334 | set_irq_flags(irq, IRQF_VALID); | 334 | set_irq_flags(irq, IRQF_VALID); |
335 | } | 335 | } |
336 | 336 | ||
337 | for (irq = 32; irq <= 48; irq++) { | 337 | for (irq = 32; irq <= 48; irq++) { |
338 | set_irq_chip(irq, &sa1100_high_gpio_chip); | 338 | irq_set_chip(irq, &sa1100_high_gpio_chip); |
339 | set_irq_handler(irq, handle_edge_irq); | 339 | irq_set_handler(irq, handle_edge_irq); |
340 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 340 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
341 | } | 341 | } |
342 | 342 | ||
343 | /* | 343 | /* |
344 | * Install handler for GPIO 11-27 edge detect interrupts | 344 | * Install handler for GPIO 11-27 edge detect interrupts |
345 | */ | 345 | */ |
346 | set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip); | 346 | irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip); |
347 | set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); | 347 | irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); |
348 | 348 | ||
349 | sa1100_init_gpio(); | 349 | sa1100_init_gpio(); |
350 | } | 350 | } |
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 4aad01f73660..b4fa53a1427e 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c | |||
@@ -145,8 +145,8 @@ static int __devinit neponset_probe(struct platform_device *dev) | |||
145 | /* | 145 | /* |
146 | * Install handler for GPIO25. | 146 | * Install handler for GPIO25. |
147 | */ | 147 | */ |
148 | set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); | 148 | irq_set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); |
149 | set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler); | 149 | irq_set_chained_handler(IRQ_GPIO25, neponset_irq_handler); |
150 | 150 | ||
151 | /* | 151 | /* |
152 | * We would set IRQ_GPIO25 to be a wake-up IRQ, but | 152 | * We would set IRQ_GPIO25 to be a wake-up IRQ, but |
@@ -161,9 +161,9 @@ static int __devinit neponset_probe(struct platform_device *dev) | |||
161 | * Setup other Neponset IRQs. SA1111 will be done by the | 161 | * Setup other Neponset IRQs. SA1111 will be done by the |
162 | * generic SA1111 code. | 162 | * generic SA1111 code. |
163 | */ | 163 | */ |
164 | set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); | 164 | irq_set_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); |
165 | set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); | 165 | set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); |
166 | set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq); | 166 | irq_set_handler(IRQ_NEPONSET_USAR, handle_simple_irq); |
167 | set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); | 167 | set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); |
168 | 168 | ||
169 | /* | 169 | /* |
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c index 42b80400c100..65161f2bea29 100644 --- a/arch/arm/mach-sa1100/pleb.c +++ b/arch/arm/mach-sa1100/pleb.c | |||
@@ -142,7 +142,7 @@ static void __init pleb_map_io(void) | |||
142 | 142 | ||
143 | GPDR &= ~GPIO_ETH0_IRQ; | 143 | GPDR &= ~GPIO_ETH0_IRQ; |
144 | 144 | ||
145 | set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); | 145 | irq_set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); |
146 | } | 146 | } |
147 | 147 | ||
148 | MACHINE_START(PLEB, "PLEB") | 148 | MACHINE_START(PLEB, "PLEB") |
diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c index 831fc66dfa4d..2e6da5fe1859 100644 --- a/arch/arm/mach-shark/irq.c +++ b/arch/arm/mach-shark/irq.c | |||
@@ -80,8 +80,8 @@ void __init shark_init_irq(void) | |||
80 | int irq; | 80 | int irq; |
81 | 81 | ||
82 | for (irq = 0; irq < NR_IRQS; irq++) { | 82 | for (irq = 0; irq < NR_IRQS; irq++) { |
83 | set_irq_chip(irq, &fb_chip); | 83 | irq_set_chip(irq, &fb_chip); |
84 | set_irq_handler(irq, handle_edge_irq); | 84 | irq_set_handler(irq, handle_edge_irq); |
85 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 85 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
86 | } | 86 | } |
87 | 87 | ||
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index a94f29da5d30..08cc45137bdc 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c | |||
@@ -1255,7 +1255,7 @@ static void __init ap4evb_init(void) | |||
1255 | gpio_request(GPIO_FN_KEYIN4, NULL); | 1255 | gpio_request(GPIO_FN_KEYIN4, NULL); |
1256 | 1256 | ||
1257 | /* enable TouchScreen */ | 1257 | /* enable TouchScreen */ |
1258 | set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); | 1258 | irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); |
1259 | 1259 | ||
1260 | tsc_device.irq = IRQ28; | 1260 | tsc_device.irq = IRQ28; |
1261 | i2c_register_board_info(1, &tsc_device, 1); | 1261 | i2c_register_board_info(1, &tsc_device, 1); |
@@ -1311,7 +1311,7 @@ static void __init ap4evb_init(void) | |||
1311 | lcdc_info.ch[0].lcd_size_cfg.height = 91; | 1311 | lcdc_info.ch[0].lcd_size_cfg.height = 91; |
1312 | 1312 | ||
1313 | /* enable TouchScreen */ | 1313 | /* enable TouchScreen */ |
1314 | set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); | 1314 | irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); |
1315 | 1315 | ||
1316 | tsc_device.irq = IRQ7; | 1316 | tsc_device.irq = IRQ7; |
1317 | i2c_register_board_info(0, &tsc_device, 1); | 1317 | i2c_register_board_info(0, &tsc_device, 1); |
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 49bc07482179..f0d0af14ae06 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c | |||
@@ -1124,15 +1124,15 @@ static void __init mackerel_init(void) | |||
1124 | 1124 | ||
1125 | /* enable Keypad */ | 1125 | /* enable Keypad */ |
1126 | gpio_request(GPIO_FN_IRQ9_42, NULL); | 1126 | gpio_request(GPIO_FN_IRQ9_42, NULL); |
1127 | set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); | 1127 | irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); |
1128 | 1128 | ||
1129 | /* enable Touchscreen */ | 1129 | /* enable Touchscreen */ |
1130 | gpio_request(GPIO_FN_IRQ7_40, NULL); | 1130 | gpio_request(GPIO_FN_IRQ7_40, NULL); |
1131 | set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); | 1131 | irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); |
1132 | 1132 | ||
1133 | /* enable Accelerometer */ | 1133 | /* enable Accelerometer */ |
1134 | gpio_request(GPIO_FN_IRQ21, NULL); | 1134 | gpio_request(GPIO_FN_IRQ21, NULL); |
1135 | set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); | 1135 | irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); |
1136 | 1136 | ||
1137 | /* enable SDHI0 */ | 1137 | /* enable SDHI0 */ |
1138 | gpio_request(GPIO_FN_SDHICD0, NULL); | 1138 | gpio_request(GPIO_FN_SDHICD0, NULL); |
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c index 2fe9704d5ea1..cc442d198cdc 100644 --- a/arch/arm/mach-shmobile/intc-sh7367.c +++ b/arch/arm/mach-shmobile/intc-sh7367.c | |||
@@ -421,7 +421,7 @@ static struct intc_desc intcs_desc __initdata = { | |||
421 | 421 | ||
422 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) | 422 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) |
423 | { | 423 | { |
424 | void __iomem *reg = (void *)get_irq_data(irq); | 424 | void __iomem *reg = (void *)irq_get_handler_data(irq); |
425 | unsigned int evtcodeas = ioread32(reg); | 425 | unsigned int evtcodeas = ioread32(reg); |
426 | 426 | ||
427 | generic_handle_irq(intcs_evt2irq(evtcodeas)); | 427 | generic_handle_irq(intcs_evt2irq(evtcodeas)); |
@@ -435,6 +435,6 @@ void __init sh7367_init_irq(void) | |||
435 | register_intc_controller(&intcs_desc); | 435 | register_intc_controller(&intcs_desc); |
436 | 436 | ||
437 | /* demux using INTEVTSA */ | 437 | /* demux using INTEVTSA */ |
438 | set_irq_data(evt2irq(0xf80), (void *)intevtsa); | 438 | irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); |
439 | set_irq_chained_handler(evt2irq(0xf80), intcs_demux); | 439 | irq_set_chained_handler(evt2irq(0xf80), intcs_demux); |
440 | } | 440 | } |
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index ca5f9d17b39a..7a4960f9c1e3 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c | |||
@@ -601,7 +601,7 @@ static struct intc_desc intcs_desc __initdata = { | |||
601 | 601 | ||
602 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) | 602 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) |
603 | { | 603 | { |
604 | void __iomem *reg = (void *)get_irq_data(irq); | 604 | void __iomem *reg = (void *)irq_get_handler_data(irq); |
605 | unsigned int evtcodeas = ioread32(reg); | 605 | unsigned int evtcodeas = ioread32(reg); |
606 | 606 | ||
607 | generic_handle_irq(intcs_evt2irq(evtcodeas)); | 607 | generic_handle_irq(intcs_evt2irq(evtcodeas)); |
@@ -615,6 +615,6 @@ void __init sh7372_init_irq(void) | |||
615 | register_intc_controller(&intcs_desc); | 615 | register_intc_controller(&intcs_desc); |
616 | 616 | ||
617 | /* demux using INTEVTSA */ | 617 | /* demux using INTEVTSA */ |
618 | set_irq_data(evt2irq(0xf80), (void *)intevtsa); | 618 | irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); |
619 | set_irq_chained_handler(evt2irq(0xf80), intcs_demux); | 619 | irq_set_chained_handler(evt2irq(0xf80), intcs_demux); |
620 | } | 620 | } |
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c index dd568382cc9f..fe45154ce660 100644 --- a/arch/arm/mach-shmobile/intc-sh7377.c +++ b/arch/arm/mach-shmobile/intc-sh7377.c | |||
@@ -626,7 +626,7 @@ static struct intc_desc intcs_desc __initdata = { | |||
626 | 626 | ||
627 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) | 627 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) |
628 | { | 628 | { |
629 | void __iomem *reg = (void *)get_irq_data(irq); | 629 | void __iomem *reg = (void *)irq_get_handler_data(irq); |
630 | unsigned int evtcodeas = ioread32(reg); | 630 | unsigned int evtcodeas = ioread32(reg); |
631 | 631 | ||
632 | generic_handle_irq(intcs_evt2irq(evtcodeas)); | 632 | generic_handle_irq(intcs_evt2irq(evtcodeas)); |
@@ -641,6 +641,6 @@ void __init sh7377_init_irq(void) | |||
641 | register_intc_controller(&intcs_desc); | 641 | register_intc_controller(&intcs_desc); |
642 | 642 | ||
643 | /* demux using INTEVTSA */ | 643 | /* demux using INTEVTSA */ |
644 | set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); | 644 | irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); |
645 | set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); | 645 | irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); |
646 | } | 646 | } |
diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c index aa9231f4fc6e..209fa5c65d4c 100644 --- a/arch/arm/mach-tcc8k/irq.c +++ b/arch/arm/mach-tcc8k/irq.c | |||
@@ -102,10 +102,10 @@ void __init tcc8k_init_irq(void) | |||
102 | 102 | ||
103 | for (irqno = 0; irqno < NR_IRQS; irqno++) { | 103 | for (irqno = 0; irqno < NR_IRQS; irqno++) { |
104 | if (irqno < 32) | 104 | if (irqno < 32) |
105 | set_irq_chip(irqno, &tcc8000_irq_chip0); | 105 | irq_set_chip(irqno, &tcc8000_irq_chip0); |
106 | else | 106 | else |
107 | set_irq_chip(irqno, &tcc8000_irq_chip1); | 107 | irq_set_chip(irqno, &tcc8000_irq_chip1); |
108 | set_irq_handler(irqno, handle_level_irq); | 108 | irq_set_handler(irqno, handle_level_irq); |
109 | set_irq_flags(irqno, IRQF_VALID); | 109 | set_irq_flags(irqno, IRQF_VALID); |
110 | } | 110 | } |
111 | } | 111 | } |
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c index 8ab2131f41d4..4148048c4191 100644 --- a/arch/arm/mach-tegra/gpio.c +++ b/arch/arm/mach-tegra/gpio.c | |||
@@ -208,9 +208,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |||
208 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); | 208 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); |
209 | 209 | ||
210 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | 210 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
211 | __set_irq_handler_unlocked(d->irq, handle_level_irq); | 211 | __irq_set_handler_locked(d->irq, handle_level_irq); |
212 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 212 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
213 | __set_irq_handler_unlocked(d->irq, handle_edge_irq); | 213 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
214 | 214 | ||
215 | return 0; | 215 | return 0; |
216 | } | 216 | } |
@@ -224,7 +224,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
224 | 224 | ||
225 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 225 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
226 | 226 | ||
227 | bank = get_irq_data(irq); | 227 | bank = irq_get_handler_data(irq); |
228 | 228 | ||
229 | for (port = 0; port < 4; port++) { | 229 | for (port = 0; port < 4; port++) { |
230 | int gpio = tegra_gpio_compose(bank->bank, port, 0); | 230 | int gpio = tegra_gpio_compose(bank->bank, port, 0); |
@@ -301,7 +301,7 @@ void tegra_gpio_suspend(void) | |||
301 | static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) | 301 | static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
302 | { | 302 | { |
303 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); | 303 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
304 | return set_irq_wake(bank->irq, enable); | 304 | return irq_set_irq_wake(bank->irq, enable); |
305 | } | 305 | } |
306 | #endif | 306 | #endif |
307 | 307 | ||
@@ -341,17 +341,17 @@ static int __init tegra_gpio_init(void) | |||
341 | bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; | 341 | bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; |
342 | 342 | ||
343 | irq_set_lockdep_class(i, &gpio_lock_class); | 343 | irq_set_lockdep_class(i, &gpio_lock_class); |
344 | set_irq_chip_data(i, bank); | 344 | irq_set_chip_data(i, bank); |
345 | set_irq_chip(i, &tegra_gpio_irq_chip); | 345 | irq_set_chip(i, &tegra_gpio_irq_chip); |
346 | set_irq_handler(i, handle_simple_irq); | 346 | irq_set_handler(i, handle_simple_irq); |
347 | set_irq_flags(i, IRQF_VALID); | 347 | set_irq_flags(i, IRQF_VALID); |
348 | } | 348 | } |
349 | 349 | ||
350 | for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { | 350 | for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { |
351 | bank = &tegra_gpio_banks[i]; | 351 | bank = &tegra_gpio_banks[i]; |
352 | 352 | ||
353 | set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler); | 353 | irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler); |
354 | set_irq_data(bank->irq, bank); | 354 | irq_set_handler_data(bank->irq, bank); |
355 | 355 | ||
356 | for (j = 0; j < 4; j++) | 356 | for (j = 0; j < 4; j++) |
357 | spin_lock_init(&bank->lvl_lock[j]); | 357 | spin_lock_init(&bank->lvl_lock[j]); |
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index dfbc219ea492..6b5c8b8abe02 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c | |||
@@ -144,7 +144,7 @@ void __init tegra_init_irq(void) | |||
144 | gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), | 144 | gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), |
145 | IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); | 145 | IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); |
146 | 146 | ||
147 | gic = get_irq_chip(29); | 147 | gic = irq_get_chip(29); |
148 | tegra_gic_unmask_irq = gic->irq_unmask; | 148 | tegra_gic_unmask_irq = gic->irq_unmask; |
149 | tegra_gic_mask_irq = gic->irq_mask; | 149 | tegra_gic_mask_irq = gic->irq_mask; |
150 | tegra_gic_ack_irq = gic->irq_ack; | 150 | tegra_gic_ack_irq = gic->irq_ack; |
@@ -154,8 +154,8 @@ void __init tegra_init_irq(void) | |||
154 | 154 | ||
155 | for (i = 0; i < INT_MAIN_NR; i++) { | 155 | for (i = 0; i < INT_MAIN_NR; i++) { |
156 | irq = INT_PRI_BASE + i; | 156 | irq = INT_PRI_BASE + i; |
157 | set_irq_chip(irq, &tegra_irq); | 157 | irq_set_chip(irq, &tegra_irq); |
158 | set_irq_handler(irq, handle_level_irq); | 158 | irq_set_handler(irq, handle_level_irq); |
159 | set_irq_flags(irq, IRQF_VALID); | 159 | set_irq_flags(irq, IRQF_VALID); |
160 | } | 160 | } |
161 | } | 161 | } |
diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c index e1296a7447c8..5f2322e6c108 100644 --- a/arch/arm/mach-ux500/modem-irq-db5500.c +++ b/arch/arm/mach-ux500/modem-irq-db5500.c | |||
@@ -90,8 +90,8 @@ static irqreturn_t modem_cpu_irq_handler(int irq, void *data) | |||
90 | 90 | ||
91 | static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip) | 91 | static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip) |
92 | { | 92 | { |
93 | set_irq_chip(irq, modem_irq_chip); | 93 | irq_set_chip(irq, modem_irq_chip); |
94 | set_irq_handler(irq, handle_simple_irq); | 94 | irq_set_handler(irq, handle_simple_irq); |
95 | set_irq_flags(irq, IRQF_VALID); | 95 | set_irq_flags(irq, IRQF_VALID); |
96 | 96 | ||
97 | pr_debug("modem_irq: Created virtual IRQ %d\n", irq); | 97 | pr_debug("modem_irq: Created virtual IRQ %d\n", irq); |
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index eb7ffa0ee8b5..96e59e3ee4f5 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c | |||
@@ -314,7 +314,7 @@ static struct mmci_platform_data mmc0_plat_data = { | |||
314 | .gpio_cd = -1, | 314 | .gpio_cd = -1, |
315 | }; | 315 | }; |
316 | 316 | ||
317 | static struct resource char_lcd_resources[] = { | 317 | static struct resource chalcd_resources[] = { |
318 | { | 318 | { |
319 | .start = VERSATILE_CHAR_LCD_BASE, | 319 | .start = VERSATILE_CHAR_LCD_BASE, |
320 | .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1), | 320 | .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1), |
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c index cba4695c0fa3..e495c014fefd 100644 --- a/arch/arm/mach-vt8500/irq.c +++ b/arch/arm/mach-vt8500/irq.c | |||
@@ -136,8 +136,8 @@ void __init vt8500_init_irq(void) | |||
136 | /* Disable all interrupts and route them to IRQ */ | 136 | /* Disable all interrupts and route them to IRQ */ |
137 | writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); | 137 | writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); |
138 | 138 | ||
139 | set_irq_chip(i, &vt8500_irq_chip); | 139 | irq_set_chip(i, &vt8500_irq_chip); |
140 | set_irq_handler(i, handle_level_irq); | 140 | irq_set_handler(i, handle_level_irq); |
141 | set_irq_flags(i, IRQF_VALID); | 141 | set_irq_flags(i, IRQF_VALID); |
142 | } | 142 | } |
143 | } else { | 143 | } else { |
@@ -167,8 +167,8 @@ void __init wm8505_init_irq(void) | |||
167 | writeb(0x00, sic_regbase + VT8500_IC_DCTR | 167 | writeb(0x00, sic_regbase + VT8500_IC_DCTR |
168 | + i - 64); | 168 | + i - 64); |
169 | 169 | ||
170 | set_irq_chip(i, &vt8500_irq_chip); | 170 | irq_set_chip(i, &vt8500_irq_chip); |
171 | set_irq_handler(i, handle_level_irq); | 171 | irq_set_handler(i, handle_level_irq); |
172 | set_irq_flags(i, IRQF_VALID); | 172 | set_irq_flags(i, IRQF_VALID); |
173 | } | 173 | } |
174 | } else { | 174 | } else { |
diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c index 9c350103dcda..5947d1f630d2 100644 --- a/arch/arm/mach-w90x900/irq.c +++ b/arch/arm/mach-w90x900/irq.c | |||
@@ -207,8 +207,8 @@ void __init nuc900_init_irq(void) | |||
207 | __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); | 207 | __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); |
208 | 208 | ||
209 | for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { | 209 | for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { |
210 | set_irq_chip(irqno, &nuc900_irq_chip); | 210 | irq_set_chip(irqno, &nuc900_irq_chip); |
211 | set_irq_handler(irqno, handle_level_irq); | 211 | irq_set_handler(irqno, handle_level_irq); |
212 | set_irq_flags(irqno, IRQF_VALID); | 212 | set_irq_flags(irqno, IRQF_VALID); |
213 | } | 213 | } |
214 | } | 214 | } |
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c index 8a2fb7046c94..9d424ce93354 100644 --- a/arch/arm/plat-mxc/3ds_debugboard.c +++ b/arch/arm/plat-mxc/3ds_debugboard.c | |||
@@ -181,12 +181,12 @@ int __init mxc_expio_init(u32 base, u32 p_irq) | |||
181 | __raw_writew(0x1F, brd_io + INTR_MASK_REG); | 181 | __raw_writew(0x1F, brd_io + INTR_MASK_REG); |
182 | for (i = MXC_EXP_IO_BASE; | 182 | for (i = MXC_EXP_IO_BASE; |
183 | i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { | 183 | i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { |
184 | set_irq_chip(i, &expio_irq_chip); | 184 | irq_set_chip(i, &expio_irq_chip); |
185 | set_irq_handler(i, handle_level_irq); | 185 | irq_set_handler(i, handle_level_irq); |
186 | set_irq_flags(i, IRQF_VALID); | 186 | set_irq_flags(i, IRQF_VALID); |
187 | } | 187 | } |
188 | set_irq_type(p_irq, IRQF_TRIGGER_LOW); | 188 | irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW); |
189 | set_irq_chained_handler(p_irq, mxc_expio_irq_handler); | 189 | irq_set_chained_handler(p_irq, mxc_expio_irq_handler); |
190 | 190 | ||
191 | /* Register Lan device on the debugboard */ | 191 | /* Register Lan device on the debugboard */ |
192 | smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); | 192 | smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); |
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c index deb284bc7c4b..8b30c83a2ab1 100644 --- a/arch/arm/plat-mxc/avic.c +++ b/arch/arm/plat-mxc/avic.c | |||
@@ -139,8 +139,8 @@ void __init mxc_init_irq(void __iomem *irqbase) | |||
139 | __raw_writel(0, avic_base + AVIC_INTTYPEH); | 139 | __raw_writel(0, avic_base + AVIC_INTTYPEH); |
140 | __raw_writel(0, avic_base + AVIC_INTTYPEL); | 140 | __raw_writel(0, avic_base + AVIC_INTTYPEL); |
141 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { | 141 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { |
142 | set_irq_chip(i, &mxc_avic_chip.base); | 142 | irq_set_chip(i, &mxc_avic_chip.base); |
143 | set_irq_handler(i, handle_level_irq); | 143 | irq_set_handler(i, handle_level_irq); |
144 | set_irq_flags(i, IRQF_VALID); | 144 | set_irq_flags(i, IRQF_VALID); |
145 | } | 145 | } |
146 | 146 | ||
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 57d59855f9ec..2ff0b3f9b46d 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c | |||
@@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) | |||
175 | static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) | 175 | static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) |
176 | { | 176 | { |
177 | u32 irq_stat; | 177 | u32 irq_stat; |
178 | struct mxc_gpio_port *port = get_irq_data(irq); | 178 | struct mxc_gpio_port *port = irq_get_handler_data(irq); |
179 | 179 | ||
180 | irq_stat = __raw_readl(port->base + GPIO_ISR) & | 180 | irq_stat = __raw_readl(port->base + GPIO_ISR) & |
181 | __raw_readl(port->base + GPIO_IMR); | 181 | __raw_readl(port->base + GPIO_IMR); |
@@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) | |||
188 | { | 188 | { |
189 | int i; | 189 | int i; |
190 | u32 irq_msk, irq_stat; | 190 | u32 irq_msk, irq_stat; |
191 | struct mxc_gpio_port *port = get_irq_data(irq); | 191 | struct mxc_gpio_port *port = irq_get_handler_data(irq); |
192 | 192 | ||
193 | /* walk through all interrupt status registers */ | 193 | /* walk through all interrupt status registers */ |
194 | for (i = 0; i < gpio_table_size; i++) { | 194 | for (i = 0; i < gpio_table_size; i++) { |
@@ -311,8 +311,8 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) | |||
311 | __raw_writel(~0, port[i].base + GPIO_ISR); | 311 | __raw_writel(~0, port[i].base + GPIO_ISR); |
312 | for (j = port[i].virtual_irq_start; | 312 | for (j = port[i].virtual_irq_start; |
313 | j < port[i].virtual_irq_start + 32; j++) { | 313 | j < port[i].virtual_irq_start + 32; j++) { |
314 | set_irq_chip(j, &gpio_irq_chip); | 314 | irq_set_chip(j, &gpio_irq_chip); |
315 | set_irq_handler(j, handle_level_irq); | 315 | irq_set_handler(j, handle_level_irq); |
316 | set_irq_flags(j, IRQF_VALID); | 316 | set_irq_flags(j, IRQF_VALID); |
317 | } | 317 | } |
318 | 318 | ||
@@ -331,21 +331,23 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) | |||
331 | 331 | ||
332 | if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { | 332 | if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { |
333 | /* setup one handler for each entry */ | 333 | /* setup one handler for each entry */ |
334 | set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); | 334 | irq_set_chained_handler(port[i].irq, |
335 | set_irq_data(port[i].irq, &port[i]); | 335 | mx3_gpio_irq_handler); |
336 | irq_set_handler_data(port[i].irq, &port[i]); | ||
336 | if (port[i].irq_high) { | 337 | if (port[i].irq_high) { |
337 | /* setup handler for GPIO 16 to 31 */ | 338 | /* setup handler for GPIO 16 to 31 */ |
338 | set_irq_chained_handler(port[i].irq_high, | 339 | irq_set_chained_handler(port[i].irq_high, |
339 | mx3_gpio_irq_handler); | 340 | mx3_gpio_irq_handler); |
340 | set_irq_data(port[i].irq_high, &port[i]); | 341 | irq_set_handler_data(port[i].irq_high, |
342 | &port[i]); | ||
341 | } | 343 | } |
342 | } | 344 | } |
343 | } | 345 | } |
344 | 346 | ||
345 | if (cpu_is_mx2()) { | 347 | if (cpu_is_mx2()) { |
346 | /* setup one handler for all GPIO interrupts */ | 348 | /* setup one handler for all GPIO interrupts */ |
347 | set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler); | 349 | irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler); |
348 | set_irq_data(port[0].irq, port); | 350 | irq_set_handler_data(port[0].irq, port); |
349 | } | 351 | } |
350 | 352 | ||
351 | return 0; | 353 | return 0; |
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c index 0c799ac27730..e1c6eff7258a 100644 --- a/arch/arm/plat-mxc/irq-common.c +++ b/arch/arm/plat-mxc/irq-common.c | |||
@@ -29,7 +29,7 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio) | |||
29 | 29 | ||
30 | ret = -ENOSYS; | 30 | ret = -ENOSYS; |
31 | 31 | ||
32 | base = get_irq_chip(irq); | 32 | base = irq_get_chip(irq); |
33 | if (base) { | 33 | if (base) { |
34 | chip = container_of(base, struct mxc_irq_chip, base); | 34 | chip = container_of(base, struct mxc_irq_chip, base); |
35 | if (chip->set_priority) | 35 | if (chip->set_priority) |
@@ -48,7 +48,7 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type) | |||
48 | 48 | ||
49 | ret = -ENOSYS; | 49 | ret = -ENOSYS; |
50 | 50 | ||
51 | base = get_irq_chip(irq); | 51 | base = irq_get_chip(irq); |
52 | if (base) { | 52 | if (base) { |
53 | chip = container_of(base, struct mxc_irq_chip, base); | 53 | chip = container_of(base, struct mxc_irq_chip, base); |
54 | if (chip->set_irq_fiq) | 54 | if (chip->set_irq_fiq) |
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index bc3a6be8a27f..c299152e0841 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c | |||
@@ -167,8 +167,8 @@ void __init tzic_init_irq(void __iomem *irqbase) | |||
167 | /* all IRQ no FIQ Warning :: No selection */ | 167 | /* all IRQ no FIQ Warning :: No selection */ |
168 | 168 | ||
169 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { | 169 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { |
170 | set_irq_chip(i, &mxc_tzic_chip.base); | 170 | irq_set_chip(i, &mxc_tzic_chip.base); |
171 | set_irq_handler(i, handle_level_irq); | 171 | irq_set_handler(i, handle_level_irq); |
172 | set_irq_flags(i, IRQF_VALID); | 172 | set_irq_flags(i, IRQF_VALID); |
173 | } | 173 | } |
174 | 174 | ||
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index 1b402a8e9031..63adc4d417fe 100644 --- a/arch/arm/plat-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c | |||
@@ -319,7 +319,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |||
319 | struct nmk_gpio_chip *nmk_chip; | 319 | struct nmk_gpio_chip *nmk_chip; |
320 | int pin = PIN_NUM(cfgs[i]); | 320 | int pin = PIN_NUM(cfgs[i]); |
321 | 321 | ||
322 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); | 322 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); |
323 | if (!nmk_chip) { | 323 | if (!nmk_chip) { |
324 | ret = -EINVAL; | 324 | ret = -EINVAL; |
325 | break; | 325 | break; |
@@ -398,7 +398,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |||
398 | struct nmk_gpio_chip *nmk_chip; | 398 | struct nmk_gpio_chip *nmk_chip; |
399 | unsigned long flags; | 399 | unsigned long flags; |
400 | 400 | ||
401 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | 401 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
402 | if (!nmk_chip) | 402 | if (!nmk_chip) |
403 | return -EINVAL; | 403 | return -EINVAL; |
404 | 404 | ||
@@ -431,7 +431,7 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |||
431 | struct nmk_gpio_chip *nmk_chip; | 431 | struct nmk_gpio_chip *nmk_chip; |
432 | unsigned long flags; | 432 | unsigned long flags; |
433 | 433 | ||
434 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | 434 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
435 | if (!nmk_chip) | 435 | if (!nmk_chip) |
436 | return -EINVAL; | 436 | return -EINVAL; |
437 | 437 | ||
@@ -457,7 +457,7 @@ int nmk_gpio_set_mode(int gpio, int gpio_mode) | |||
457 | struct nmk_gpio_chip *nmk_chip; | 457 | struct nmk_gpio_chip *nmk_chip; |
458 | unsigned long flags; | 458 | unsigned long flags; |
459 | 459 | ||
460 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | 460 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
461 | if (!nmk_chip) | 461 | if (!nmk_chip) |
462 | return -EINVAL; | 462 | return -EINVAL; |
463 | 463 | ||
@@ -474,7 +474,7 @@ int nmk_gpio_get_mode(int gpio) | |||
474 | struct nmk_gpio_chip *nmk_chip; | 474 | struct nmk_gpio_chip *nmk_chip; |
475 | u32 afunc, bfunc, bit; | 475 | u32 afunc, bfunc, bit; |
476 | 476 | ||
477 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | 477 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
478 | if (!nmk_chip) | 478 | if (!nmk_chip) |
479 | return -EINVAL; | 479 | return -EINVAL; |
480 | 480 | ||
@@ -678,7 +678,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, | |||
678 | u32 status) | 678 | u32 status) |
679 | { | 679 | { |
680 | struct nmk_gpio_chip *nmk_chip; | 680 | struct nmk_gpio_chip *nmk_chip; |
681 | struct irq_chip *host_chip = get_irq_chip(irq); | 681 | struct irq_chip *host_chip = irq_get_chip(irq); |
682 | unsigned int first_irq; | 682 | unsigned int first_irq; |
683 | 683 | ||
684 | if (host_chip->irq_mask_ack) | 684 | if (host_chip->irq_mask_ack) |
@@ -689,7 +689,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, | |||
689 | host_chip->irq_ack(&desc->irq_data); | 689 | host_chip->irq_ack(&desc->irq_data); |
690 | } | 690 | } |
691 | 691 | ||
692 | nmk_chip = get_irq_data(irq); | 692 | nmk_chip = irq_get_handler_data(irq); |
693 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | 693 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); |
694 | while (status) { | 694 | while (status) { |
695 | int bit = __ffs(status); | 695 | int bit = __ffs(status); |
@@ -703,7 +703,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, | |||
703 | 703 | ||
704 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | 704 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
705 | { | 705 | { |
706 | struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); | 706 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
707 | u32 status = readl(nmk_chip->addr + NMK_GPIO_IS); | 707 | u32 status = readl(nmk_chip->addr + NMK_GPIO_IS); |
708 | 708 | ||
709 | __nmk_gpio_irq_handler(irq, desc, status); | 709 | __nmk_gpio_irq_handler(irq, desc, status); |
@@ -712,7 +712,7 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
712 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | 712 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, |
713 | struct irq_desc *desc) | 713 | struct irq_desc *desc) |
714 | { | 714 | { |
715 | struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); | 715 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
716 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); | 716 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
717 | 717 | ||
718 | __nmk_gpio_irq_handler(irq, desc, status); | 718 | __nmk_gpio_irq_handler(irq, desc, status); |
@@ -725,20 +725,20 @@ static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) | |||
725 | 725 | ||
726 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | 726 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); |
727 | for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { | 727 | for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { |
728 | set_irq_chip(i, &nmk_gpio_irq_chip); | 728 | irq_set_chip(i, &nmk_gpio_irq_chip); |
729 | set_irq_handler(i, handle_edge_irq); | 729 | irq_set_handler(i, handle_edge_irq); |
730 | set_irq_flags(i, IRQF_VALID); | 730 | set_irq_flags(i, IRQF_VALID); |
731 | set_irq_chip_data(i, nmk_chip); | 731 | irq_set_chip_data(i, nmk_chip); |
732 | set_irq_type(i, IRQ_TYPE_EDGE_FALLING); | 732 | irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); |
733 | } | 733 | } |
734 | 734 | ||
735 | set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); | 735 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
736 | set_irq_data(nmk_chip->parent_irq, nmk_chip); | 736 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); |
737 | 737 | ||
738 | if (nmk_chip->secondary_parent_irq >= 0) { | 738 | if (nmk_chip->secondary_parent_irq >= 0) { |
739 | set_irq_chained_handler(nmk_chip->secondary_parent_irq, | 739 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
740 | nmk_gpio_secondary_irq_handler); | 740 | nmk_gpio_secondary_irq_handler); |
741 | set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip); | 741 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
742 | } | 742 | } |
743 | 743 | ||
744 | return 0; | 744 | return 0; |
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index af07333e478e..d2adcdda23cf 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c | |||
@@ -758,9 +758,9 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) | |||
758 | spin_unlock_irqrestore(&bank->lock, flags); | 758 | spin_unlock_irqrestore(&bank->lock, flags); |
759 | 759 | ||
760 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | 760 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
761 | __set_irq_handler_unlocked(d->irq, handle_level_irq); | 761 | __irq_set_handler_locked(d->irq, handle_level_irq); |
762 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 762 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
763 | __set_irq_handler_unlocked(d->irq, handle_edge_irq); | 763 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
764 | 764 | ||
765 | return retval; | 765 | return retval; |
766 | } | 766 | } |
@@ -1140,7 +1140,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
1140 | 1140 | ||
1141 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 1141 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
1142 | 1142 | ||
1143 | bank = get_irq_data(irq); | 1143 | bank = irq_get_handler_data(irq); |
1144 | #ifdef CONFIG_ARCH_OMAP1 | 1144 | #ifdef CONFIG_ARCH_OMAP1 |
1145 | if (bank->method == METHOD_MPUIO) | 1145 | if (bank->method == METHOD_MPUIO) |
1146 | isr_reg = bank->base + | 1146 | isr_reg = bank->base + |
@@ -1666,16 +1666,16 @@ static void __init omap_gpio_chip_init(struct gpio_bank *bank) | |||
1666 | for (j = bank->virtual_irq_start; | 1666 | for (j = bank->virtual_irq_start; |
1667 | j < bank->virtual_irq_start + bank_width; j++) { | 1667 | j < bank->virtual_irq_start + bank_width; j++) { |
1668 | irq_set_lockdep_class(j, &gpio_lock_class); | 1668 | irq_set_lockdep_class(j, &gpio_lock_class); |
1669 | set_irq_chip_data(j, bank); | 1669 | irq_set_chip_data(j, bank); |
1670 | if (bank_is_mpuio(bank)) | 1670 | if (bank_is_mpuio(bank)) |
1671 | set_irq_chip(j, &mpuio_irq_chip); | 1671 | irq_set_chip(j, &mpuio_irq_chip); |
1672 | else | 1672 | else |
1673 | set_irq_chip(j, &gpio_irq_chip); | 1673 | irq_set_chip(j, &gpio_irq_chip); |
1674 | set_irq_handler(j, handle_simple_irq); | 1674 | irq_set_handler(j, handle_simple_irq); |
1675 | set_irq_flags(j, IRQF_VALID); | 1675 | set_irq_flags(j, IRQF_VALID); |
1676 | } | 1676 | } |
1677 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | 1677 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1678 | set_irq_data(bank->irq, bank); | 1678 | irq_set_handler_data(bank->irq, bank); |
1679 | } | 1679 | } |
1680 | 1680 | ||
1681 | static int __devinit omap_gpio_probe(struct platform_device *pdev) | 1681 | static int __devinit omap_gpio_probe(struct platform_device *pdev) |
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 222327b2c230..9ea0ae4b782f 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c | |||
@@ -474,9 +474,9 @@ void __init orion_gpio_init(int gpio_base, int ngpio, | |||
474 | for (i = 0; i < ngpio; i++) { | 474 | for (i = 0; i < ngpio; i++) { |
475 | unsigned int irq = secondary_irq_base + i; | 475 | unsigned int irq = secondary_irq_base + i; |
476 | 476 | ||
477 | set_irq_chip(irq, &orion_gpio_irq_chip); | 477 | irq_set_chip(irq, &orion_gpio_irq_chip); |
478 | set_irq_handler(irq, handle_level_irq); | 478 | irq_set_handler(irq, handle_level_irq); |
479 | set_irq_chip_data(irq, ochip); | 479 | irq_set_chip_data(irq, ochip); |
480 | irq_set_status_flags(irq, IRQ_LEVEL); | 480 | irq_set_status_flags(irq, IRQ_LEVEL); |
481 | set_irq_flags(irq, IRQF_VALID); | 481 | set_irq_flags(irq, IRQF_VALID); |
482 | } | 482 | } |
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index c163f9079e4b..aba3ffed9427 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c | |||
@@ -56,9 +56,9 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) | |||
56 | for (i = 0; i < 32; i++) { | 56 | for (i = 0; i < 32; i++) { |
57 | unsigned int irq = irq_start + i; | 57 | unsigned int irq = irq_start + i; |
58 | 58 | ||
59 | set_irq_chip(irq, &orion_irq_chip); | 59 | irq_set_chip(irq, &orion_irq_chip); |
60 | set_irq_chip_data(irq, maskaddr); | 60 | irq_set_chip_data(irq, maskaddr); |
61 | set_irq_handler(irq, handle_level_irq); | 61 | irq_set_handler(irq, handle_level_irq); |
62 | irq_set_status_flags(irq, IRQ_LEVEL); | 62 | irq_set_status_flags(irq, IRQ_LEVEL); |
63 | set_irq_flags(irq, IRQF_VALID); | 63 | set_irq_flags(irq, IRQF_VALID); |
64 | } | 64 | } |
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c index e7de6ae2a1e8..5e05467eec3d 100644 --- a/arch/arm/plat-pxa/gpio.c +++ b/arch/arm/plat-pxa/gpio.c | |||
@@ -284,13 +284,13 @@ void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) | |||
284 | } | 284 | } |
285 | 285 | ||
286 | for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { | 286 | for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { |
287 | set_irq_chip(irq, &pxa_muxed_gpio_chip); | 287 | irq_set_chip(irq, &pxa_muxed_gpio_chip); |
288 | set_irq_handler(irq, handle_edge_irq); | 288 | irq_set_handler(irq, handle_edge_irq); |
289 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 289 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
290 | } | 290 | } |
291 | 291 | ||
292 | /* Install handler for GPIO>=2 edge detect interrupts */ | 292 | /* Install handler for GPIO>=2 edge detect interrupts */ |
293 | set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler); | 293 | irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler); |
294 | pxa_muxed_gpio_chip.irq_set_wake = fn; | 294 | pxa_muxed_gpio_chip.irq_set_wake = fn; |
295 | } | 295 | } |
296 | 296 | ||
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index 4434cb56bd9a..c2a42d526635 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c | |||
@@ -592,8 +592,8 @@ void __init s3c24xx_init_irq(void) | |||
592 | case IRQ_UART1: | 592 | case IRQ_UART1: |
593 | case IRQ_UART2: | 593 | case IRQ_UART2: |
594 | case IRQ_ADCPARENT: | 594 | case IRQ_ADCPARENT: |
595 | set_irq_chip(irqno, &s3c_irq_level_chip); | 595 | irq_set_chip(irqno, &s3c_irq_level_chip); |
596 | set_irq_handler(irqno, handle_level_irq); | 596 | irq_set_handler(irqno, handle_level_irq); |
597 | break; | 597 | break; |
598 | 598 | ||
599 | case IRQ_RESERVED6: | 599 | case IRQ_RESERVED6: |
@@ -603,35 +603,35 @@ void __init s3c24xx_init_irq(void) | |||
603 | 603 | ||
604 | default: | 604 | default: |
605 | //irqdbf("registering irq %d (s3c irq)\n", irqno); | 605 | //irqdbf("registering irq %d (s3c irq)\n", irqno); |
606 | set_irq_chip(irqno, &s3c_irq_chip); | 606 | irq_set_chip(irqno, &s3c_irq_chip); |
607 | set_irq_handler(irqno, handle_edge_irq); | 607 | irq_set_handler(irqno, handle_edge_irq); |
608 | set_irq_flags(irqno, IRQF_VALID); | 608 | set_irq_flags(irqno, IRQF_VALID); |
609 | } | 609 | } |
610 | } | 610 | } |
611 | 611 | ||
612 | /* setup the cascade irq handlers */ | 612 | /* setup the cascade irq handlers */ |
613 | 613 | ||
614 | set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7); | 614 | irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7); |
615 | set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8); | 615 | irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8); |
616 | 616 | ||
617 | set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); | 617 | irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); |
618 | set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); | 618 | irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); |
619 | set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2); | 619 | irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2); |
620 | set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc); | 620 | irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc); |
621 | 621 | ||
622 | /* external interrupts */ | 622 | /* external interrupts */ |
623 | 623 | ||
624 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { | 624 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { |
625 | irqdbf("registering irq %d (ext int)\n", irqno); | 625 | irqdbf("registering irq %d (ext int)\n", irqno); |
626 | set_irq_chip(irqno, &s3c_irq_eint0t4); | 626 | irq_set_chip(irqno, &s3c_irq_eint0t4); |
627 | set_irq_handler(irqno, handle_edge_irq); | 627 | irq_set_handler(irqno, handle_edge_irq); |
628 | set_irq_flags(irqno, IRQF_VALID); | 628 | set_irq_flags(irqno, IRQF_VALID); |
629 | } | 629 | } |
630 | 630 | ||
631 | for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { | 631 | for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { |
632 | irqdbf("registering irq %d (extended s3c irq)\n", irqno); | 632 | irqdbf("registering irq %d (extended s3c irq)\n", irqno); |
633 | set_irq_chip(irqno, &s3c_irqext_chip); | 633 | irq_set_chip(irqno, &s3c_irqext_chip); |
634 | set_irq_handler(irqno, handle_edge_irq); | 634 | irq_set_handler(irqno, handle_edge_irq); |
635 | set_irq_flags(irqno, IRQF_VALID); | 635 | set_irq_flags(irqno, IRQF_VALID); |
636 | } | 636 | } |
637 | 637 | ||
@@ -641,29 +641,29 @@ void __init s3c24xx_init_irq(void) | |||
641 | 641 | ||
642 | for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { | 642 | for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { |
643 | irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); | 643 | irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); |
644 | set_irq_chip(irqno, &s3c_irq_uart0); | 644 | irq_set_chip(irqno, &s3c_irq_uart0); |
645 | set_irq_handler(irqno, handle_level_irq); | 645 | irq_set_handler(irqno, handle_level_irq); |
646 | set_irq_flags(irqno, IRQF_VALID); | 646 | set_irq_flags(irqno, IRQF_VALID); |
647 | } | 647 | } |
648 | 648 | ||
649 | for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { | 649 | for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { |
650 | irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); | 650 | irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); |
651 | set_irq_chip(irqno, &s3c_irq_uart1); | 651 | irq_set_chip(irqno, &s3c_irq_uart1); |
652 | set_irq_handler(irqno, handle_level_irq); | 652 | irq_set_handler(irqno, handle_level_irq); |
653 | set_irq_flags(irqno, IRQF_VALID); | 653 | set_irq_flags(irqno, IRQF_VALID); |
654 | } | 654 | } |
655 | 655 | ||
656 | for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { | 656 | for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { |
657 | irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); | 657 | irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); |
658 | set_irq_chip(irqno, &s3c_irq_uart2); | 658 | irq_set_chip(irqno, &s3c_irq_uart2); |
659 | set_irq_handler(irqno, handle_level_irq); | 659 | irq_set_handler(irqno, handle_level_irq); |
660 | set_irq_flags(irqno, IRQF_VALID); | 660 | set_irq_flags(irqno, IRQF_VALID); |
661 | } | 661 | } |
662 | 662 | ||
663 | for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { | 663 | for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { |
664 | irqdbf("registering irq %d (s3c adc irq)\n", irqno); | 664 | irqdbf("registering irq %d (s3c adc irq)\n", irqno); |
665 | set_irq_chip(irqno, &s3c_irq_adc); | 665 | irq_set_chip(irqno, &s3c_irq_adc); |
666 | set_irq_handler(irqno, handle_edge_irq); | 666 | irq_set_handler(irqno, handle_edge_irq); |
667 | set_irq_flags(irqno, IRQF_VALID); | 667 | set_irq_flags(irqno, IRQF_VALID); |
668 | } | 668 | } |
669 | 669 | ||
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c index 225aa25405db..f3d15e8c02c1 100644 --- a/arch/arm/plat-s5p/irq-eint.c +++ b/arch/arm/plat-s5p/irq-eint.c | |||
@@ -205,15 +205,15 @@ int __init s5p_init_irq_eint(void) | |||
205 | int irq; | 205 | int irq; |
206 | 206 | ||
207 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) | 207 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) |
208 | set_irq_chip(irq, &s5p_irq_vic_eint); | 208 | irq_set_chip(irq, &s5p_irq_vic_eint); |
209 | 209 | ||
210 | for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { | 210 | for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { |
211 | set_irq_chip(irq, &s5p_irq_eint); | 211 | irq_set_chip(irq, &s5p_irq_eint); |
212 | set_irq_handler(irq, handle_level_irq); | 212 | irq_set_handler(irq, handle_level_irq); |
213 | set_irq_flags(irq, IRQF_VALID); | 213 | set_irq_flags(irq, IRQF_VALID); |
214 | } | 214 | } |
215 | 215 | ||
216 | set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); | 216 | irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); |
217 | return 0; | 217 | return 0; |
218 | } | 218 | } |
219 | 219 | ||
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c index cd87d3256e03..46dd078147d8 100644 --- a/arch/arm/plat-s5p/irq-gpioint.c +++ b/arch/arm/plat-s5p/irq-gpioint.c | |||
@@ -43,13 +43,13 @@ LIST_HEAD(banks); | |||
43 | 43 | ||
44 | static int s5p_gpioint_get_offset(struct irq_data *data) | 44 | static int s5p_gpioint_get_offset(struct irq_data *data) |
45 | { | 45 | { |
46 | struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); | 46 | struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); |
47 | return data->irq - chip->irq_base; | 47 | return data->irq - chip->irq_base; |
48 | } | 48 | } |
49 | 49 | ||
50 | static void s5p_gpioint_ack(struct irq_data *data) | 50 | static void s5p_gpioint_ack(struct irq_data *data) |
51 | { | 51 | { |
52 | struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); | 52 | struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); |
53 | int group, offset, pend_offset; | 53 | int group, offset, pend_offset; |
54 | unsigned int value; | 54 | unsigned int value; |
55 | 55 | ||
@@ -64,7 +64,7 @@ static void s5p_gpioint_ack(struct irq_data *data) | |||
64 | 64 | ||
65 | static void s5p_gpioint_mask(struct irq_data *data) | 65 | static void s5p_gpioint_mask(struct irq_data *data) |
66 | { | 66 | { |
67 | struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); | 67 | struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); |
68 | int group, offset, mask_offset; | 68 | int group, offset, mask_offset; |
69 | unsigned int value; | 69 | unsigned int value; |
70 | 70 | ||
@@ -79,7 +79,7 @@ static void s5p_gpioint_mask(struct irq_data *data) | |||
79 | 79 | ||
80 | static void s5p_gpioint_unmask(struct irq_data *data) | 80 | static void s5p_gpioint_unmask(struct irq_data *data) |
81 | { | 81 | { |
82 | struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); | 82 | struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); |
83 | int group, offset, mask_offset; | 83 | int group, offset, mask_offset; |
84 | unsigned int value; | 84 | unsigned int value; |
85 | 85 | ||
@@ -100,7 +100,7 @@ static void s5p_gpioint_mask_ack(struct irq_data *data) | |||
100 | 100 | ||
101 | static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) | 101 | static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) |
102 | { | 102 | { |
103 | struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); | 103 | struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); |
104 | int group, offset, con_offset; | 104 | int group, offset, con_offset; |
105 | unsigned int value; | 105 | unsigned int value; |
106 | 106 | ||
@@ -149,7 +149,7 @@ static struct irq_chip s5p_gpioint = { | |||
149 | 149 | ||
150 | static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) | 150 | static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) |
151 | { | 151 | { |
152 | struct s5p_gpioint_bank *bank = get_irq_data(irq); | 152 | struct s5p_gpioint_bank *bank = irq_get_handler_data(irq); |
153 | int group, pend_offset, mask_offset; | 153 | int group, pend_offset, mask_offset; |
154 | unsigned int pend, mask; | 154 | unsigned int pend, mask; |
155 | 155 | ||
@@ -200,8 +200,8 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) | |||
200 | if (!bank->chips) | 200 | if (!bank->chips) |
201 | return -ENOMEM; | 201 | return -ENOMEM; |
202 | 202 | ||
203 | set_irq_chained_handler(bank->irq, s5p_gpioint_handler); | 203 | irq_set_chained_handler(bank->irq, s5p_gpioint_handler); |
204 | set_irq_data(bank->irq, bank); | 204 | irq_set_handler_data(bank->irq, bank); |
205 | bank->handler = s5p_gpioint_handler; | 205 | bank->handler = s5p_gpioint_handler; |
206 | printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n", | 206 | printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n", |
207 | bank->irq); | 207 | bank->irq); |
@@ -219,9 +219,9 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) | |||
219 | bank->chips[group - bank->start] = chip; | 219 | bank->chips[group - bank->start] = chip; |
220 | for (i = 0; i < chip->chip.ngpio; i++) { | 220 | for (i = 0; i < chip->chip.ngpio; i++) { |
221 | irq = chip->irq_base + i; | 221 | irq = chip->irq_base + i; |
222 | set_irq_chip(irq, &s5p_gpioint); | 222 | irq_set_chip(irq, &s5p_gpioint); |
223 | set_irq_data(irq, chip); | 223 | irq_set_handler_data(irq, chip); |
224 | set_irq_handler(irq, handle_level_irq); | 224 | irq_set_handler(irq, handle_level_irq); |
225 | set_irq_flags(irq, IRQF_VALID); | 225 | set_irq_flags(irq, IRQF_VALID); |
226 | } | 226 | } |
227 | return 0; | 227 | return 0; |
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c index b721c04a830e..3c064a0176b7 100644 --- a/arch/arm/plat-samsung/irq-uart.c +++ b/arch/arm/plat-samsung/irq-uart.c | |||
@@ -117,9 +117,9 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) | |||
117 | for (offs = 0; offs < 3; offs++) { | 117 | for (offs = 0; offs < 3; offs++) { |
118 | irq = uirq->base_irq + offs; | 118 | irq = uirq->base_irq + offs; |
119 | 119 | ||
120 | set_irq_chip(irq, &s3c_irq_uart); | 120 | irq_set_chip(irq, &s3c_irq_uart); |
121 | set_irq_chip_data(irq, uirq); | 121 | irq_set_chip_data(irq, uirq); |
122 | set_irq_handler(irq, handle_level_irq); | 122 | irq_set_handler(irq, handle_level_irq); |
123 | set_irq_flags(irq, IRQF_VALID); | 123 | set_irq_flags(irq, IRQF_VALID); |
124 | } | 124 | } |
125 | 125 | ||
diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c index 78189035e7f1..b4294cc140fa 100644 --- a/arch/arm/plat-spear/shirq.c +++ b/arch/arm/plat-spear/shirq.c | |||
@@ -68,7 +68,7 @@ static struct irq_chip shirq_chip = { | |||
68 | static void shirq_handler(unsigned irq, struct irq_desc *desc) | 68 | static void shirq_handler(unsigned irq, struct irq_desc *desc) |
69 | { | 69 | { |
70 | u32 i, val, mask; | 70 | u32 i, val, mask; |
71 | struct spear_shirq *shirq = get_irq_data(irq); | 71 | struct spear_shirq *shirq = irq_get_handler_data(irq); |
72 | 72 | ||
73 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 73 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
74 | while ((val = readl(shirq->regs.base + shirq->regs.status_reg) & | 74 | while ((val = readl(shirq->regs.base + shirq->regs.status_reg) & |
@@ -105,14 +105,14 @@ int spear_shirq_register(struct spear_shirq *shirq) | |||
105 | if (!shirq->dev_count) | 105 | if (!shirq->dev_count) |
106 | return -EINVAL; | 106 | return -EINVAL; |
107 | 107 | ||
108 | set_irq_chained_handler(shirq->irq, shirq_handler); | 108 | irq_set_chained_handler(shirq->irq, shirq_handler); |
109 | for (i = 0; i < shirq->dev_count; i++) { | 109 | for (i = 0; i < shirq->dev_count; i++) { |
110 | set_irq_chip(shirq->dev_config[i].virq, &shirq_chip); | 110 | irq_set_chip(shirq->dev_config[i].virq, &shirq_chip); |
111 | set_irq_handler(shirq->dev_config[i].virq, handle_simple_irq); | 111 | irq_set_handler(shirq->dev_config[i].virq, handle_simple_irq); |
112 | set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID); | 112 | set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID); |
113 | set_irq_chip_data(shirq->dev_config[i].virq, shirq); | 113 | irq_set_chip_data(shirq->dev_config[i].virq, shirq); |
114 | } | 114 | } |
115 | 115 | ||
116 | set_irq_data(shirq->irq, shirq); | 116 | irq_set_handler_data(shirq->irq, shirq); |
117 | return 0; | 117 | return 0; |
118 | } | 118 | } |
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c index aaa168683d4e..fc2e76488c16 100644 --- a/arch/arm/plat-stmp3xxx/irq.c +++ b/arch/arm/plat-stmp3xxx/irq.c | |||
@@ -35,8 +35,8 @@ void __init stmp3xxx_init_irq(struct irq_chip *chip) | |||
35 | /* Disable all interrupts initially */ | 35 | /* Disable all interrupts initially */ |
36 | for (i = 0; i < NR_REAL_IRQS; i++) { | 36 | for (i = 0; i < NR_REAL_IRQS; i++) { |
37 | chip->irq_mask(irq_get_irq_data(i)); | 37 | chip->irq_mask(irq_get_irq_data(i)); |
38 | set_irq_chip(i, chip); | 38 | irq_set_chip(i, chip); |
39 | set_irq_handler(i, handle_level_irq); | 39 | irq_set_handler(i, handle_level_irq); |
40 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 40 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
41 | } | 41 | } |
42 | 42 | ||
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c index c9c38e8d8b13..9057d932799a 100644 --- a/arch/arm/plat-stmp3xxx/pinmux.c +++ b/arch/arm/plat-stmp3xxx/pinmux.c | |||
@@ -489,7 +489,7 @@ static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset) | |||
489 | 489 | ||
490 | static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc) | 490 | static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc) |
491 | { | 491 | { |
492 | struct stmp3xxx_pinmux_bank *pm = get_irq_data(irq); | 492 | struct stmp3xxx_pinmux_bank *pm = irq_get_handler_data(irq); |
493 | int gpio_irq = pm->virq; | 493 | int gpio_irq = pm->virq; |
494 | u32 stat = __raw_readl(pm->irqstat); | 494 | u32 stat = __raw_readl(pm->irqstat); |
495 | 495 | ||
@@ -533,15 +533,15 @@ int __init stmp3xxx_pinmux_init(int virtual_irq_start) | |||
533 | 533 | ||
534 | for (virq = pm->virq; virq < pm->virq; virq++) { | 534 | for (virq = pm->virq; virq < pm->virq; virq++) { |
535 | gpio_irq_chip.irq_mask(irq_get_irq_data(virq)); | 535 | gpio_irq_chip.irq_mask(irq_get_irq_data(virq)); |
536 | set_irq_chip(virq, &gpio_irq_chip); | 536 | irq_set_chip(virq, &gpio_irq_chip); |
537 | set_irq_handler(virq, handle_level_irq); | 537 | irq_set_handler(virq, handle_level_irq); |
538 | set_irq_flags(virq, IRQF_VALID); | 538 | set_irq_flags(virq, IRQF_VALID); |
539 | } | 539 | } |
540 | r = gpiochip_add(&pm->chip); | 540 | r = gpiochip_add(&pm->chip); |
541 | if (r < 0) | 541 | if (r < 0) |
542 | break; | 542 | break; |
543 | set_irq_chained_handler(pm->irq, stmp3xxx_gpio_irq); | 543 | irq_set_chained_handler(pm->irq, stmp3xxx_gpio_irq); |
544 | set_irq_data(pm->irq, pm); | 544 | irq_set_handler_data(pm->irq, pm); |
545 | } | 545 | } |
546 | return r; | 546 | return r; |
547 | } | 547 | } |
diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c index 31d945d37e4f..f21d838044c8 100644 --- a/arch/arm/plat-versatile/fpga-irq.c +++ b/arch/arm/plat-versatile/fpga-irq.c | |||
@@ -30,7 +30,7 @@ static void fpga_irq_unmask(struct irq_data *d) | |||
30 | 30 | ||
31 | static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc) | 31 | static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc) |
32 | { | 32 | { |
33 | struct fpga_irq_data *f = get_irq_desc_data(desc); | 33 | struct fpga_irq_data *f = irq_desc_get_handler_data(desc); |
34 | u32 status = readl(f->base + IRQ_STATUS); | 34 | u32 status = readl(f->base + IRQ_STATUS); |
35 | 35 | ||
36 | if (status == 0) { | 36 | if (status == 0) { |
@@ -55,17 +55,17 @@ void __init fpga_irq_init(int parent_irq, u32 valid, struct fpga_irq_data *f) | |||
55 | f->chip.irq_unmask = fpga_irq_unmask; | 55 | f->chip.irq_unmask = fpga_irq_unmask; |
56 | 56 | ||
57 | if (parent_irq != -1) { | 57 | if (parent_irq != -1) { |
58 | set_irq_data(parent_irq, f); | 58 | irq_set_handler_data(parent_irq, f); |
59 | set_irq_chained_handler(parent_irq, fpga_irq_handle); | 59 | irq_set_chained_handler(parent_irq, fpga_irq_handle); |
60 | } | 60 | } |
61 | 61 | ||
62 | for (i = 0; i < 32; i++) { | 62 | for (i = 0; i < 32; i++) { |
63 | if (valid & (1 << i)) { | 63 | if (valid & (1 << i)) { |
64 | unsigned int irq = f->irq_start + i; | 64 | unsigned int irq = f->irq_start + i; |
65 | 65 | ||
66 | set_irq_chip_data(irq, f); | 66 | irq_set_chip_data(irq, f); |
67 | set_irq_chip(irq, &f->chip); | 67 | irq_set_chip(irq, &f->chip); |
68 | set_irq_handler(irq, handle_level_irq); | 68 | irq_set_handler(irq, handle_level_irq); |
69 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 69 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
70 | } | 70 | } |
71 | } | 71 | } |