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authorDan Williams <dan.j.williams@intel.com>2006-12-01 13:31:42 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-12-01 18:40:37 -0500
commitf5236225a3858b505221a59233af1f1158be9139 (patch)
tree1d59e171dae730ead66c21cb243d218df4ab457c /arch
parent0e5fdca7622eb950f42f97a1970670e00a739175 (diff)
[ARM] 3967/1: xsc3: make branch predication configurable on xsc3
Remove BTB_ENABLE from proc-xsc3.S On some early revisions of xsc3 enabling the branch target buffer can cause crashes, see erratum #42. Cc: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mm/Kconfig2
-rw-r--r--arch/arm/mm/proc-xsc3.S7
2 files changed, 1 insertions, 8 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c0bfb8212b77..efebd6050285 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -580,7 +580,7 @@ config CPU_CACHE_ROUND_ROBIN
580 580
581config CPU_BPREDICT_DISABLE 581config CPU_BPREDICT_DISABLE
582 bool "Disable branch prediction" 582 bool "Disable branch prediction"
583 depends on CPU_ARM1020 || CPU_V6 583 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3
584 help 584 help
585 Say Y here to disable branch prediction. If unsure, say N. 585 Say Y here to disable branch prediction. If unsure, say N.
586 586
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 85c3523d0a95..1ef564d0957f 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -57,11 +57,6 @@
57#define L2_CACHE_ENABLE 1 57#define L2_CACHE_ENABLE 1
58 58
59/* 59/*
60 * Enable the Branch Target Buffer (can cause crashes, see erratum #42.)
61 */
62#define BTB_ENABLE 0
63
64/*
65 * This macro is used to wait for a CP15 write and is needed 60 * This macro is used to wait for a CP15 write and is needed
66 * when we have to ensure that the last operation to the co-pro 61 * when we have to ensure that the last operation to the co-pro
67 * was completed before continuing with operation. 62 * was completed before continuing with operation.
@@ -434,9 +429,7 @@ __xsc3_setup:
434 mrc p15, 0, r0, c1, c0, 0 @ get control register 429 mrc p15, 0, r0, c1, c0, 0 @ get control register
435 bic r0, r0, r5 @ .... .... .... ..A. 430 bic r0, r0, r5 @ .... .... .... ..A.
436 orr r0, r0, r6 @ .... .... .... .C.M 431 orr r0, r0, r6 @ .... .... .... .C.M
437#if BTB_ENABLE
438 orr r0, r0, #0x00000800 @ ..VI Z..S .... .... 432 orr r0, r0, #0x00000800 @ ..VI Z..S .... ....
439#endif
440#if L2_CACHE_ENABLE 433#if L2_CACHE_ENABLE
441 orr r0, r0, #0x04000000 @ L2 enable 434 orr r0, r0, #0x04000000 @ L2 enable
442#endif 435#endif