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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2006-05-26 11:44:54 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-06-05 19:15:13 -0400
commit9370b35175ca43fad7d24bc7b391473f3becbee8 (patch)
tree4d1f3e7a0708c86da26720288711f8702b00b601 /arch
parentcac4bcbce0e800f2219a27b66aaeb4a33f2e3dbc (diff)
[MIPS] Save write-only Config.OD from being clobbered
Save the Config.OD bit from being clobbered by coherency_setup(). This bit, when set, fixes various errata in the early steppings of Au1x00 SOCs. Unfortunately, the bit was write-only on the most early of them. In addition, also restore the bit after a wakeup from sleep. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/au1000/common/sleeper.S5
-rw-r--r--arch/mips/mm/c-r4k.c34
2 files changed, 39 insertions, 0 deletions
diff --git a/arch/mips/au1000/common/sleeper.S b/arch/mips/au1000/common/sleeper.S
index 44dac3b0df3b..683d9da84b66 100644
--- a/arch/mips/au1000/common/sleeper.S
+++ b/arch/mips/au1000/common/sleeper.S
@@ -112,6 +112,11 @@ sdsleep:
112 mtc0 k0, CP0_PAGEMASK 112 mtc0 k0, CP0_PAGEMASK
113 lw k0, 0x14(sp) 113 lw k0, 0x14(sp)
114 mtc0 k0, CP0_CONFIG 114 mtc0 k0, CP0_CONFIG
115
116 /* We need to catch the ealry Alchemy SOCs with
117 * the write-only Config[OD] bit and set it back to one...
118 */
119 jal au1x00_fixup_config_od
115 lw $1, PT_R1(sp) 120 lw $1, PT_R1(sp)
116 lw $2, PT_R2(sp) 121 lw $2, PT_R2(sp)
117 lw $3, PT_R3(sp) 122 lw $3, PT_R3(sp)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6b3541769602..4a43924cd4fc 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1161,6 +1161,31 @@ static void __init setup_scache(void)
1161 c->options |= MIPS_CPU_SUBSET_CACHES; 1161 c->options |= MIPS_CPU_SUBSET_CACHES;
1162} 1162}
1163 1163
1164void au1x00_fixup_config_od(void)
1165{
1166 /*
1167 * c0_config.od (bit 19) was write only (and read as 0)
1168 * on the early revisions of Alchemy SOCs. It disables the bus
1169 * transaction overlapping and needs to be set to fix various errata.
1170 */
1171 switch (read_c0_prid()) {
1172 case 0x00030100: /* Au1000 DA */
1173 case 0x00030201: /* Au1000 HA */
1174 case 0x00030202: /* Au1000 HB */
1175 case 0x01030200: /* Au1500 AB */
1176 /*
1177 * Au1100 errata actually keeps silence about this bit, so we set it
1178 * just in case for those revisions that require it to be set according
1179 * to arch/mips/au1000/common/cputable.c
1180 */
1181 case 0x02030200: /* Au1100 AB */
1182 case 0x02030201: /* Au1100 BA */
1183 case 0x02030202: /* Au1100 BC */
1184 set_c0_config(1 << 19);
1185 break;
1186 }
1187}
1188
1164static inline void coherency_setup(void) 1189static inline void coherency_setup(void)
1165{ 1190{
1166 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); 1191 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
@@ -1181,6 +1206,15 @@ static inline void coherency_setup(void)
1181 case CPU_R4400MC: 1206 case CPU_R4400MC:
1182 clear_c0_config(CONF_CU); 1207 clear_c0_config(CONF_CU);
1183 break; 1208 break;
1209 /*
1210 * We need to catch the ealry Alchemy SOCs with
1211 * the write-only co_config.od bit and set it back to one...
1212 */
1213 case CPU_AU1000: /* rev. DA, HA, HB */
1214 case CPU_AU1100: /* rev. AB, BA, BC ?? */
1215 case CPU_AU1500: /* rev. AB */
1216 au1x00_fixup_config_od();
1217 break;
1184 } 1218 }
1185} 1219}
1186 1220