Thumb-2: Add some .align statements to the .S files

Since the Thumb-2 instructions can be 16-bit wide, data in the .text
sections may not be aligned to a 32-bit word and this leads to unaligned
exceptions. This patch does not affect the ARM code generation.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

5 files changed, 13 insertions, 0 deletions

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 4515728c5345..82f5fcfd9567 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -291,6 +291,7 @@ wont_overwrite:	mov	r0, r4
                 bl      decompress_kernel
                 b       call_kernel
 
+                .align  2
                 .type   LC0, #object
 LC0:            .word   LC0                     @ r1
                 .word   __bss_start             @ r2
@@ -589,6 +590,7 @@ call_cache_fn:	adr	r12, proc_types
  * methods.  Writeback caches _must_ have the flush method
  * defined.
  */
+                .align  2
                 .type   proc_types,#object
 proc_types:
                 .word   0x41560600              @ ARM6/610
@@ -945,6 +947,7 @@ __armv3_mpu_cache_flush:
  * memory, which again must be relocatable.
  */
 #ifdef DEBUG
+                .align  2
                 .type   phexbuf,#object
 phexbuf:        .space  12
                 .size   phexbuf, . - phexbuf
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index fc8af43c5000..0befd1cabf45 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -1065,6 +1065,10 @@ vector_\name:
         ldr     lr, [pc, lr, lsl #2]
         movs    pc, lr                  @ branch to handler in SVC mode
 ENDPROC(vector_\name)
+
+        .align  2
+        @ handler addresses follow this label
+1:
         .endm
 
         .globl  __stubs_start
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 991952c644d1..dbfaef07a1f4 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -14,6 +14,7 @@
 #define ATAG_CORE 0x54410001
 #define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2)
 
+        .align  2
         .type   __switch_data, %object
 __switch_data:
         .long   __mmap_switched
@@ -185,6 +186,7 @@ ENDPROC(lookup_processor_type)
  * Look in <asm/procinfo.h> and arch/arm/kernel/arch.[ch] for
  * more information about the __proc_info and __arch_info structures.
  */
+        .align  2
         .long   __proc_info_begin
         .long   __proc_info_end
 3:      .long   .
diff --git a/arch/arm/lib/sha1.S b/arch/arm/lib/sha1.S
index a16fb208c841..09b548cac1a4 100644
--- a/arch/arm/lib/sha1.S
+++ b/arch/arm/lib/sha1.S
@@ -187,6 +187,7 @@ ENTRY(sha_transform)
 
 ENDPROC(sha_transform)
 
+        .align  2
 .L_sha_K:
         .word   0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6
 
@@ -195,6 +196,7 @@ ENDPROC(sha_transform)
  * void sha_init(__u32 *buf)
  */
 
+        .align  2
 .L_sha_initial_digest:
         .word   0x67452301, 0xefcdab89, 0x98badcfe, 0x10325476, 0xc3d2e1f0
 
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index a2bed62aec21..4fa9903b83cf 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -42,6 +42,7 @@ ENTRY(vfp_null_entry)
         mov     pc, lr
 ENDPROC(vfp_null_entry)
 
+        .align  2
 .LCvfp:
         .word   vfp_vector
 
@@ -61,6 +62,7 @@ ENTRY(vfp_testing_entry)
         mov     pc, r9                  @ we have handled the fault
 ENDPROC(vfp_testing_entry)
 
+        .align  2
 VFP_arch_address:
         .word   VFP_arch