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authorRoland Stigge <stigge@antcom.de>2012-10-18 12:06:10 -0400
committerSascha Hauer <s.hauer@pengutronix.de>2012-11-16 10:21:48 -0500
commiteebdb17287443408c979dbc1cee594f6b770bc68 (patch)
tree598dece2668f4e82996644d4915c73eabd3be5ec /arch
parent3ab3a350200c14350220fffde893f3afb640fd25 (diff)
ARM: mach-imx: Support for DryIce RTC in i.MX53
This patch enables support for i.MX53 in addition to i.MX25 by providing a dummy clock on i.MX53 since this one doesn't have a separate clock for internal RTC but the driver requests one. Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index abb71f6b4d60..6cb97952bbfb 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -466,6 +466,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
466 clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can"); 466 clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
467 clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can"); 467 clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
468 clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can"); 468 clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
469 clk_register_clkdev(clk[dummy], NULL, "53fa4000.rtc");
469 470
470 /* set SDHC root clock to 200MHZ*/ 471 /* set SDHC root clock to 200MHZ*/
471 clk_set_rate(clk[esdhc_a_podf], 200000000); 472 clk_set_rate(clk[esdhc_a_podf], 200000000);