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authorTony Lindgren <tony@atomide.com>2011-03-29 18:54:48 -0400
committerTony Lindgren <tony@atomide.com>2011-06-20 04:25:39 -0400
commitec97489d199b3dcfc44042ccf89b37a264d14565 (patch)
treea57340d2bc3043cdf45ad0c2f9125c6b8809f964 /arch
parente74984e46e899c22137a385869fb4f3ae756e3df (diff)
omap: Move dmtimer defines to dmtimer.h
These will be needed when dmtimer platform init code gets split for omap1 and omap2+. These will also be needed for separate sys_timer init and driver init for the rest of the hardware timers in the following patches. No functional changes. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/plat-omap/dmtimer.c121
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h125
2 files changed, 125 insertions, 121 deletions
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index ee9f6ebba29b..dfdc3b2e3201 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -41,127 +41,6 @@
41#include <plat/dmtimer.h> 41#include <plat/dmtimer.h>
42#include <mach/irqs.h> 42#include <mach/irqs.h>
43 43
44/* register offsets */
45#define _OMAP_TIMER_ID_OFFSET 0x00
46#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
47#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
48#define _OMAP_TIMER_STAT_OFFSET 0x18
49#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
50#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
51#define _OMAP_TIMER_CTRL_OFFSET 0x24
52#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
53#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
54#define OMAP_TIMER_CTRL_PT (1 << 12)
55#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
56#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
57#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
58#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
59#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
60#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
61#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
62#define OMAP_TIMER_CTRL_POSTED (1 << 2)
63#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
64#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
65#define _OMAP_TIMER_COUNTER_OFFSET 0x28
66#define _OMAP_TIMER_LOAD_OFFSET 0x2c
67#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
68#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
69#define WP_NONE 0 /* no write pending bit */
70#define WP_TCLR (1 << 0)
71#define WP_TCRR (1 << 1)
72#define WP_TLDR (1 << 2)
73#define WP_TTGR (1 << 3)
74#define WP_TMAR (1 << 4)
75#define WP_TPIR (1 << 5)
76#define WP_TNIR (1 << 6)
77#define WP_TCVR (1 << 7)
78#define WP_TOCR (1 << 8)
79#define WP_TOWR (1 << 9)
80#define _OMAP_TIMER_MATCH_OFFSET 0x38
81#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
82#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
83#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
84#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
85#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
86#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
87#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
88#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
89
90/* register offsets with the write pending bit encoded */
91#define WPSHIFT 16
92
93#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
94 | (WP_NONE << WPSHIFT))
95
96#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
97 | (WP_NONE << WPSHIFT))
98
99#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
100 | (WP_NONE << WPSHIFT))
101
102#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
103 | (WP_NONE << WPSHIFT))
104
105#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
106 | (WP_NONE << WPSHIFT))
107
108#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
109 | (WP_NONE << WPSHIFT))
110
111#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
112 | (WP_TCLR << WPSHIFT))
113
114#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
115 | (WP_TCRR << WPSHIFT))
116
117#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
118 | (WP_TLDR << WPSHIFT))
119
120#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
121 | (WP_TTGR << WPSHIFT))
122
123#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
124 | (WP_NONE << WPSHIFT))
125
126#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
127 | (WP_TMAR << WPSHIFT))
128
129#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
130 | (WP_NONE << WPSHIFT))
131
132#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
133 | (WP_NONE << WPSHIFT))
134
135#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
136 | (WP_NONE << WPSHIFT))
137
138#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
139 | (WP_TPIR << WPSHIFT))
140
141#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
142 | (WP_TNIR << WPSHIFT))
143
144#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
145 | (WP_TCVR << WPSHIFT))
146
147#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
148 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
149
150#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
151 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
152
153struct omap_dm_timer {
154 unsigned long phys_base;
155 int irq;
156#ifdef CONFIG_ARCH_OMAP2PLUS
157 struct clk *iclk, *fclk;
158#endif
159 void __iomem *io_base;
160 unsigned reserved:1;
161 unsigned enabled:1;
162 unsigned posted:1;
163};
164
165static int dm_timer_count; 44static int dm_timer_count;
166 45
167#ifdef CONFIG_ARCH_OMAP1 46#ifdef CONFIG_ARCH_OMAP1
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 330bd17bb5e7..32031056165d 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -92,5 +92,130 @@ void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value
92 92
93int omap_dm_timers_active(void); 93int omap_dm_timers_active(void);
94 94
95/*
96 * Do not use the defines below, they are not needed. They should be only
97 * used by dmtimer.c and sys_timer related code.
98 */
99
100/* register offsets */
101#define _OMAP_TIMER_ID_OFFSET 0x00
102#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
103#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
104#define _OMAP_TIMER_STAT_OFFSET 0x18
105#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
106#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
107#define _OMAP_TIMER_CTRL_OFFSET 0x24
108#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
109#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
110#define OMAP_TIMER_CTRL_PT (1 << 12)
111#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
112#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
113#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
114#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
115#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
116#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
117#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
118#define OMAP_TIMER_CTRL_POSTED (1 << 2)
119#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
120#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
121#define _OMAP_TIMER_COUNTER_OFFSET 0x28
122#define _OMAP_TIMER_LOAD_OFFSET 0x2c
123#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
124#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
125#define WP_NONE 0 /* no write pending bit */
126#define WP_TCLR (1 << 0)
127#define WP_TCRR (1 << 1)
128#define WP_TLDR (1 << 2)
129#define WP_TTGR (1 << 3)
130#define WP_TMAR (1 << 4)
131#define WP_TPIR (1 << 5)
132#define WP_TNIR (1 << 6)
133#define WP_TCVR (1 << 7)
134#define WP_TOCR (1 << 8)
135#define WP_TOWR (1 << 9)
136#define _OMAP_TIMER_MATCH_OFFSET 0x38
137#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
138#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
139#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
140#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
141#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
142#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
143#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
144#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
145
146/* register offsets with the write pending bit encoded */
147#define WPSHIFT 16
148
149#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
150 | (WP_NONE << WPSHIFT))
151
152#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
153 | (WP_NONE << WPSHIFT))
154
155#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
156 | (WP_NONE << WPSHIFT))
157
158#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
159 | (WP_NONE << WPSHIFT))
160
161#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
162 | (WP_NONE << WPSHIFT))
163
164#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
165 | (WP_NONE << WPSHIFT))
166
167#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
168 | (WP_TCLR << WPSHIFT))
169
170#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
171 | (WP_TCRR << WPSHIFT))
172
173#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
174 | (WP_TLDR << WPSHIFT))
175
176#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
177 | (WP_TTGR << WPSHIFT))
178
179#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
180 | (WP_NONE << WPSHIFT))
181
182#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
183 | (WP_TMAR << WPSHIFT))
184
185#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
186 | (WP_NONE << WPSHIFT))
187
188#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
189 | (WP_NONE << WPSHIFT))
190
191#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
192 | (WP_NONE << WPSHIFT))
193
194#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
195 | (WP_TPIR << WPSHIFT))
196
197#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
198 | (WP_TNIR << WPSHIFT))
199
200#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
201 | (WP_TCVR << WPSHIFT))
202
203#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
204 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
205
206#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
207 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
208
209struct omap_dm_timer {
210 unsigned long phys_base;
211 int irq;
212#ifdef CONFIG_ARCH_OMAP2PLUS
213 struct clk *iclk, *fclk;
214#endif
215 void __iomem *io_base;
216 unsigned reserved:1;
217 unsigned enabled:1;
218 unsigned posted:1;
219};
95 220
96#endif /* __ASM_ARCH_DMTIMER_H */ 221#endif /* __ASM_ARCH_DMTIMER_H */
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