diff options
author | Jarkko Nikula <jhnikula@gmail.com> | 2011-06-14 07:23:51 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2011-06-29 06:23:40 -0400 |
commit | e285bca6d926b17ad6343f20ef174799785e4235 (patch) | |
tree | 57bfb6acb497a2fb907e3685c60d510b0dca9020 /arch | |
parent | d19f579aae74d6df9276e244716cedd96895d566 (diff) |
omap: mcbsp: Drop SPI mode support
We haven't seen any use for the SPI API in McBSP driver over the years. More
over, Peter Ujfalusi <peter.ujfalusi@ti.com> noticed that SPI mode is not
even supported since OMAP2430 so it's very unlikely that we'll see any use
for it in the future either.
Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/plat-omap/include/plat/mcbsp.h | 37 | ||||
-rw-r--r-- | arch/arm/plat-omap/mcbsp.c | 214 |
2 files changed, 0 insertions, 251 deletions
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index f8f690ab2997..3fc75a8fe21f 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h | |||
@@ -353,38 +353,6 @@ typedef enum { | |||
353 | OMAP_MCBSP_WORD_32, | 353 | OMAP_MCBSP_WORD_32, |
354 | } omap_mcbsp_word_length; | 354 | } omap_mcbsp_word_length; |
355 | 355 | ||
356 | typedef enum { | ||
357 | OMAP_MCBSP_CLK_RISING = 0, | ||
358 | OMAP_MCBSP_CLK_FALLING, | ||
359 | } omap_mcbsp_clk_polarity; | ||
360 | |||
361 | typedef enum { | ||
362 | OMAP_MCBSP_FS_ACTIVE_HIGH = 0, | ||
363 | OMAP_MCBSP_FS_ACTIVE_LOW, | ||
364 | } omap_mcbsp_fs_polarity; | ||
365 | |||
366 | typedef enum { | ||
367 | OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0, | ||
368 | OMAP_MCBSP_CLK_STP_MODE_DELAY, | ||
369 | } omap_mcbsp_clk_stp_mode; | ||
370 | |||
371 | |||
372 | /******* SPI specific mode **********/ | ||
373 | typedef enum { | ||
374 | OMAP_MCBSP_SPI_MASTER = 0, | ||
375 | OMAP_MCBSP_SPI_SLAVE, | ||
376 | } omap_mcbsp_spi_mode; | ||
377 | |||
378 | struct omap_mcbsp_spi_cfg { | ||
379 | omap_mcbsp_spi_mode spi_mode; | ||
380 | omap_mcbsp_clk_polarity rx_clock_polarity; | ||
381 | omap_mcbsp_clk_polarity tx_clock_polarity; | ||
382 | omap_mcbsp_fs_polarity fsx_polarity; | ||
383 | u8 clk_div; | ||
384 | omap_mcbsp_clk_stp_mode clk_stp_mode; | ||
385 | omap_mcbsp_word_length word_length; | ||
386 | }; | ||
387 | |||
388 | /* Platform specific configuration */ | 356 | /* Platform specific configuration */ |
389 | struct omap_mcbsp_ops { | 357 | struct omap_mcbsp_ops { |
390 | void (*request)(unsigned int); | 358 | void (*request)(unsigned int); |
@@ -504,14 +472,9 @@ u32 omap_mcbsp_recv_word(unsigned int id); | |||
504 | 472 | ||
505 | int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); | 473 | int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); |
506 | int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); | 474 | int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); |
507 | int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word); | ||
508 | int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word); | ||
509 | |||
510 | 475 | ||
511 | /* McBSP functional clock source changing function */ | 476 | /* McBSP functional clock source changing function */ |
512 | extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id); | 477 | extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id); |
513 | /* SPI specific API */ | ||
514 | void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); | ||
515 | 478 | ||
516 | /* Polled read/write functions */ | 479 | /* Polled read/write functions */ |
517 | int omap_mcbsp_pollread(unsigned int id, u16 * buf); | 480 | int omap_mcbsp_pollread(unsigned int id, u16 * buf); |
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 5587acf0eb2c..1de27243385f 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c | |||
@@ -1175,147 +1175,6 @@ u32 omap_mcbsp_recv_word(unsigned int id) | |||
1175 | } | 1175 | } |
1176 | EXPORT_SYMBOL(omap_mcbsp_recv_word); | 1176 | EXPORT_SYMBOL(omap_mcbsp_recv_word); |
1177 | 1177 | ||
1178 | int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) | ||
1179 | { | ||
1180 | struct omap_mcbsp *mcbsp; | ||
1181 | omap_mcbsp_word_length tx_word_length; | ||
1182 | omap_mcbsp_word_length rx_word_length; | ||
1183 | u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; | ||
1184 | |||
1185 | if (!omap_mcbsp_check_valid_id(id)) { | ||
1186 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | ||
1187 | return -ENODEV; | ||
1188 | } | ||
1189 | mcbsp = id_to_mcbsp_ptr(id); | ||
1190 | tx_word_length = mcbsp->tx_word_length; | ||
1191 | rx_word_length = mcbsp->rx_word_length; | ||
1192 | |||
1193 | if (tx_word_length != rx_word_length) | ||
1194 | return -EINVAL; | ||
1195 | |||
1196 | /* First we wait for the transmitter to be ready */ | ||
1197 | spcr2 = MCBSP_READ(mcbsp, SPCR2); | ||
1198 | while (!(spcr2 & XRDY)) { | ||
1199 | spcr2 = MCBSP_READ(mcbsp, SPCR2); | ||
1200 | if (attempts++ > 1000) { | ||
1201 | /* We must reset the transmitter */ | ||
1202 | MCBSP_WRITE(mcbsp, SPCR2, | ||
1203 | MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST)); | ||
1204 | udelay(10); | ||
1205 | MCBSP_WRITE(mcbsp, SPCR2, | ||
1206 | MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST); | ||
1207 | udelay(10); | ||
1208 | dev_err(mcbsp->dev, "McBSP%d transmitter not " | ||
1209 | "ready\n", mcbsp->id); | ||
1210 | return -EAGAIN; | ||
1211 | } | ||
1212 | } | ||
1213 | |||
1214 | /* Now we can push the data */ | ||
1215 | if (tx_word_length > OMAP_MCBSP_WORD_16) | ||
1216 | MCBSP_WRITE(mcbsp, DXR2, word >> 16); | ||
1217 | MCBSP_WRITE(mcbsp, DXR1, word & 0xffff); | ||
1218 | |||
1219 | /* We wait for the receiver to be ready */ | ||
1220 | spcr1 = MCBSP_READ(mcbsp, SPCR1); | ||
1221 | while (!(spcr1 & RRDY)) { | ||
1222 | spcr1 = MCBSP_READ(mcbsp, SPCR1); | ||
1223 | if (attempts++ > 1000) { | ||
1224 | /* We must reset the receiver */ | ||
1225 | MCBSP_WRITE(mcbsp, SPCR1, | ||
1226 | MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST)); | ||
1227 | udelay(10); | ||
1228 | MCBSP_WRITE(mcbsp, SPCR1, | ||
1229 | MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST); | ||
1230 | udelay(10); | ||
1231 | dev_err(mcbsp->dev, "McBSP%d receiver not " | ||
1232 | "ready\n", mcbsp->id); | ||
1233 | return -EAGAIN; | ||
1234 | } | ||
1235 | } | ||
1236 | |||
1237 | /* Receiver is ready, let's read the dummy data */ | ||
1238 | if (rx_word_length > OMAP_MCBSP_WORD_16) | ||
1239 | word_msb = MCBSP_READ(mcbsp, DRR2); | ||
1240 | word_lsb = MCBSP_READ(mcbsp, DRR1); | ||
1241 | |||
1242 | return 0; | ||
1243 | } | ||
1244 | EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll); | ||
1245 | |||
1246 | int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) | ||
1247 | { | ||
1248 | struct omap_mcbsp *mcbsp; | ||
1249 | u32 clock_word = 0; | ||
1250 | omap_mcbsp_word_length tx_word_length; | ||
1251 | omap_mcbsp_word_length rx_word_length; | ||
1252 | u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; | ||
1253 | |||
1254 | if (!omap_mcbsp_check_valid_id(id)) { | ||
1255 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | ||
1256 | return -ENODEV; | ||
1257 | } | ||
1258 | |||
1259 | mcbsp = id_to_mcbsp_ptr(id); | ||
1260 | |||
1261 | tx_word_length = mcbsp->tx_word_length; | ||
1262 | rx_word_length = mcbsp->rx_word_length; | ||
1263 | |||
1264 | if (tx_word_length != rx_word_length) | ||
1265 | return -EINVAL; | ||
1266 | |||
1267 | /* First we wait for the transmitter to be ready */ | ||
1268 | spcr2 = MCBSP_READ(mcbsp, SPCR2); | ||
1269 | while (!(spcr2 & XRDY)) { | ||
1270 | spcr2 = MCBSP_READ(mcbsp, SPCR2); | ||
1271 | if (attempts++ > 1000) { | ||
1272 | /* We must reset the transmitter */ | ||
1273 | MCBSP_WRITE(mcbsp, SPCR2, | ||
1274 | MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST)); | ||
1275 | udelay(10); | ||
1276 | MCBSP_WRITE(mcbsp, SPCR2, | ||
1277 | MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST); | ||
1278 | udelay(10); | ||
1279 | dev_err(mcbsp->dev, "McBSP%d transmitter not " | ||
1280 | "ready\n", mcbsp->id); | ||
1281 | return -EAGAIN; | ||
1282 | } | ||
1283 | } | ||
1284 | |||
1285 | /* We first need to enable the bus clock */ | ||
1286 | if (tx_word_length > OMAP_MCBSP_WORD_16) | ||
1287 | MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16); | ||
1288 | MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff); | ||
1289 | |||
1290 | /* We wait for the receiver to be ready */ | ||
1291 | spcr1 = MCBSP_READ(mcbsp, SPCR1); | ||
1292 | while (!(spcr1 & RRDY)) { | ||
1293 | spcr1 = MCBSP_READ(mcbsp, SPCR1); | ||
1294 | if (attempts++ > 1000) { | ||
1295 | /* We must reset the receiver */ | ||
1296 | MCBSP_WRITE(mcbsp, SPCR1, | ||
1297 | MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST)); | ||
1298 | udelay(10); | ||
1299 | MCBSP_WRITE(mcbsp, SPCR1, | ||
1300 | MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST); | ||
1301 | udelay(10); | ||
1302 | dev_err(mcbsp->dev, "McBSP%d receiver not " | ||
1303 | "ready\n", mcbsp->id); | ||
1304 | return -EAGAIN; | ||
1305 | } | ||
1306 | } | ||
1307 | |||
1308 | /* Receiver is ready, there is something for us */ | ||
1309 | if (rx_word_length > OMAP_MCBSP_WORD_16) | ||
1310 | word_msb = MCBSP_READ(mcbsp, DRR2); | ||
1311 | word_lsb = MCBSP_READ(mcbsp, DRR1); | ||
1312 | |||
1313 | word[0] = (word_lsb | (word_msb << 16)); | ||
1314 | |||
1315 | return 0; | ||
1316 | } | ||
1317 | EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll); | ||
1318 | |||
1319 | /* | 1178 | /* |
1320 | * Simple DMA based buffer rx/tx routines. | 1179 | * Simple DMA based buffer rx/tx routines. |
1321 | * Nothing fancy, just a single buffer tx/rx through DMA. | 1180 | * Nothing fancy, just a single buffer tx/rx through DMA. |
@@ -1449,79 +1308,6 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, | |||
1449 | } | 1308 | } |
1450 | EXPORT_SYMBOL(omap_mcbsp_recv_buffer); | 1309 | EXPORT_SYMBOL(omap_mcbsp_recv_buffer); |
1451 | 1310 | ||
1452 | /* | ||
1453 | * SPI wrapper. | ||
1454 | * Since SPI setup is much simpler than the generic McBSP one, | ||
1455 | * this wrapper just need an omap_mcbsp_spi_cfg structure as an input. | ||
1456 | * Once this is done, you can call omap_mcbsp_start(). | ||
1457 | */ | ||
1458 | void omap_mcbsp_set_spi_mode(unsigned int id, | ||
1459 | const struct omap_mcbsp_spi_cfg *spi_cfg) | ||
1460 | { | ||
1461 | struct omap_mcbsp *mcbsp; | ||
1462 | struct omap_mcbsp_reg_cfg mcbsp_cfg; | ||
1463 | |||
1464 | if (!omap_mcbsp_check_valid_id(id)) { | ||
1465 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | ||
1466 | return; | ||
1467 | } | ||
1468 | mcbsp = id_to_mcbsp_ptr(id); | ||
1469 | |||
1470 | memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg)); | ||
1471 | |||
1472 | /* SPI has only one frame */ | ||
1473 | mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0)); | ||
1474 | mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0)); | ||
1475 | |||
1476 | /* Clock stop mode */ | ||
1477 | if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY) | ||
1478 | mcbsp_cfg.spcr1 |= (1 << 12); | ||
1479 | else | ||
1480 | mcbsp_cfg.spcr1 |= (3 << 11); | ||
1481 | |||
1482 | /* Set clock parities */ | ||
1483 | if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING) | ||
1484 | mcbsp_cfg.pcr0 |= CLKRP; | ||
1485 | else | ||
1486 | mcbsp_cfg.pcr0 &= ~CLKRP; | ||
1487 | |||
1488 | if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING) | ||
1489 | mcbsp_cfg.pcr0 &= ~CLKXP; | ||
1490 | else | ||
1491 | mcbsp_cfg.pcr0 |= CLKXP; | ||
1492 | |||
1493 | /* Set SCLKME to 0 and CLKSM to 1 */ | ||
1494 | mcbsp_cfg.pcr0 &= ~SCLKME; | ||
1495 | mcbsp_cfg.srgr2 |= CLKSM; | ||
1496 | |||
1497 | /* Set FSXP */ | ||
1498 | if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH) | ||
1499 | mcbsp_cfg.pcr0 &= ~FSXP; | ||
1500 | else | ||
1501 | mcbsp_cfg.pcr0 |= FSXP; | ||
1502 | |||
1503 | if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) { | ||
1504 | mcbsp_cfg.pcr0 |= CLKXM; | ||
1505 | mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1); | ||
1506 | mcbsp_cfg.pcr0 |= FSXM; | ||
1507 | mcbsp_cfg.srgr2 &= ~FSGM; | ||
1508 | mcbsp_cfg.xcr2 |= XDATDLY(1); | ||
1509 | mcbsp_cfg.rcr2 |= RDATDLY(1); | ||
1510 | } else { | ||
1511 | mcbsp_cfg.pcr0 &= ~CLKXM; | ||
1512 | mcbsp_cfg.srgr1 |= CLKGDV(1); | ||
1513 | mcbsp_cfg.pcr0 &= ~FSXM; | ||
1514 | mcbsp_cfg.xcr2 &= ~XDATDLY(3); | ||
1515 | mcbsp_cfg.rcr2 &= ~RDATDLY(3); | ||
1516 | } | ||
1517 | |||
1518 | mcbsp_cfg.xcr2 &= ~XPHASE; | ||
1519 | mcbsp_cfg.rcr2 &= ~RPHASE; | ||
1520 | |||
1521 | omap_mcbsp_config(id, &mcbsp_cfg); | ||
1522 | } | ||
1523 | EXPORT_SYMBOL(omap_mcbsp_set_spi_mode); | ||
1524 | |||
1525 | #ifdef CONFIG_ARCH_OMAP3 | 1311 | #ifdef CONFIG_ARCH_OMAP3 |
1526 | #define max_thres(m) (mcbsp->pdata->buffer_size) | 1312 | #define max_thres(m) (mcbsp->pdata->buffer_size) |
1527 | #define valid_threshold(m, val) ((val) <= max_thres(m)) | 1313 | #define valid_threshold(m, val) ((val) <= max_thres(m)) |