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authorKen Cox <jkc@redhat.com>2012-07-18 23:19:10 -0400
committerMark Salter <msalter@redhat.com>2012-07-18 23:52:31 -0400
commitdbe91a2e6e53aa85efa0aac86e3a22ba95f8b85f (patch)
treeb4c4275ea7fa1797c0ff66df5661bbfaa81f91b6 /arch
parentf84f1f462bfaf0e45511f97ef54068b8539a7af6 (diff)
C6X: add basic support for TMS320C6678 SoC
This patch adds support for the TMS320C6678 SoC on an EVMC6678LE evaluation board. The 6678 is a C66x family CPU which is very similar to the already supported C64x CPUs with the addition of floating point instructions. Signed-off-by: Ken Cox <jkc@redhat.com> Signed-off-by: Mark Salter <msalter@redhat.com> CC: Aurelien Jacquiot <a-jacquiot@ti.com> CC: linux-c6x-dev@linux-c6x.org
Diffstat (limited to 'arch')
-rw-r--r--arch/c6x/boot/dts/evmc6678.dts83
-rw-r--r--arch/c6x/boot/dts/tms320c6678.dtsi146
-rw-r--r--arch/c6x/configs/evmc6678_defconfig42
-rw-r--r--arch/c6x/kernel/setup.c4
-rw-r--r--arch/c6x/platforms/Kconfig4
-rw-r--r--arch/c6x/platforms/plldata.c65
6 files changed, 344 insertions, 0 deletions
diff --git a/arch/c6x/boot/dts/evmc6678.dts b/arch/c6x/boot/dts/evmc6678.dts
new file mode 100644
index 000000000000..ab686301d321
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6678.dts
@@ -0,0 +1,83 @@
1/*
2 * arch/c6x/boot/dts/evmc6678.dts
3 *
4 * EVMC6678 Evaluation Platform For TMS320C6678
5 *
6 * Copyright (C) 2012 Texas Instruments Incorporated
7 *
8 * Author: Ken Cox <jkc@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 */
16
17/dts-v1/;
18
19/include/ "tms320c6678.dtsi"
20
21/ {
22 model = "Advantech EVMC6678";
23 compatible = "advantech,evmc6678";
24
25 chosen {
26 bootargs = "root=/dev/nfs ip=dhcp rw";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0x80000000 0x20000000>;
32 };
33
34 soc {
35 megamod_pic: interrupt-controller@1800000 {
36 interrupts = < 12 13 14 15 >;
37 };
38
39 timer8: timer@2280000 {
40 interrupt-parent = <&megamod_pic>;
41 interrupts = < 66 >;
42 };
43
44 timer9: timer@2290000 {
45 interrupt-parent = <&megamod_pic>;
46 interrupts = < 68 >;
47 };
48
49 timer10: timer@22A0000 {
50 interrupt-parent = <&megamod_pic>;
51 interrupts = < 70 >;
52 };
53
54 timer11: timer@22B0000 {
55 interrupt-parent = <&megamod_pic>;
56 interrupts = < 72 >;
57 };
58
59 timer12: timer@22C0000 {
60 interrupt-parent = <&megamod_pic>;
61 interrupts = < 74 >;
62 };
63
64 timer13: timer@22D0000 {
65 interrupt-parent = <&megamod_pic>;
66 interrupts = < 76 >;
67 };
68
69 timer14: timer@22E0000 {
70 interrupt-parent = <&megamod_pic>;
71 interrupts = < 78 >;
72 };
73
74 timer15: timer@22F0000 {
75 interrupt-parent = <&megamod_pic>;
76 interrupts = < 80 >;
77 };
78
79 clock-controller@2310000 {
80 clock-frequency = <100000000>;
81 };
82 };
83};
diff --git a/arch/c6x/boot/dts/tms320c6678.dtsi b/arch/c6x/boot/dts/tms320c6678.dtsi
new file mode 100644
index 000000000000..386196e5eae7
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6678.dtsi
@@ -0,0 +1,146 @@
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 reg = <0>;
13 model = "ti,c66x";
14 };
15 cpu@1 {
16 device_type = "cpu";
17 reg = <1>;
18 model = "ti,c66x";
19 };
20 cpu@2 {
21 device_type = "cpu";
22 reg = <2>;
23 model = "ti,c66x";
24 };
25 cpu@3 {
26 device_type = "cpu";
27 reg = <3>;
28 model = "ti,c66x";
29 };
30 cpu@4 {
31 device_type = "cpu";
32 reg = <4>;
33 model = "ti,c66x";
34 };
35 cpu@5 {
36 device_type = "cpu";
37 reg = <5>;
38 model = "ti,c66x";
39 };
40 cpu@6 {
41 device_type = "cpu";
42 reg = <6>;
43 model = "ti,c66x";
44 };
45 cpu@7 {
46 device_type = "cpu";
47 reg = <7>;
48 model = "ti,c66x";
49 };
50 };
51
52 soc {
53 compatible = "simple-bus";
54 model = "tms320c6678";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58
59 core_pic: interrupt-controller {
60 compatible = "ti,c64x+core-pic";
61 interrupt-controller;
62 #interrupt-cells = <1>;
63 };
64
65 megamod_pic: interrupt-controller@1800000 {
66 compatible = "ti,c64x+megamod-pic";
67 interrupt-controller;
68 #interrupt-cells = <1>;
69 reg = <0x1800000 0x1000>;
70 interrupt-parent = <&core_pic>;
71 };
72
73 cache-controller@1840000 {
74 compatible = "ti,c64x+cache";
75 reg = <0x01840000 0x8400>;
76 };
77
78 timer8: timer@2280000 {
79 compatible = "ti,c64x+timer64";
80 ti,core-mask = < 0x01 >;
81 reg = <0x2280000 0x40>;
82 };
83
84 timer9: timer@2290000 {
85 compatible = "ti,c64x+timer64";
86 ti,core-mask = < 0x02 >;
87 reg = <0x2290000 0x40>;
88 };
89
90 timer10: timer@22A0000 {
91 compatible = "ti,c64x+timer64";
92 ti,core-mask = < 0x04 >;
93 reg = <0x22A0000 0x40>;
94 };
95
96 timer11: timer@22B0000 {
97 compatible = "ti,c64x+timer64";
98 ti,core-mask = < 0x08 >;
99 reg = <0x22B0000 0x40>;
100 };
101
102 timer12: timer@22C0000 {
103 compatible = "ti,c64x+timer64";
104 ti,core-mask = < 0x10 >;
105 reg = <0x22C0000 0x40>;
106 };
107
108 timer13: timer@22D0000 {
109 compatible = "ti,c64x+timer64";
110 ti,core-mask = < 0x20 >;
111 reg = <0x22D0000 0x40>;
112 };
113
114 timer14: timer@22E0000 {
115 compatible = "ti,c64x+timer64";
116 ti,core-mask = < 0x40 >;
117 reg = <0x22E0000 0x40>;
118 };
119
120 timer15: timer@22F0000 {
121 compatible = "ti,c64x+timer64";
122 ti,core-mask = < 0x80 >;
123 reg = <0x22F0000 0x40>;
124 };
125
126 clock-controller@2310000 {
127 compatible = "ti,c6678-pll", "ti,c64x+pll";
128 reg = <0x02310000 0x200>;
129 ti,c64x+pll-bypass-delay = <200>;
130 ti,c64x+pll-reset-delay = <12000>;
131 ti,c64x+pll-lock-delay = <80000>;
132 };
133
134 device-state-controller@2620000 {
135 compatible = "ti,c64x+dscr";
136 reg = <0x02620000 0x1000>;
137
138 ti,dscr-devstat = <0x20>;
139 ti,dscr-silicon-rev = <0x18 28 0xf>;
140
141 ti,dscr-mac-fuse-regs = <0x110 1 2 3 4
142 0x114 5 6 0 0>;
143
144 };
145 };
146};
diff --git a/arch/c6x/configs/evmc6678_defconfig b/arch/c6x/configs/evmc6678_defconfig
new file mode 100644
index 000000000000..5f126d4905b1
--- /dev/null
+++ b/arch/c6x/configs/evmc6678_defconfig
@@ -0,0 +1,42 @@
1CONFIG_SOC_TMS320C6678=y
2CONFIG_EXPERIMENTAL=y
3# CONFIG_LOCALVERSION_AUTO is not set
4CONFIG_SYSVIPC=y
5CONFIG_SPARSE_IRQ=y
6CONFIG_LOG_BUF_SHIFT=14
7CONFIG_NAMESPACES=y
8# CONFIG_UTS_NS is not set
9# CONFIG_USER_NS is not set
10# CONFIG_PID_NS is not set
11CONFIG_BLK_DEV_INITRD=y
12CONFIG_CC_OPTIMIZE_FOR_SIZE=y
13CONFIG_EXPERT=y
14# CONFIG_FUTEX is not set
15# CONFIG_SLUB_DEBUG is not set
16CONFIG_MODULES=y
17CONFIG_MODULE_FORCE_LOAD=y
18CONFIG_MODULE_UNLOAD=y
19CONFIG_MODULE_FORCE_UNLOAD=y
20CONFIG_CMDLINE_BOOL=y
21CONFIG_CMDLINE=""
22# CONFIG_CMDLINE_FORCE is not set
23CONFIG_BOARD_EVM6678=y
24CONFIG_NO_HZ=y
25CONFIG_HIGH_RES_TIMERS=y
26CONFIG_BLK_DEV_LOOP=y
27CONFIG_BLK_DEV_RAM=y
28CONFIG_BLK_DEV_RAM_COUNT=2
29CONFIG_BLK_DEV_RAM_SIZE=17000
30CONFIG_MISC_DEVICES=y
31# CONFIG_INPUT is not set
32# CONFIG_SERIO is not set
33# CONFIG_VT is not set
34# CONFIG_HW_RANDOM is not set
35# CONFIG_HWMON is not set
36# CONFIG_USB_SUPPORT is not set
37# CONFIG_IOMMU_SUPPORT is not set
38# CONFIG_MISC_FILESYSTEMS is not set
39CONFIG_CRC16=y
40# CONFIG_ENABLE_MUST_CHECK is not set
41# CONFIG_SCHED_DEBUG is not set
42# CONFIG_DEBUG_BUGVERBOSE is not set
diff --git a/arch/c6x/kernel/setup.c b/arch/c6x/kernel/setup.c
index ce46186600c5..f4e72bd8c103 100644
--- a/arch/c6x/kernel/setup.c
+++ b/arch/c6x/kernel/setup.c
@@ -143,6 +143,10 @@ static void __init get_cpuinfo(void)
143 p->cpu_name = "C64x+"; 143 p->cpu_name = "C64x+";
144 p->cpu_voltage = "1.2"; 144 p->cpu_voltage = "1.2";
145 break; 145 break;
146 case 21:
147 p->cpu_name = "C66X";
148 p->cpu_voltage = "1.2";
149 break;
146 default: 150 default:
147 p->cpu_name = "unknown"; 151 p->cpu_name = "unknown";
148 break; 152 break;
diff --git a/arch/c6x/platforms/Kconfig b/arch/c6x/platforms/Kconfig
index 401ee678fd01..c4a0fad89aaf 100644
--- a/arch/c6x/platforms/Kconfig
+++ b/arch/c6x/platforms/Kconfig
@@ -14,3 +14,7 @@ config SOC_TMS320C6472
14config SOC_TMS320C6474 14config SOC_TMS320C6474
15 bool "TMS320C6474" 15 bool "TMS320C6474"
16 default n 16 default n
17
18config SOC_TMS320C6678
19 bool "TMS320C6678"
20 default n
diff --git a/arch/c6x/platforms/plldata.c b/arch/c6x/platforms/plldata.c
index 2cfd6f42968f..755359eb6286 100644
--- a/arch/c6x/platforms/plldata.c
+++ b/arch/c6x/platforms/plldata.c
@@ -335,6 +335,68 @@ static void __init c6474_setup_clocks(struct device_node *node)
335} 335}
336#endif /* CONFIG_SOC_TMS320C6474 */ 336#endif /* CONFIG_SOC_TMS320C6474 */
337 337
338#ifdef CONFIG_SOC_TMS320C6678
339static struct clk_lookup c6678_clks[] = {
340 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
341 CLK(NULL, "pll1_refclk", &c6x_soc_pll1.sysclks[1]),
342 CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
343 CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
344 CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
345 CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
346 CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
347 CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
348 CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
349 CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
350 CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
351 CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
352 CLK(NULL, "core", &c6x_core_clk),
353 CLK("", NULL, NULL)
354};
355
356static void __init c6678_setup_clocks(struct device_node *node)
357{
358 struct pll_data *pll = &c6x_soc_pll1;
359 struct clk *sysclks = pll->sysclks;
360
361 pll->flags = PLL_HAS_MUL;
362
363 sysclks[1].flags |= FIXED_DIV_PLL;
364 sysclks[1].div = 1;
365
366 sysclks[2].div = PLLDIV2;
367
368 sysclks[3].flags |= FIXED_DIV_PLL;
369 sysclks[3].div = 2;
370
371 sysclks[4].flags |= FIXED_DIV_PLL;
372 sysclks[4].div = 3;
373
374 sysclks[5].div = PLLDIV5;
375
376 sysclks[6].flags |= FIXED_DIV_PLL;
377 sysclks[6].div = 64;
378
379 sysclks[7].flags |= FIXED_DIV_PLL;
380 sysclks[7].div = 6;
381
382 sysclks[8].div = PLLDIV8;
383
384 sysclks[9].flags |= FIXED_DIV_PLL;
385 sysclks[9].div = 12;
386
387 sysclks[10].flags |= FIXED_DIV_PLL;
388 sysclks[10].div = 3;
389
390 sysclks[11].flags |= FIXED_DIV_PLL;
391 sysclks[11].div = 6;
392
393 c6x_core_clk.parent = &sysclks[0];
394 c6x_i2c_clk.parent = &sysclks[7];
395
396 c6x_clks_init(c6678_clks);
397}
398#endif /* CONFIG_SOC_TMS320C6678 */
399
338static struct of_device_id c6x_clkc_match[] __initdata = { 400static struct of_device_id c6x_clkc_match[] __initdata = {
339#ifdef CONFIG_SOC_TMS320C6455 401#ifdef CONFIG_SOC_TMS320C6455
340 { .compatible = "ti,c6455-pll", .data = c6455_setup_clocks }, 402 { .compatible = "ti,c6455-pll", .data = c6455_setup_clocks },
@@ -348,6 +410,9 @@ static struct of_device_id c6x_clkc_match[] __initdata = {
348#ifdef CONFIG_SOC_TMS320C6474 410#ifdef CONFIG_SOC_TMS320C6474
349 { .compatible = "ti,c6474-pll", .data = c6474_setup_clocks }, 411 { .compatible = "ti,c6474-pll", .data = c6474_setup_clocks },
350#endif 412#endif
413#ifdef CONFIG_SOC_TMS320C6678
414 { .compatible = "ti,c6678-pll", .data = c6678_setup_clocks },
415#endif
351 { .compatible = "ti,c64x+pll" }, 416 { .compatible = "ti,c64x+pll" },
352 {} 417 {}
353}; 418};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 07:41:10 -0500