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authorAl Cooper <alcooperx@gmail.com>2012-07-13 16:44:50 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-10-11 05:02:41 -0400
commitc5600b2dd9fc7318feddf69f127ca793437c714d (patch)
tree23f669aec84929c070db8996e2e8d8598555fb6a /arch
parent485172b3dff29f888a88d3dba8caec5d589a4049 (diff)
MIPS: perf: Change the "mips_perf_event" table unsupported indicator.
Change the indicator from 0xffffffff in the "event_id" member to zero in the "cntr_mask" member. This removes the need to initialize entries that are unsupported. This also solves a problem where the number of entries in the table was increased based on a globel enum used for all platforms, but the new unsupported entries were not added for mips. This was leaving new table entries of all zeros that we not marked UNSUPPORTED. Signed-off-by: Al Cooper <alcooperx@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/4110/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/kernel/perf_event_mipsxx.c154
1 files changed, 4 insertions, 150 deletions
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 2f28d3b55687..8451f04627d8 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -78,7 +78,6 @@ struct mips_perf_event {
78static struct mips_perf_event raw_event; 78static struct mips_perf_event raw_event;
79static DEFINE_MUTEX(raw_event_mutex); 79static DEFINE_MUTEX(raw_event_mutex);
80 80
81#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
82#define C(x) PERF_COUNT_HW_CACHE_##x 81#define C(x) PERF_COUNT_HW_CACHE_##x
83 82
84struct mips_pmu { 83struct mips_pmu {
@@ -664,13 +663,10 @@ static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
664 663
665static const struct mips_perf_event *mipspmu_map_general_event(int idx) 664static const struct mips_perf_event *mipspmu_map_general_event(int idx)
666{ 665{
667 const struct mips_perf_event *pev;
668
669 pev = ((*mipspmu.general_event_map)[idx].event_id ==
670 UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) :
671 &(*mipspmu.general_event_map)[idx]);
672 666
673 return pev; 667 if ((*mipspmu.general_event_map)[idx].cntr_mask == 0)
668 return ERR_PTR(-EOPNOTSUPP);
669 return &(*mipspmu.general_event_map)[idx];
674} 670}
675 671
676static const struct mips_perf_event *mipspmu_map_cache_event(u64 config) 672static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
@@ -695,7 +691,7 @@ static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
695 [cache_op] 691 [cache_op]
696 [cache_result]); 692 [cache_result]);
697 693
698 if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID) 694 if (pev->cntr_mask == 0)
699 return ERR_PTR(-EOPNOTSUPP); 695 return ERR_PTR(-EOPNOTSUPP);
700 696
701 return pev; 697 return pev;
@@ -800,11 +796,8 @@ static const struct mips_perf_event mipsxxcore_event_map
800 [PERF_COUNT_HW_MAX] = { 796 [PERF_COUNT_HW_MAX] = {
801 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, 797 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
802 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, 798 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
803 [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
804 [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
805 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T }, 799 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
806 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, 800 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
807 [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
808}; 801};
809 802
810/* 74K core has different branch event code. */ 803/* 74K core has different branch event code. */
@@ -812,11 +805,8 @@ static const struct mips_perf_event mipsxx74Kcore_event_map
812 [PERF_COUNT_HW_MAX] = { 805 [PERF_COUNT_HW_MAX] = {
813 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, 806 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
814 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, 807 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
815 [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
816 [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
817 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T }, 808 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
818 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T }, 809 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
819 [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
820}; 810};
821 811
822static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = { 812static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
@@ -849,10 +839,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
849 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, 839 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
850 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, 840 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
851 }, 841 },
852 [C(OP_PREFETCH)] = {
853 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
854 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
855 },
856}, 842},
857[C(L1I)] = { 843[C(L1I)] = {
858 [C(OP_READ)] = { 844 [C(OP_READ)] = {
@@ -869,7 +855,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
869 * Note that MIPS has only "hit" events countable for 855 * Note that MIPS has only "hit" events countable for
870 * the prefetch operation. 856 * the prefetch operation.
871 */ 857 */
872 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
873 }, 858 },
874}, 859},
875[C(LL)] = { 860[C(LL)] = {
@@ -881,10 +866,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
881 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, 866 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
882 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, 867 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
883 }, 868 },
884 [C(OP_PREFETCH)] = {
885 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
886 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
887 },
888}, 869},
889[C(DTLB)] = { 870[C(DTLB)] = {
890 [C(OP_READ)] = { 871 [C(OP_READ)] = {
@@ -895,10 +876,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
895 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, 876 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
896 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, 877 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
897 }, 878 },
898 [C(OP_PREFETCH)] = {
899 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
900 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
901 },
902}, 879},
903[C(ITLB)] = { 880[C(ITLB)] = {
904 [C(OP_READ)] = { 881 [C(OP_READ)] = {
@@ -909,10 +886,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
909 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, 886 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
910 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, 887 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
911 }, 888 },
912 [C(OP_PREFETCH)] = {
913 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
914 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
915 },
916}, 889},
917[C(BPU)] = { 890[C(BPU)] = {
918 /* Using the same code for *HW_BRANCH* */ 891 /* Using the same code for *HW_BRANCH* */
@@ -924,24 +897,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
924 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, 897 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
925 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, 898 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
926 }, 899 },
927 [C(OP_PREFETCH)] = {
928 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
929 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
930 },
931},
932[C(NODE)] = {
933 [C(OP_READ)] = {
934 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
935 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
936 },
937 [C(OP_WRITE)] = {
938 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
939 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
940 },
941 [C(OP_PREFETCH)] = {
942 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
943 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
944 },
945}, 900},
946}; 901};
947 902
@@ -965,10 +920,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
965 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, 920 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
966 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, 921 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
967 }, 922 },
968 [C(OP_PREFETCH)] = {
969 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
970 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
971 },
972}, 923},
973[C(L1I)] = { 924[C(L1I)] = {
974 [C(OP_READ)] = { 925 [C(OP_READ)] = {
@@ -985,7 +936,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
985 * Note that MIPS has only "hit" events countable for 936 * Note that MIPS has only "hit" events countable for
986 * the prefetch operation. 937 * the prefetch operation.
987 */ 938 */
988 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
989 }, 939 },
990}, 940},
991[C(LL)] = { 941[C(LL)] = {
@@ -997,25 +947,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
997 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, 947 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
998 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, 948 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
999 }, 949 },
1000 [C(OP_PREFETCH)] = {
1001 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1002 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1003 },
1004},
1005[C(DTLB)] = {
1006 /* 74K core does not have specific DTLB events. */
1007 [C(OP_READ)] = {
1008 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1009 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1010 },
1011 [C(OP_WRITE)] = {
1012 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1013 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1014 },
1015 [C(OP_PREFETCH)] = {
1016 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1017 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1018 },
1019}, 950},
1020[C(ITLB)] = { 951[C(ITLB)] = {
1021 [C(OP_READ)] = { 952 [C(OP_READ)] = {
@@ -1026,10 +957,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
1026 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, 957 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1027 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, 958 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1028 }, 959 },
1029 [C(OP_PREFETCH)] = {
1030 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1031 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1032 },
1033}, 960},
1034[C(BPU)] = { 961[C(BPU)] = {
1035 /* Using the same code for *HW_BRANCH* */ 962 /* Using the same code for *HW_BRANCH* */
@@ -1041,24 +968,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
1041 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, 968 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1042 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, 969 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1043 }, 970 },
1044 [C(OP_PREFETCH)] = {
1045 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1046 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1047 },
1048},
1049[C(NODE)] = {
1050 [C(OP_READ)] = {
1051 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1052 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1053 },
1054 [C(OP_WRITE)] = {
1055 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1056 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1057 },
1058 [C(OP_PREFETCH)] = {
1059 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1060 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1061 },
1062}, 971},
1063}; 972};
1064 973
@@ -1074,39 +983,14 @@ static const struct mips_perf_event octeon_cache_map
1074 }, 983 },
1075 [C(OP_WRITE)] = { 984 [C(OP_WRITE)] = {
1076 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL }, 985 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
1077 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1078 },
1079 [C(OP_PREFETCH)] = {
1080 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1081 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1082 }, 986 },
1083}, 987},
1084[C(L1I)] = { 988[C(L1I)] = {
1085 [C(OP_READ)] = { 989 [C(OP_READ)] = {
1086 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL }, 990 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
1087 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1088 },
1089 [C(OP_WRITE)] = {
1090 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1091 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1092 }, 991 },
1093 [C(OP_PREFETCH)] = { 992 [C(OP_PREFETCH)] = {
1094 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL }, 993 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
1095 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1096 },
1097},
1098[C(LL)] = {
1099 [C(OP_READ)] = {
1100 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1101 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1102 },
1103 [C(OP_WRITE)] = {
1104 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1105 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1106 },
1107 [C(OP_PREFETCH)] = {
1108 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1109 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1110 }, 994 },
1111}, 995},
1112[C(DTLB)] = { 996[C(DTLB)] = {
@@ -1115,46 +999,16 @@ static const struct mips_perf_event octeon_cache_map
1115 * read and write. 999 * read and write.
1116 */ 1000 */
1117 [C(OP_READ)] = { 1001 [C(OP_READ)] = {
1118 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1119 [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, 1002 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1120 }, 1003 },
1121 [C(OP_WRITE)] = { 1004 [C(OP_WRITE)] = {
1122 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1123 [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, 1005 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1124 }, 1006 },
1125 [C(OP_PREFETCH)] = {
1126 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1127 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1128 },
1129}, 1007},
1130[C(ITLB)] = { 1008[C(ITLB)] = {
1131 [C(OP_READ)] = { 1009 [C(OP_READ)] = {
1132 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1133 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, 1010 [C(RESULT_MISS)] = { 0x37, CNTR_ALL },
1134 }, 1011 },
1135 [C(OP_WRITE)] = {
1136 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1137 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1138 },
1139 [C(OP_PREFETCH)] = {
1140 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1141 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1142 },
1143},
1144[C(BPU)] = {
1145 /* Using the same code for *HW_BRANCH* */
1146 [C(OP_READ)] = {
1147 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1148 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1149 },
1150 [C(OP_WRITE)] = {
1151 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1152 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1153 },
1154 [C(OP_PREFETCH)] = {
1155 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1156 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1157 },
1158}, 1012},
1159}; 1013};
1160 1014
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