ARM: u300: move the gated system controller clocks to DT

This moves the slow, fast, AHB bridge and "rest" clocks on the U300 system controller over to registration from the device tree. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
author: Linus Walleij <linus.walleij@linaro.org> 2013-05-23 09:42:33 -0400
committer: Linus Walleij <linus.walleij@linaro.org> 2013-06-17 07:54:37 -0400
commit: bba5f2cc2f0fe4191ad2699c7c03a6def31f54e2 (patch)
tree: fb7bc7d023f56292cc7c5b4335cbcfc77b611ba1 /arch
parent: 2165f836c8f7036491fae41e9bc327a3cdf2fea3 (diff)
2 files changed, 150 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 203ec1fcbc10..7edc5e58a5a5 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -43,6 +43,49 @@
                        compatible = "fixed-clock";
                        clock-frequency = <13000000>;
                };
+                /* Slow bridge clocks under PLL13 */
+                slow_clk: slow_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <0>;
+                        clocks = <&pll13>;
+                };
+                uart0_clk: uart0_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <1>;
+                        clocks = <&slow_clk>;
+                };
+                gpio_clk: gpio_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <4>;
+                        clocks = <&slow_clk>;
+                };
+                rtc_clk: rtc_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <6>;
+                        clocks = <&slow_clk>;
+                };
+                apptimer_clk: app_tmr_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <7>;
+                        clocks = <&slow_clk>;
+                };
+                acc_tmr_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <8>;
+                        clocks = <&slow_clk>;
+                };
                pll208: pll208@208M {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
@@ -55,6 +98,13 @@
                        clock-mult = <1>;
                        clocks = <&pll208>;
                };
+                cpu_clk@208M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <3>;
+                        clocks = <&app208>;
+                };
                app104: app_104_clk@104M {
                        #clock-cells = <0>;
                        compatible = "fixed-factor-clock";
@@ -62,6 +112,13 @@
                        clock-mult = <1>;
                        clocks = <&pll208>;
                };
+                semi_clk@104M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <9>;
+                        clocks = <&app104>;
+                };
                app52: app_52_clk@52M {
                        #clock-cells = <0>;
                        compatible = "fixed-factor-clock";
@@ -69,6 +126,49 @@
                        clock-mult = <1>;
                        clocks = <&pll208>;
                };
+                /* AHB subsystem clocks */
+                ahb_clk: ahb_subsys_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <10>;
+                        clocks = <&app52>;
+                };
+                intcon_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <12>;
+                        clocks = <&ahb_clk>;
+                };
+                emif_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <5>;
+                        clocks = <&ahb_clk>;
+                };
+                dmac_clk: dmac_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <4>;
+                        clocks = <&app52>;
+                };
+                fsmc_clk: fsmc_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <6>;
+                        clocks = <&app52>;
+                };
+                xgam_clk: xgam_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <8>;
+                        clocks = <&app52>;
+                };
                app26: app_26_clk@26M {
                        #clock-cells = <0>;
                        compatible = "fixed-factor-clock";
@@ -76,6 +176,42 @@
                        clock-mult = <1>;
                        clocks = <&app52>;
                };
+                /* Fast bridge  clocks */
+                fast_clk: fast_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <0>;
+                        clocks = <&app26>;
+                };
+                i2c0_clk: i2c0_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <1>;
+                        clocks = <&fast_clk>;
+                };
+                i2c1_clk: i2c1_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <2>;
+                        clocks = <&fast_clk>;
+                };
+                mmc_pclk: mmc_p_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <5>;
+                        clocks = <&fast_clk>;
+                };
+                spi_clk: spi_p_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <6>;
+                        clocks = <&fast_clk>;
+                };
        };
        timer: timer@c0014000 {
@@ -83,6 +219,7 @@
                reg = <0xc0014000 0x1000>;
                interrupt-parent = <&vica>;
                interrupts = <24 25 26 27>;
+                clocks = <&apptimer_clk>;
        };
        gpio: gpio@c0016000 {
@@ -90,6 +227,7 @@
                reg = <0xc0016000 0x1000>;
                interrupt-parent = <&vicb>;
                interrupts = <0 1 2 18 21 22 23>;
+                clocks = <&gpio_clk>;
                interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
                                "gpio4", "gpio5", "gpio6";
                interrupt-controller;
@@ -116,6 +254,7 @@
                reg = <0xc0017000 0x1000>;
                interrupt-parent = <&vicb>;
                interrupts = <10>;
+                clocks = <&rtc_clk>;
        };
        dmac: dma-controller@c00020000 {
@@ -125,6 +264,7 @@
                interrupts = <2>;
                #dma-cells = <1>;
                dma-channels = <40>;
+                clocks = <&dmac_clk>;
        };
        /* A NAND flash of 128 MiB */
@@ -138,6 +278,7 @@
                        <0x80010000 0x4000>;    /* NAND Base CMD */
                reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
                nand-skip-bbtscan;
+                clocks = <&fsmc_clk>;
                partition@0 {
                label = "boot records";
@@ -158,6 +299,7 @@
                reg = <0xc0004000 0x1000>;
                interrupt-parent = <&vicb>;
                interrupts = <8>;
+                clocks = <&i2c0_clk>;
                #address-cells = <1>;
                #size-cells = <0>;
                ab3100: ab3100@0x48 {
@@ -235,6 +377,7 @@
                reg = <0xc0005000 0x1000>;
                interrupt-parent = <&vicb>;
                interrupts = <9>;
+                clocks = <&i2c1_clk>;
                #address-cells = <1>;
                #size-cells = <0>;
                fwcam0: fwcam@0x10 {
@@ -270,6 +413,8 @@
                        reg = <0xc0013000 0x1000>;
                        interrupt-parent = <&vica>;
                        interrupts = <22>;
+                        clocks = <&uart0_clk>, <&uart0_clk>;
+                        clock-names = "apb_pclk", "uart0_clk";
                        dmas = <&dmac 17 &dmac 18>;
                        dma-names = "tx", "rx";
                };
@@ -288,6 +433,8 @@
                        reg = <0xc0001000 0x1000>;
                        interrupt-parent = <&vicb>;
                        interrupts = <6 7>;
+                        clocks = <&mmc_pclk>;
+                        clock-names = "apb_pclk";
                        max-frequency = <24000000>;
                        bus-width = <4>; // SD-card slot
                        mmc-cap-mmc-highspeed;
@@ -304,6 +451,8 @@
                        reg = <0xc0006000 0x1000>;
                        interrupt-parent = <&vica>;
                        interrupts = <23>;
+                        clocks = <&spi_clk>, <&spi_clk>;
+                        clock-names = "apb_pclk", "spi_clk";
                        dmas = <&dmac 27 &dmac 28>;
                        dma-names = "tx", "rx";
                        num-cs = <3>;
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 2e1c81daf3c1..390ae5feb1d0 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -375,7 +375,7 @@ static void __init u300_timer_init_of(struct device_node *np)
        pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
        /* Clock the interrupt controller */
-        clk = clk_get_sys("apptimer", NULL);
+        clk = of_clk_get(np, 0);
        BUG_ON(IS_ERR(clk));
        clk_prepare_enable(clk);
        rate = clk_get_rate(clk);
author	Linus Walleij <linus.walleij@linaro.org>	2013-05-23 09:42:33 -0400
committer	Linus Walleij <linus.walleij@linaro.org>	2013-06-17 07:54:37 -0400
commit	bba5f2cc2f0fe4191ad2699c7c03a6def31f54e2 (patch)
tree	fb7bc7d023f56292cc7c5b4335cbcfc77b611ba1 /arch
parent	2165f836c8f7036491fae41e9bc327a3cdf2fea3 (diff)

diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts index 203ec1fcbc10..7edc5e58a5a5 100644 --- a/arch/arm/boot/dts/ste-u300.dts +++ b/arch/arm/boot/dts/ste-u300.dts
@@ -43,6 +43,49 @@
43	compatible = "fixed-clock";	43	compatible = "fixed-clock";
44	clock-frequency = <13000000>;	44	clock-frequency = <13000000>;
45	};	45	};
		46	/* Slow bridge clocks under PLL13 */
		47	slow_clk: slow_clk@13M {
		48	#clock-cells = <0>;
		49	compatible = "stericsson,u300-syscon-clk";
		50	clock-type = <0>; /* Slow */
		51	clock-id = <0>;
		52	clocks = <&pll13>;
		53	};
		54	uart0_clk: uart0_clk@13M {
		55	#clock-cells = <0>;
		56	compatible = "stericsson,u300-syscon-clk";
		57	clock-type = <0>; /* Slow */
		58	clock-id = <1>;
		59	clocks = <&slow_clk>;
		60	};
		61	gpio_clk: gpio_clk@13M {
		62	#clock-cells = <0>;
		63	compatible = "stericsson,u300-syscon-clk";
		64	clock-type = <0>; /* Slow */
		65	clock-id = <4>;
		66	clocks = <&slow_clk>;
		67	};
		68	rtc_clk: rtc_clk@13M {
		69	#clock-cells = <0>;
		70	compatible = "stericsson,u300-syscon-clk";
		71	clock-type = <0>; /* Slow */
		72	clock-id = <6>;
		73	clocks = <&slow_clk>;
		74	};
		75	apptimer_clk: app_tmr_clk@13M {
		76	#clock-cells = <0>;
		77	compatible = "stericsson,u300-syscon-clk";
		78	clock-type = <0>; /* Slow */
		79	clock-id = <7>;
		80	clocks = <&slow_clk>;
		81	};
		82	acc_tmr_clk@13M {
		83	#clock-cells = <0>;
		84	compatible = "stericsson,u300-syscon-clk";
		85	clock-type = <0>; /* Slow */
		86	clock-id = <8>;
		87	clocks = <&slow_clk>;
		88	};
46	pll208: pll208@208M {	89	pll208: pll208@208M {
47	#clock-cells = <0>;	90	#clock-cells = <0>;
48	compatible = "fixed-clock";	91	compatible = "fixed-clock";
@@ -55,6 +98,13 @@
55	clock-mult = <1>;	98	clock-mult = <1>;
56	clocks = <&pll208>;	99	clocks = <&pll208>;
57	};	100	};
		101	cpu_clk@208M {
		102	#clock-cells = <0>;
		103	compatible = "stericsson,u300-syscon-clk";
		104	clock-type = <2>; /* Rest */
		105	clock-id = <3>;
		106	clocks = <&app208>;
		107	};
58	app104: app_104_clk@104M {	108	app104: app_104_clk@104M {
59	#clock-cells = <0>;	109	#clock-cells = <0>;
60	compatible = "fixed-factor-clock";	110	compatible = "fixed-factor-clock";
@@ -62,6 +112,13 @@
62	clock-mult = <1>;	112	clock-mult = <1>;
63	clocks = <&pll208>;	113	clocks = <&pll208>;
64	};	114	};
		115	semi_clk@104M {
		116	#clock-cells = <0>;
		117	compatible = "stericsson,u300-syscon-clk";
		118	clock-type = <2>; /* Rest */
		119	clock-id = <9>;
		120	clocks = <&app104>;
		121	};
65	app52: app_52_clk@52M {	122	app52: app_52_clk@52M {
66	#clock-cells = <0>;	123	#clock-cells = <0>;
67	compatible = "fixed-factor-clock";	124	compatible = "fixed-factor-clock";
@@ -69,6 +126,49 @@
69	clock-mult = <1>;	126	clock-mult = <1>;
70	clocks = <&pll208>;	127	clocks = <&pll208>;
71	};	128	};
		129	/* AHB subsystem clocks */
		130	ahb_clk: ahb_subsys_clk@52M {
		131	#clock-cells = <0>;
		132	compatible = "stericsson,u300-syscon-clk";
		133	clock-type = <2>; /* Rest */
		134	clock-id = <10>;
		135	clocks = <&app52>;
		136	};
		137	intcon_clk@52M {
		138	#clock-cells = <0>;
		139	compatible = "stericsson,u300-syscon-clk";
		140	clock-type = <2>; /* Rest */
		141	clock-id = <12>;
		142	clocks = <&ahb_clk>;
		143	};
		144	emif_clk@52M {
		145	#clock-cells = <0>;
		146	compatible = "stericsson,u300-syscon-clk";
		147	clock-type = <2>; /* Rest */
		148	clock-id = <5>;
		149	clocks = <&ahb_clk>;
		150	};
		151	dmac_clk: dmac_clk@52M {
		152	#clock-cells = <0>;
		153	compatible = "stericsson,u300-syscon-clk";
		154	clock-type = <2>; /* Rest */
		155	clock-id = <4>;
		156	clocks = <&app52>;
		157	};
		158	fsmc_clk: fsmc_clk@52M {
		159	#clock-cells = <0>;
		160	compatible = "stericsson,u300-syscon-clk";
		161	clock-type = <2>; /* Rest */
		162	clock-id = <6>;
		163	clocks = <&app52>;
		164	};
		165	xgam_clk: xgam_clk@52M {
		166	#clock-cells = <0>;
		167	compatible = "stericsson,u300-syscon-clk";
		168	clock-type = <2>; /* Rest */
		169	clock-id = <8>;
		170	clocks = <&app52>;
		171	};
72	app26: app_26_clk@26M {	172	app26: app_26_clk@26M {
73	#clock-cells = <0>;	173	#clock-cells = <0>;
74	compatible = "fixed-factor-clock";	174	compatible = "fixed-factor-clock";
@@ -76,6 +176,42 @@
76	clock-mult = <1>;	176	clock-mult = <1>;
77	clocks = <&app52>;	177	clocks = <&app52>;
78	};	178	};
		179	/* Fast bridge clocks */
		180	fast_clk: fast_clk@26M {
		181	#clock-cells = <0>;
		182	compatible = "stericsson,u300-syscon-clk";
		183	clock-type = <1>; /* Fast */
		184	clock-id = <0>;
		185	clocks = <&app26>;
		186	};
		187	i2c0_clk: i2c0_clk@26M {
		188	#clock-cells = <0>;
		189	compatible = "stericsson,u300-syscon-clk";
		190	clock-type = <1>; /* Fast */
		191	clock-id = <1>;
		192	clocks = <&fast_clk>;
		193	};
		194	i2c1_clk: i2c1_clk@26M {
		195	#clock-cells = <0>;
		196	compatible = "stericsson,u300-syscon-clk";
		197	clock-type = <1>; /* Fast */
		198	clock-id = <2>;
		199	clocks = <&fast_clk>;
		200	};
		201	mmc_pclk: mmc_p_clk@26M {
		202	#clock-cells = <0>;
		203	compatible = "stericsson,u300-syscon-clk";
		204	clock-type = <1>; /* Fast */
		205	clock-id = <5>;
		206	clocks = <&fast_clk>;
		207	};
		208	spi_clk: spi_p_clk@26M {
		209	#clock-cells = <0>;
		210	compatible = "stericsson,u300-syscon-clk";
		211	clock-type = <1>; /* Fast */
		212	clock-id = <6>;
		213	clocks = <&fast_clk>;
		214	};
79	};	215	};
80		216
81	timer: timer@c0014000 {	217	timer: timer@c0014000 {
@@ -83,6 +219,7 @@
83	reg = <0xc0014000 0x1000>;	219	reg = <0xc0014000 0x1000>;
84	interrupt-parent = <&vica>;	220	interrupt-parent = <&vica>;
85	interrupts = <24 25 26 27>;	221	interrupts = <24 25 26 27>;
		222	clocks = <&apptimer_clk>;
86	};	223	};
87		224
88	gpio: gpio@c0016000 {	225	gpio: gpio@c0016000 {
@@ -90,6 +227,7 @@
90	reg = <0xc0016000 0x1000>;	227	reg = <0xc0016000 0x1000>;
91	interrupt-parent = <&vicb>;	228	interrupt-parent = <&vicb>;
92	interrupts = <0 1 2 18 21 22 23>;	229	interrupts = <0 1 2 18 21 22 23>;
		230	clocks = <&gpio_clk>;
93	interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",	231	interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
94	"gpio4", "gpio5", "gpio6";	232	"gpio4", "gpio5", "gpio6";
95	interrupt-controller;	233	interrupt-controller;
@@ -116,6 +254,7 @@
116	reg = <0xc0017000 0x1000>;	254	reg = <0xc0017000 0x1000>;
117	interrupt-parent = <&vicb>;	255	interrupt-parent = <&vicb>;
118	interrupts = <10>;	256	interrupts = <10>;
		257	clocks = <&rtc_clk>;
119	};	258	};
120		259
121	dmac: dma-controller@c00020000 {	260	dmac: dma-controller@c00020000 {
@@ -125,6 +264,7 @@
125	interrupts = <2>;	264	interrupts = <2>;
126	#dma-cells = <1>;	265	#dma-cells = <1>;
127	dma-channels = <40>;	266	dma-channels = <40>;
		267	clocks = <&dmac_clk>;
128	};	268	};
129		269
130	/* A NAND flash of 128 MiB */	270	/* A NAND flash of 128 MiB */
@@ -138,6 +278,7 @@
138	<0x80010000 0x4000>; /* NAND Base CMD */	278	<0x80010000 0x4000>; /* NAND Base CMD */
139	reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";	279	reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
140	nand-skip-bbtscan;	280	nand-skip-bbtscan;
		281	clocks = <&fsmc_clk>;
141		282
142	partition@0 {	283	partition@0 {
143	label = "boot records";	284	label = "boot records";
@@ -158,6 +299,7 @@
158	reg = <0xc0004000 0x1000>;	299	reg = <0xc0004000 0x1000>;
159	interrupt-parent = <&vicb>;	300	interrupt-parent = <&vicb>;
160	interrupts = <8>;	301	interrupts = <8>;
		302	clocks = <&i2c0_clk>;
161	#address-cells = <1>;	303	#address-cells = <1>;
162	#size-cells = <0>;	304	#size-cells = <0>;
163	ab3100: ab3100@0x48 {	305	ab3100: ab3100@0x48 {
@@ -235,6 +377,7 @@
235	reg = <0xc0005000 0x1000>;	377	reg = <0xc0005000 0x1000>;
236	interrupt-parent = <&vicb>;	378	interrupt-parent = <&vicb>;
237	interrupts = <9>;	379	interrupts = <9>;
		380	clocks = <&i2c1_clk>;
238	#address-cells = <1>;	381	#address-cells = <1>;
239	#size-cells = <0>;	382	#size-cells = <0>;
240	fwcam0: fwcam@0x10 {	383	fwcam0: fwcam@0x10 {
@@ -270,6 +413,8 @@
270	reg = <0xc0013000 0x1000>;	413	reg = <0xc0013000 0x1000>;
271	interrupt-parent = <&vica>;	414	interrupt-parent = <&vica>;
272	interrupts = <22>;	415	interrupts = <22>;
		416	clocks = <&uart0_clk>, <&uart0_clk>;
		417	clock-names = "apb_pclk", "uart0_clk";
273	dmas = <&dmac 17 &dmac 18>;	418	dmas = <&dmac 17 &dmac 18>;
274	dma-names = "tx", "rx";	419	dma-names = "tx", "rx";
275	};	420	};
@@ -288,6 +433,8 @@
288	reg = <0xc0001000 0x1000>;	433	reg = <0xc0001000 0x1000>;
289	interrupt-parent = <&vicb>;	434	interrupt-parent = <&vicb>;
290	interrupts = <6 7>;	435	interrupts = <6 7>;
		436	clocks = <&mmc_pclk>;
		437	clock-names = "apb_pclk";
291	max-frequency = <24000000>;	438	max-frequency = <24000000>;
292	bus-width = <4>; // SD-card slot	439	bus-width = <4>; // SD-card slot
293	mmc-cap-mmc-highspeed;	440	mmc-cap-mmc-highspeed;
@@ -304,6 +451,8 @@
304	reg = <0xc0006000 0x1000>;	451	reg = <0xc0006000 0x1000>;
305	interrupt-parent = <&vica>;	452	interrupt-parent = <&vica>;
306	interrupts = <23>;	453	interrupts = <23>;
		454	clocks = <&spi_clk>, <&spi_clk>;
		455	clock-names = "apb_pclk", "spi_clk";
307	dmas = <&dmac 27 &dmac 28>;	456	dmas = <&dmac 27 &dmac 28>;
308	dma-names = "tx", "rx";	457	dma-names = "tx", "rx";
309	num-cs = <3>;	458	num-cs = <3>;


diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index 2e1c81daf3c1..390ae5feb1d0 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c
@@ -375,7 +375,7 @@ static void __init u300_timer_init_of(struct device_node *np)
375	pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);	375	pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
376		376
377	/* Clock the interrupt controller */	377	/* Clock the interrupt controller */
378	clk = clk_get_sys("apptimer", NULL);	378	clk = of_clk_get(np, 0);
379	BUG_ON(IS_ERR(clk));	379	BUG_ON(IS_ERR(clk));
380	clk_prepare_enable(clk);	380	clk_prepare_enable(clk);
381	rate = clk_get_rate(clk);	381	rate = clk_get_rate(clk);