diff options
| author | Steven Miao <realmz6@gmail.com> | 2014-03-17 02:49:26 -0400 |
|---|---|---|
| committer | Steven Miao <realmz6@gmail.com> | 2014-04-11 20:47:51 -0400 |
| commit | ba3b6d75046b266ded31c8f91ce558c7c819fc80 (patch) | |
| tree | 2c76e3357e31d20e881d85905fd960f2d7280aff /arch | |
| parent | a0c1fb2ea74dedecd303fb0388e21ca869239db2 (diff) | |
bf54x: drop unuesd HOST status,control,timeout registers bit define macros
Signed-off-by: Steven Miao <realmz6@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF544.h | 30 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF547.h | 30 |
2 files changed, 0 insertions, 60 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h index 329b2c58228b..018ebfc27f5a 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF544.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h | |||
| @@ -601,36 +601,6 @@ | |||
| 601 | #define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ | 601 | #define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ |
| 602 | #define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ | 602 | #define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ |
| 603 | 603 | ||
| 604 | /* Bit masks for HOST_CONTROL */ | ||
| 605 | |||
| 606 | #define HOST_EN 0x1 /* Host Enable */ | ||
| 607 | #define HOST_END 0x2 /* Host Endianess */ | ||
| 608 | #define DATA_SIZE 0x4 /* Data Size */ | ||
| 609 | #define HOST_RST 0x8 /* Host Reset */ | ||
| 610 | #define HRDY_OVR 0x20 /* Host Ready Override */ | ||
| 611 | #define INT_MODE 0x40 /* Interrupt Mode */ | ||
| 612 | #define BT_EN 0x80 /* Bus Timeout Enable */ | ||
| 613 | #define EHW 0x100 /* Enable Host Write */ | ||
| 614 | #define EHR 0x200 /* Enable Host Read */ | ||
| 615 | #define BDR 0x400 /* Burst DMA Requests */ | ||
| 616 | |||
| 617 | /* Bit masks for HOST_STATUS */ | ||
| 618 | |||
| 619 | #define DMA_READY 0x1 /* DMA Ready */ | ||
| 620 | #define FIFOFULL 0x2 /* FIFO Full */ | ||
| 621 | #define FIFOEMPTY 0x4 /* FIFO Empty */ | ||
| 622 | #define DMA_COMPLETE 0x8 /* DMA Complete */ | ||
| 623 | #define HSHK 0x10 /* Host Handshake */ | ||
| 624 | #define HSTIMEOUT 0x20 /* Host Timeout */ | ||
| 625 | #define HIRQ 0x40 /* Host Interrupt Request */ | ||
| 626 | #define ALLOW_CNFG 0x80 /* Allow New Configuration */ | ||
| 627 | #define DMA_DIR 0x100 /* DMA Direction */ | ||
| 628 | #define BTE 0x200 /* Bus Timeout Enabled */ | ||
| 629 | |||
| 630 | /* Bit masks for HOST_TIMEOUT */ | ||
| 631 | |||
| 632 | #define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ | ||
| 633 | |||
| 634 | /* Bit masks for TIMER_ENABLE1 */ | 604 | /* Bit masks for TIMER_ENABLE1 */ |
| 635 | 605 | ||
| 636 | #define TIMEN8 0x1 /* Timer 8 Enable */ | 606 | #define TIMEN8 0x1 /* Timer 8 Enable */ |
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h index e18de212ba1a..d55dcc0f5324 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF547.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h | |||
| @@ -581,36 +581,6 @@ | |||
| 581 | #define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ | 581 | #define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ |
| 582 | #define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ | 582 | #define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ |
| 583 | 583 | ||
| 584 | /* Bit masks for HOST_CONTROL */ | ||
| 585 | |||
| 586 | #define HOST_EN 0x1 /* Host Enable */ | ||
| 587 | #define HOST_END 0x2 /* Host Endianess */ | ||
| 588 | #define DATA_SIZE 0x4 /* Data Size */ | ||
| 589 | #define HOST_RST 0x8 /* Host Reset */ | ||
| 590 | #define HRDY_OVR 0x20 /* Host Ready Override */ | ||
| 591 | #define INT_MODE 0x40 /* Interrupt Mode */ | ||
| 592 | #define BT_EN 0x80 /* Bus Timeout Enable */ | ||
| 593 | #define EHW 0x100 /* Enable Host Write */ | ||
| 594 | #define EHR 0x200 /* Enable Host Read */ | ||
| 595 | #define BDR 0x400 /* Burst DMA Requests */ | ||
| 596 | |||
| 597 | /* Bit masks for HOST_STATUS */ | ||
| 598 | |||
| 599 | #define DMA_READY 0x1 /* DMA Ready */ | ||
| 600 | #define FIFOFULL 0x2 /* FIFO Full */ | ||
| 601 | #define FIFOEMPTY 0x4 /* FIFO Empty */ | ||
| 602 | #define DMA_COMPLETE 0x8 /* DMA Complete */ | ||
| 603 | #define HSHK 0x10 /* Host Handshake */ | ||
| 604 | #define HSTIMEOUT 0x20 /* Host Timeout */ | ||
| 605 | #define HIRQ 0x40 /* Host Interrupt Request */ | ||
| 606 | #define ALLOW_CNFG 0x80 /* Allow New Configuration */ | ||
| 607 | #define DMA_DIR 0x100 /* DMA Direction */ | ||
| 608 | #define BTE 0x200 /* Bus Timeout Enabled */ | ||
| 609 | |||
| 610 | /* Bit masks for HOST_TIMEOUT */ | ||
| 611 | |||
| 612 | #define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ | ||
| 613 | |||
| 614 | /* Bit masks for KPAD_CTL */ | 584 | /* Bit masks for KPAD_CTL */ |
| 615 | 585 | ||
| 616 | #define KPAD_EN 0x1 /* Keypad Enable */ | 586 | #define KPAD_EN 0x1 /* Keypad Enable */ |