aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorJesper Nilsson <jesper.nilsson@axis.com>2010-08-04 05:25:13 -0400
committerJesper Nilsson <jesper.nilsson@axis.com>2010-08-04 07:02:38 -0400
commit4f248d1cea12afd2d961509eb2ba19bd0939033f (patch)
treed320bfb5fcaca4b137534f68e96371255c418b8e /arch
parent97a644461d9f47a0b2085d79783017d45b575325 (diff)
CRIS: Better ARTPEC-3 support for gpio
Add PWM support, correct comment for ARTPEC-3. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/cris/include/asm/etraxgpio.h96
1 files changed, 78 insertions, 18 deletions
diff --git a/arch/cris/include/asm/etraxgpio.h b/arch/cris/include/asm/etraxgpio.h
index 38f1c8e1770c..d474818a537e 100644
--- a/arch/cris/include/asm/etraxgpio.h
+++ b/arch/cris/include/asm/etraxgpio.h
@@ -21,31 +21,35 @@
21 * /dev/leds minor 2, Access to leds depending on kernelconfig 21 * /dev/leds minor 2, Access to leds depending on kernelconfig
22 * 22 *
23 * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3): 23 * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3):
24 * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction 24 * /dev/gpioa minor 0, 32 bit GPIO, each bit can change direction
25 * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction 25 * /dev/gpiob minor 1, 32 bit GPIO, each bit can change direction
26 * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction 26 * /dev/gpioc minor 3, 16 bit GPIO, each bit can change direction
27 * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction 27 * /dev/gpiod minor 4, 32 bit GPIO, input only
28 * /dev/leds minor 2, Access to leds depending on kernelconfig 28 * /dev/leds minor 2, Access to leds depending on kernelconfig
29 * /dev/pwm0 minor 16, PWM channel 0 on PA30 29 * /dev/pwm0 minor 16, PWM channel 0 on PA30
30 * /dev/pwm1 minor 17, PWM channel 1 on PA31 30 * /dev/pwm1 minor 17, PWM channel 1 on PA31
31 * /dev/pwm2 minor 18, PWM channel 2 on PB26 31 * /dev/pwm2 minor 18, PWM channel 2 on PB26
32 * /dev/ppwm minor 19, PPWM channel
32 * 33 *
33 */ 34 */
34#ifndef _ASM_ETRAXGPIO_H 35#ifndef _ASM_ETRAXGPIO_H
35#define _ASM_ETRAXGPIO_H 36#define _ASM_ETRAXGPIO_H
36 37
38#define GPIO_MINOR_FIRST 0
39
40#define ETRAXGPIO_IOCTYPE 43
41
37/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ 42/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
38#ifdef CONFIG_ETRAX_ARCH_V10 43#ifdef CONFIG_ETRAX_ARCH_V10
39#define ETRAXGPIO_IOCTYPE 43
40#define GPIO_MINOR_A 0 44#define GPIO_MINOR_A 0
41#define GPIO_MINOR_B 1 45#define GPIO_MINOR_B 1
42#define GPIO_MINOR_LEDS 2 46#define GPIO_MINOR_LEDS 2
43#define GPIO_MINOR_G 3 47#define GPIO_MINOR_G 3
44#define GPIO_MINOR_LAST 3 48#define GPIO_MINOR_LAST 3
49#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
45#endif 50#endif
46 51
47#ifdef CONFIG_ETRAXFS 52#ifdef CONFIG_ETRAXFS
48#define ETRAXGPIO_IOCTYPE 43
49#define GPIO_MINOR_A 0 53#define GPIO_MINOR_A 0
50#define GPIO_MINOR_B 1 54#define GPIO_MINOR_B 1
51#define GPIO_MINOR_LEDS 2 55#define GPIO_MINOR_LEDS 2
@@ -58,10 +62,10 @@
58#else 62#else
59#define GPIO_MINOR_LAST 5 63#define GPIO_MINOR_LAST 5
60#endif 64#endif
65#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
61#endif 66#endif
62 67
63#ifdef CONFIG_CRIS_MACH_ARTPEC3 68#ifdef CONFIG_CRIS_MACH_ARTPEC3
64#define ETRAXGPIO_IOCTYPE 43
65#define GPIO_MINOR_A 0 69#define GPIO_MINOR_A 0
66#define GPIO_MINOR_B 1 70#define GPIO_MINOR_B 1
67#define GPIO_MINOR_LEDS 2 71#define GPIO_MINOR_LEDS 2
@@ -73,12 +77,17 @@
73#else 77#else
74#define GPIO_MINOR_LAST 4 78#define GPIO_MINOR_LAST 4
75#endif 79#endif
76#define GPIO_MINOR_PWM0 16 80#define GPIO_MINOR_FIRST_PWM 16
77#define GPIO_MINOR_PWM1 17 81#define GPIO_MINOR_PWM0 (GPIO_MINOR_FIRST_PWM+0)
78#define GPIO_MINOR_PWM2 18 82#define GPIO_MINOR_PWM1 (GPIO_MINOR_FIRST_PWM+1)
79#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2 83#define GPIO_MINOR_PWM2 (GPIO_MINOR_FIRST_PWM+2)
84#define GPIO_MINOR_PPWM (GPIO_MINOR_FIRST_PWM+3)
85#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PPWM
86#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST_PWM
80#endif 87#endif
81 88
89
90
82/* supported ioctl _IOC_NR's */ 91/* supported ioctl _IOC_NR's */
83 92
84#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */ 93#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */
@@ -125,12 +134,10 @@
125 */ 134 */
126#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */ 135#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */
127#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */ 136#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */
128#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, 137#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, */
129 * *arg updated with current input pins. 138 /* *arg updated with current input pins. */
130 */ 139#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */
131#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, 140 /* *arg updated with current output pins. */
132 * *arg updated with current output pins.
133 */
134 141
135/* The following ioctl's are applicable to the PWM channels only */ 142/* The following ioctl's are applicable to the PWM channels only */
136 143
@@ -140,7 +147,8 @@ enum io_pwm_mode {
140 PWM_OFF = 0, /* disabled, deallocated */ 147 PWM_OFF = 0, /* disabled, deallocated */
141 PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */ 148 PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */
142 PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */ 149 PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */
143 PWM_VARFREQ = 3 /* individually configurable high/low periods */ 150 PWM_VARFREQ = 3, /* individually configurable high/low periods */
151 PWM_SOFT = 4 /* software generated */
144}; 152};
145 153
146struct io_pwm_set_mode { 154struct io_pwm_set_mode {
@@ -176,4 +184,56 @@ struct io_pwm_set_duty {
176 int duty; /* 0..255 */ 184 int duty; /* 0..255 */
177}; 185};
178 186
187/* Returns information about the latest PWM pulse.
188 * lo: Length of the latest low period, in units of 10ns.
189 * hi: Length of the latest high period, in units of 10ns.
190 * cnt: Time since last detected edge, in units of 10ns.
191 *
192 * The input source to PWM is decied by IO_PWM_SET_INPUT_SRC.
193 *
194 * NOTE: All PWM devices is connected to the same input source.
195 */
196#define IO_PWM_GET_PERIOD 0x23
197
198struct io_pwm_get_period {
199 unsigned int lo;
200 unsigned int hi;
201 unsigned int cnt;
202};
203
204/* Sets the input source for the PWM input. For the src value see the
205 * register description for gio:rw_pwm_in_cfg.
206 *
207 * NOTE: All PWM devices is connected to the same input source.
208 */
209#define IO_PWM_SET_INPUT_SRC 0x24
210struct io_pwm_set_input_src {
211 unsigned int src; /* 0..7 */
212};
213
214/* Sets the duty cycles in steps of 1/256, 0 = 0%, 255 = 100% duty cycle */
215#define IO_PPWM_SET_DUTY 0x25
216
217struct io_ppwm_set_duty {
218 int duty; /* 0..255 */
219};
220
221/* Configuraton struct for the IO_PWMCLK_SET_CONFIG ioctl to configure
222 * PWM capable gpio pins:
223 */
224#define IO_PWMCLK_SETGET_CONFIG 0x26
225struct gpio_pwmclk_conf {
226 unsigned int gpiopin; /* The pin number based on the opened device */
227 unsigned int baseclk; /* The base clock to use, or sw will select one close*/
228 unsigned int low; /* The number of low periods of the baseclk */
229 unsigned int high; /* The number of high periods of the baseclk */
230};
231
232/* Examples:
233 * To get a symmetric 12 MHz clock without knowing anything about the hardware:
234 * baseclk = 12000000, low = 0, high = 0
235 * To just get info of current setting:
236 * baseclk = 0, low = 0, high = 0, the values will be updated by driver.
237 */
238
179#endif 239#endif