diff options
author | Mike Turquette <mturquette@linaro.org> | 2014-06-10 19:53:25 -0400 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2014-06-10 19:53:25 -0400 |
commit | 3f6eec9969d24f91a3909d51e86e007ca5efd4c4 (patch) | |
tree | bff0f51bab78b18d52cfd57ad7cd8b78ac6a882c /arch | |
parent | 963649d735c8b6eb0f97e82c54f02426ff3f1f45 (diff) | |
parent | 7e148070001ae82df08966199580a29b934e3bf3 (diff) |
Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into clk-next
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/boot/dts/dra7xx-clocks.dtsi | 24 | ||||
-rw-r--r-- | arch/arm/boot/dts/omap54xx-clocks.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 53 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock.h | 13 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock2xxx.h | 4 | ||||
-rw-r--r-- | arch/arm/mach-omap2/dpll3xxx.c | 9 |
6 files changed, 75 insertions, 30 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index c7676871d9c0..b03cfe49d22b 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi | |||
@@ -26,7 +26,7 @@ | |||
26 | clock-frequency = <0>; | 26 | clock-frequency = <0>; |
27 | }; | 27 | }; |
28 | 28 | ||
29 | atlclkin3_ck: atlclkin3_ck { | 29 | atl_clkin3_ck: atl_clkin3_ck { |
30 | #clock-cells = <0>; | 30 | #clock-cells = <0>; |
31 | compatible = "fixed-clock"; | 31 | compatible = "fixed-clock"; |
32 | clock-frequency = <0>; | 32 | clock-frequency = <0>; |
@@ -277,7 +277,7 @@ | |||
277 | 277 | ||
278 | dpll_mpu_ck: dpll_mpu_ck { | 278 | dpll_mpu_ck: dpll_mpu_ck { |
279 | #clock-cells = <0>; | 279 | #clock-cells = <0>; |
280 | compatible = "ti,omap4-dpll-clock"; | 280 | compatible = "ti,omap5-mpu-dpll-clock"; |
281 | clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; | 281 | clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; |
282 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; | 282 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; |
283 | }; | 283 | }; |
@@ -730,7 +730,7 @@ | |||
730 | mcasp1_ahclkr_mux: mcasp1_ahclkr_mux { | 730 | mcasp1_ahclkr_mux: mcasp1_ahclkr_mux { |
731 | #clock-cells = <0>; | 731 | #clock-cells = <0>; |
732 | compatible = "ti,mux-clock"; | 732 | compatible = "ti,mux-clock"; |
733 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 733 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
734 | ti,bit-shift = <28>; | 734 | ti,bit-shift = <28>; |
735 | reg = <0x0550>; | 735 | reg = <0x0550>; |
736 | }; | 736 | }; |
@@ -738,7 +738,7 @@ | |||
738 | mcasp1_ahclkx_mux: mcasp1_ahclkx_mux { | 738 | mcasp1_ahclkx_mux: mcasp1_ahclkx_mux { |
739 | #clock-cells = <0>; | 739 | #clock-cells = <0>; |
740 | compatible = "ti,mux-clock"; | 740 | compatible = "ti,mux-clock"; |
741 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 741 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
742 | ti,bit-shift = <24>; | 742 | ti,bit-shift = <24>; |
743 | reg = <0x0550>; | 743 | reg = <0x0550>; |
744 | }; | 744 | }; |
@@ -1639,7 +1639,7 @@ | |||
1639 | mcasp2_ahclkr_mux: mcasp2_ahclkr_mux { | 1639 | mcasp2_ahclkr_mux: mcasp2_ahclkr_mux { |
1640 | #clock-cells = <0>; | 1640 | #clock-cells = <0>; |
1641 | compatible = "ti,mux-clock"; | 1641 | compatible = "ti,mux-clock"; |
1642 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1642 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
1643 | ti,bit-shift = <28>; | 1643 | ti,bit-shift = <28>; |
1644 | reg = <0x1860>; | 1644 | reg = <0x1860>; |
1645 | }; | 1645 | }; |
@@ -1647,7 +1647,7 @@ | |||
1647 | mcasp2_ahclkx_mux: mcasp2_ahclkx_mux { | 1647 | mcasp2_ahclkx_mux: mcasp2_ahclkx_mux { |
1648 | #clock-cells = <0>; | 1648 | #clock-cells = <0>; |
1649 | compatible = "ti,mux-clock"; | 1649 | compatible = "ti,mux-clock"; |
1650 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1650 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
1651 | ti,bit-shift = <24>; | 1651 | ti,bit-shift = <24>; |
1652 | reg = <0x1860>; | 1652 | reg = <0x1860>; |
1653 | }; | 1653 | }; |
@@ -1663,7 +1663,7 @@ | |||
1663 | mcasp3_ahclkx_mux: mcasp3_ahclkx_mux { | 1663 | mcasp3_ahclkx_mux: mcasp3_ahclkx_mux { |
1664 | #clock-cells = <0>; | 1664 | #clock-cells = <0>; |
1665 | compatible = "ti,mux-clock"; | 1665 | compatible = "ti,mux-clock"; |
1666 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1666 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
1667 | ti,bit-shift = <24>; | 1667 | ti,bit-shift = <24>; |
1668 | reg = <0x1868>; | 1668 | reg = <0x1868>; |
1669 | }; | 1669 | }; |
@@ -1679,7 +1679,7 @@ | |||
1679 | mcasp4_ahclkx_mux: mcasp4_ahclkx_mux { | 1679 | mcasp4_ahclkx_mux: mcasp4_ahclkx_mux { |
1680 | #clock-cells = <0>; | 1680 | #clock-cells = <0>; |
1681 | compatible = "ti,mux-clock"; | 1681 | compatible = "ti,mux-clock"; |
1682 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1682 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
1683 | ti,bit-shift = <24>; | 1683 | ti,bit-shift = <24>; |
1684 | reg = <0x1898>; | 1684 | reg = <0x1898>; |
1685 | }; | 1685 | }; |
@@ -1695,7 +1695,7 @@ | |||
1695 | mcasp5_ahclkx_mux: mcasp5_ahclkx_mux { | 1695 | mcasp5_ahclkx_mux: mcasp5_ahclkx_mux { |
1696 | #clock-cells = <0>; | 1696 | #clock-cells = <0>; |
1697 | compatible = "ti,mux-clock"; | 1697 | compatible = "ti,mux-clock"; |
1698 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1698 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
1699 | ti,bit-shift = <24>; | 1699 | ti,bit-shift = <24>; |
1700 | reg = <0x1878>; | 1700 | reg = <0x1878>; |
1701 | }; | 1701 | }; |
@@ -1711,7 +1711,7 @@ | |||
1711 | mcasp6_ahclkx_mux: mcasp6_ahclkx_mux { | 1711 | mcasp6_ahclkx_mux: mcasp6_ahclkx_mux { |
1712 | #clock-cells = <0>; | 1712 | #clock-cells = <0>; |
1713 | compatible = "ti,mux-clock"; | 1713 | compatible = "ti,mux-clock"; |
1714 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1714 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
1715 | ti,bit-shift = <24>; | 1715 | ti,bit-shift = <24>; |
1716 | reg = <0x1904>; | 1716 | reg = <0x1904>; |
1717 | }; | 1717 | }; |
@@ -1727,7 +1727,7 @@ | |||
1727 | mcasp7_ahclkx_mux: mcasp7_ahclkx_mux { | 1727 | mcasp7_ahclkx_mux: mcasp7_ahclkx_mux { |
1728 | #clock-cells = <0>; | 1728 | #clock-cells = <0>; |
1729 | compatible = "ti,mux-clock"; | 1729 | compatible = "ti,mux-clock"; |
1730 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1730 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
1731 | ti,bit-shift = <24>; | 1731 | ti,bit-shift = <24>; |
1732 | reg = <0x1908>; | 1732 | reg = <0x1908>; |
1733 | }; | 1733 | }; |
@@ -1743,7 +1743,7 @@ | |||
1743 | mcasp8_ahclk_mux: mcasp8_ahclk_mux { | 1743 | mcasp8_ahclk_mux: mcasp8_ahclk_mux { |
1744 | #clock-cells = <0>; | 1744 | #clock-cells = <0>; |
1745 | compatible = "ti,mux-clock"; | 1745 | compatible = "ti,mux-clock"; |
1746 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1746 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
1747 | ti,bit-shift = <22>; | 1747 | ti,bit-shift = <22>; |
1748 | reg = <0x1890>; | 1748 | reg = <0x1890>; |
1749 | }; | 1749 | }; |
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index aeb142ce8e9d..e67a23b5d788 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi | |||
@@ -335,7 +335,7 @@ | |||
335 | 335 | ||
336 | dpll_mpu_ck: dpll_mpu_ck { | 336 | dpll_mpu_ck: dpll_mpu_ck { |
337 | #clock-cells = <0>; | 337 | #clock-cells = <0>; |
338 | compatible = "ti,omap4-dpll-clock"; | 338 | compatible = "ti,omap5-mpu-dpll-clock"; |
339 | clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; | 339 | clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; |
340 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; | 340 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; |
341 | }; | 341 | }; |
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index b935ed2922d8..85e0b0c06718 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | |||
@@ -208,3 +208,56 @@ void omap2xxx_clkt_vps_late_init(void) | |||
208 | clk_put(c); | 208 | clk_put(c); |
209 | } | 209 | } |
210 | } | 210 | } |
211 | |||
212 | #ifdef CONFIG_OF | ||
213 | #include <linux/clk-provider.h> | ||
214 | #include <linux/clkdev.h> | ||
215 | |||
216 | static const struct clk_ops virt_prcm_set_ops = { | ||
217 | .recalc_rate = &omap2_table_mpu_recalc, | ||
218 | .set_rate = &omap2_select_table_rate, | ||
219 | .round_rate = &omap2_round_to_table_rate, | ||
220 | }; | ||
221 | |||
222 | /** | ||
223 | * omap2xxx_clkt_vps_init - initialize virt_prcm_set clock | ||
224 | * | ||
225 | * Does a manual init for the virtual prcm DVFS clock for OMAP2. This | ||
226 | * function is called only from omap2 DT clock init, as the virtual | ||
227 | * node is not modelled in the DT clock data. | ||
228 | */ | ||
229 | void omap2xxx_clkt_vps_init(void) | ||
230 | { | ||
231 | struct clk_init_data init = { NULL }; | ||
232 | struct clk_hw_omap *hw = NULL; | ||
233 | struct clk *clk; | ||
234 | const char *parent_name = "mpu_ck"; | ||
235 | struct clk_lookup *lookup = NULL; | ||
236 | |||
237 | omap2xxx_clkt_vps_late_init(); | ||
238 | omap2xxx_clkt_vps_check_bootloader_rates(); | ||
239 | |||
240 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); | ||
241 | lookup = kzalloc(sizeof(*lookup), GFP_KERNEL); | ||
242 | if (!hw || !lookup) | ||
243 | goto cleanup; | ||
244 | init.name = "virt_prcm_set"; | ||
245 | init.ops = &virt_prcm_set_ops; | ||
246 | init.parent_names = &parent_name; | ||
247 | init.num_parents = 1; | ||
248 | |||
249 | hw->hw.init = &init; | ||
250 | |||
251 | clk = clk_register(NULL, &hw->hw); | ||
252 | |||
253 | lookup->dev_id = NULL; | ||
254 | lookup->con_id = "cpufreq_ck"; | ||
255 | lookup->clk = clk; | ||
256 | |||
257 | clkdev_add(lookup); | ||
258 | return; | ||
259 | cleanup: | ||
260 | kfree(hw); | ||
261 | kfree(lookup); | ||
262 | } | ||
263 | #endif | ||
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index bda767a9dea8..12f54d428d7c 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
@@ -178,17 +178,6 @@ struct clksel { | |||
178 | const struct clksel_rate *rates; | 178 | const struct clksel_rate *rates; |
179 | }; | 179 | }; |
180 | 180 | ||
181 | struct clk_hw_omap_ops { | ||
182 | void (*find_idlest)(struct clk_hw_omap *oclk, | ||
183 | void __iomem **idlest_reg, | ||
184 | u8 *idlest_bit, u8 *idlest_val); | ||
185 | void (*find_companion)(struct clk_hw_omap *oclk, | ||
186 | void __iomem **other_reg, | ||
187 | u8 *other_bit); | ||
188 | void (*allow_idle)(struct clk_hw_omap *oclk); | ||
189 | void (*deny_idle)(struct clk_hw_omap *oclk); | ||
190 | }; | ||
191 | |||
192 | unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, | 181 | unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, |
193 | unsigned long parent_rate); | 182 | unsigned long parent_rate); |
194 | 183 | ||
@@ -279,8 +268,6 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait; | |||
279 | extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; | 268 | extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; |
280 | extern const struct clk_hw_omap_ops clkhwops_apll54; | 269 | extern const struct clk_hw_omap_ops clkhwops_apll54; |
281 | extern const struct clk_hw_omap_ops clkhwops_apll96; | 270 | extern const struct clk_hw_omap_ops clkhwops_apll96; |
282 | extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; | ||
283 | extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; | ||
284 | 271 | ||
285 | /* clksel_rate blocks shared between OMAP44xx and AM33xx */ | 272 | /* clksel_rate blocks shared between OMAP44xx and AM33xx */ |
286 | extern const struct clksel_rate div_1_0_rates[]; | 273 | extern const struct clksel_rate div_1_0_rates[]; |
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index 539dc08afbba..45f41a411603 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h | |||
@@ -21,10 +21,6 @@ unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, | |||
21 | unsigned long parent_rate); | 21 | unsigned long parent_rate); |
22 | unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, | 22 | unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, |
23 | unsigned long parent_rate); | 23 | unsigned long parent_rate); |
24 | unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, | ||
25 | unsigned long parent_rate); | ||
26 | int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, | ||
27 | unsigned long parent_rate); | ||
28 | void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); | 24 | void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); |
29 | unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw, | 25 | unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw, |
30 | unsigned long parent_rate); | 26 | unsigned long parent_rate); |
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index fcd8036af910..6d7ba37e2257 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c | |||
@@ -319,6 +319,15 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) | |||
319 | 319 | ||
320 | /* Set DPLL multiplier, divider */ | 320 | /* Set DPLL multiplier, divider */ |
321 | v = omap2_clk_readl(clk, dd->mult_div1_reg); | 321 | v = omap2_clk_readl(clk, dd->mult_div1_reg); |
322 | |||
323 | /* Handle Duty Cycle Correction */ | ||
324 | if (dd->dcc_mask) { | ||
325 | if (dd->last_rounded_rate >= dd->dcc_rate) | ||
326 | v |= dd->dcc_mask; /* Enable DCC */ | ||
327 | else | ||
328 | v &= ~dd->dcc_mask; /* Disable DCC */ | ||
329 | } | ||
330 | |||
322 | v &= ~(dd->mult_mask | dd->div1_mask); | 331 | v &= ~(dd->mult_mask | dd->div1_mask); |
323 | v |= dd->last_rounded_m << __ffs(dd->mult_mask); | 332 | v |= dd->last_rounded_m << __ffs(dd->mult_mask); |
324 | v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); | 333 | v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); |