diff options
author | Paul Mundt <lethal@linux-sh.org> | 2006-12-24 20:19:56 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2007-02-12 20:54:45 -0500 |
commit | 11c1965687b0a472add948d4240dfe65a2fcb298 (patch) | |
tree | 69a71a34591bbdc6339dbe72de36819479f96198 /arch | |
parent | aec5e0e1c179fac4bbca4007a3f0d3107275a73c (diff) |
sh: Fixup cpu_data references for the non-boot CPUs.
There are a lot of bogus cpu_data-> references that only end up working
for the boot CPU, convert these to current_cpu_data to fixup SMP.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/sh/kernel/cpu/init.c | 30 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh2/probe.c | 32 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh2a/probe.c | 16 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh3/probe.c | 42 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4/probe.c | 185 | ||||
-rw-r--r-- | arch/sh/kernel/process.c | 5 | ||||
-rw-r--r-- | arch/sh/kernel/setup.c | 49 | ||||
-rw-r--r-- | arch/sh/kernel/signal.c | 6 | ||||
-rw-r--r-- | arch/sh/kernel/traps.c | 2 | ||||
-rw-r--r-- | arch/sh/mm/cache-debugfs.c | 4 | ||||
-rw-r--r-- | arch/sh/mm/cache-sh3.c | 8 | ||||
-rw-r--r-- | arch/sh/mm/cache-sh4.c | 65 | ||||
-rw-r--r-- | arch/sh/mm/cache-sh7705.c | 20 | ||||
-rw-r--r-- | arch/sh/mm/pg-sh4.c | 2 | ||||
-rw-r--r-- | arch/sh/mm/pg-sh7705.c | 6 | ||||
-rw-r--r-- | arch/sh/mm/tlb-sh3.c | 2 | ||||
-rw-r--r-- | arch/sh/oprofile/op_model_sh7750.c | 2 |
17 files changed, 244 insertions, 232 deletions
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index 6c3c7687e81f..4b339a640b13 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c | |||
@@ -48,7 +48,7 @@ static void __init cache_init(void) | |||
48 | { | 48 | { |
49 | unsigned long ccr, flags; | 49 | unsigned long ccr, flags; |
50 | 50 | ||
51 | if (cpu_data->type == CPU_SH_NONE) | 51 | if (current_cpu_data.type == CPU_SH_NONE) |
52 | panic("Unknown CPU"); | 52 | panic("Unknown CPU"); |
53 | 53 | ||
54 | jump_to_P2(); | 54 | jump_to_P2(); |
@@ -68,7 +68,7 @@ static void __init cache_init(void) | |||
68 | if (ccr & CCR_CACHE_ENABLE) { | 68 | if (ccr & CCR_CACHE_ENABLE) { |
69 | unsigned long ways, waysize, addrstart; | 69 | unsigned long ways, waysize, addrstart; |
70 | 70 | ||
71 | waysize = cpu_data->dcache.sets; | 71 | waysize = current_cpu_data.dcache.sets; |
72 | 72 | ||
73 | #ifdef CCR_CACHE_ORA | 73 | #ifdef CCR_CACHE_ORA |
74 | /* | 74 | /* |
@@ -79,7 +79,7 @@ static void __init cache_init(void) | |||
79 | waysize >>= 1; | 79 | waysize >>= 1; |
80 | #endif | 80 | #endif |
81 | 81 | ||
82 | waysize <<= cpu_data->dcache.entry_shift; | 82 | waysize <<= current_cpu_data.dcache.entry_shift; |
83 | 83 | ||
84 | #ifdef CCR_CACHE_EMODE | 84 | #ifdef CCR_CACHE_EMODE |
85 | /* If EMODE is not set, we only have 1 way to flush. */ | 85 | /* If EMODE is not set, we only have 1 way to flush. */ |
@@ -87,7 +87,7 @@ static void __init cache_init(void) | |||
87 | ways = 1; | 87 | ways = 1; |
88 | else | 88 | else |
89 | #endif | 89 | #endif |
90 | ways = cpu_data->dcache.ways; | 90 | ways = current_cpu_data.dcache.ways; |
91 | 91 | ||
92 | addrstart = CACHE_OC_ADDRESS_ARRAY; | 92 | addrstart = CACHE_OC_ADDRESS_ARRAY; |
93 | do { | 93 | do { |
@@ -95,10 +95,10 @@ static void __init cache_init(void) | |||
95 | 95 | ||
96 | for (addr = addrstart; | 96 | for (addr = addrstart; |
97 | addr < addrstart + waysize; | 97 | addr < addrstart + waysize; |
98 | addr += cpu_data->dcache.linesz) | 98 | addr += current_cpu_data.dcache.linesz) |
99 | ctrl_outl(0, addr); | 99 | ctrl_outl(0, addr); |
100 | 100 | ||
101 | addrstart += cpu_data->dcache.way_incr; | 101 | addrstart += current_cpu_data.dcache.way_incr; |
102 | } while (--ways); | 102 | } while (--ways); |
103 | } | 103 | } |
104 | 104 | ||
@@ -110,7 +110,7 @@ static void __init cache_init(void) | |||
110 | 110 | ||
111 | #ifdef CCR_CACHE_EMODE | 111 | #ifdef CCR_CACHE_EMODE |
112 | /* Force EMODE if possible */ | 112 | /* Force EMODE if possible */ |
113 | if (cpu_data->dcache.ways > 1) | 113 | if (current_cpu_data.dcache.ways > 1) |
114 | flags |= CCR_CACHE_EMODE; | 114 | flags |= CCR_CACHE_EMODE; |
115 | else | 115 | else |
116 | flags &= ~CCR_CACHE_EMODE; | 116 | flags &= ~CCR_CACHE_EMODE; |
@@ -127,10 +127,10 @@ static void __init cache_init(void) | |||
127 | #ifdef CONFIG_SH_OCRAM | 127 | #ifdef CONFIG_SH_OCRAM |
128 | /* Turn on OCRAM -- halve the OC */ | 128 | /* Turn on OCRAM -- halve the OC */ |
129 | flags |= CCR_CACHE_ORA; | 129 | flags |= CCR_CACHE_ORA; |
130 | cpu_data->dcache.sets >>= 1; | 130 | current_cpu_data.dcache.sets >>= 1; |
131 | 131 | ||
132 | cpu_data->dcache.way_size = cpu_data->dcache.sets * | 132 | current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * |
133 | cpu_data->dcache.linesz; | 133 | current_cpu_data.dcache.linesz; |
134 | #endif | 134 | #endif |
135 | 135 | ||
136 | ctrl_outl(flags, CCR); | 136 | ctrl_outl(flags, CCR); |
@@ -172,7 +172,7 @@ static void __init dsp_init(void) | |||
172 | 172 | ||
173 | /* If the DSP bit is still set, this CPU has a DSP */ | 173 | /* If the DSP bit is still set, this CPU has a DSP */ |
174 | if (sr & SR_DSP) | 174 | if (sr & SR_DSP) |
175 | cpu_data->flags |= CPU_HAS_DSP; | 175 | current_cpu_data.flags |= CPU_HAS_DSP; |
176 | 176 | ||
177 | /* Now that we've determined the DSP status, clear the DSP bit. */ | 177 | /* Now that we've determined the DSP status, clear the DSP bit. */ |
178 | release_dsp(); | 178 | release_dsp(); |
@@ -204,18 +204,18 @@ asmlinkage void __init sh_cpu_init(void) | |||
204 | cache_init(); | 204 | cache_init(); |
205 | 205 | ||
206 | shm_align_mask = max_t(unsigned long, | 206 | shm_align_mask = max_t(unsigned long, |
207 | cpu_data->dcache.way_size - 1, | 207 | current_cpu_data.dcache.way_size - 1, |
208 | PAGE_SIZE - 1); | 208 | PAGE_SIZE - 1); |
209 | 209 | ||
210 | /* Disable the FPU */ | 210 | /* Disable the FPU */ |
211 | if (fpu_disabled) { | 211 | if (fpu_disabled) { |
212 | printk("FPU Disabled\n"); | 212 | printk("FPU Disabled\n"); |
213 | cpu_data->flags &= ~CPU_HAS_FPU; | 213 | current_cpu_data.flags &= ~CPU_HAS_FPU; |
214 | disable_fpu(); | 214 | disable_fpu(); |
215 | } | 215 | } |
216 | 216 | ||
217 | /* FPU initialization */ | 217 | /* FPU initialization */ |
218 | if ((cpu_data->flags & CPU_HAS_FPU)) { | 218 | if ((current_cpu_data.flags & CPU_HAS_FPU)) { |
219 | clear_thread_flag(TIF_USEDFPU); | 219 | clear_thread_flag(TIF_USEDFPU); |
220 | clear_used_math(); | 220 | clear_used_math(); |
221 | } | 221 | } |
@@ -233,7 +233,7 @@ asmlinkage void __init sh_cpu_init(void) | |||
233 | /* Disable the DSP */ | 233 | /* Disable the DSP */ |
234 | if (dsp_disabled) { | 234 | if (dsp_disabled) { |
235 | printk("DSP Disabled\n"); | 235 | printk("DSP Disabled\n"); |
236 | cpu_data->flags &= ~CPU_HAS_DSP; | 236 | current_cpu_data.flags &= ~CPU_HAS_DSP; |
237 | release_dsp(); | 237 | release_dsp(); |
238 | } | 238 | } |
239 | #endif | 239 | #endif |
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c index ba527d9b5024..108e81b682ed 100644 --- a/arch/sh/kernel/cpu/sh2/probe.c +++ b/arch/sh/kernel/cpu/sh2/probe.c | |||
@@ -18,27 +18,27 @@ | |||
18 | int __init detect_cpu_and_cache_system(void) | 18 | int __init detect_cpu_and_cache_system(void) |
19 | { | 19 | { |
20 | #if defined(CONFIG_CPU_SUBTYPE_SH7604) | 20 | #if defined(CONFIG_CPU_SUBTYPE_SH7604) |
21 | cpu_data->type = CPU_SH7604; | 21 | current_cpu_data.type = CPU_SH7604; |
22 | cpu_data->dcache.ways = 4; | 22 | current_cpu_data.dcache.ways = 4; |
23 | cpu_data->dcache.way_incr = (1<<10); | 23 | current_cpu_data.dcache.way_incr = (1<<10); |
24 | cpu_data->dcache.sets = 64; | 24 | current_cpu_data.dcache.sets = 64; |
25 | cpu_data->dcache.entry_shift = 4; | 25 | current_cpu_data.dcache.entry_shift = 4; |
26 | cpu_data->dcache.linesz = L1_CACHE_BYTES; | 26 | current_cpu_data.dcache.linesz = L1_CACHE_BYTES; |
27 | cpu_data->dcache.flags = 0; | 27 | current_cpu_data.dcache.flags = 0; |
28 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | 28 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) |
29 | cpu_data->type = CPU_SH7619; | 29 | current_cpu_data.type = CPU_SH7619; |
30 | cpu_data->dcache.ways = 4; | 30 | current_cpu_data.dcache.ways = 4; |
31 | cpu_data->dcache.way_incr = (1<<12); | 31 | current_cpu_data.dcache.way_incr = (1<<12); |
32 | cpu_data->dcache.sets = 256; | 32 | current_cpu_data.dcache.sets = 256; |
33 | cpu_data->dcache.entry_shift = 4; | 33 | current_cpu_data.dcache.entry_shift = 4; |
34 | cpu_data->dcache.linesz = L1_CACHE_BYTES; | 34 | current_cpu_data.dcache.linesz = L1_CACHE_BYTES; |
35 | cpu_data->dcache.flags = 0; | 35 | current_cpu_data.dcache.flags = 0; |
36 | #endif | 36 | #endif |
37 | /* | 37 | /* |
38 | * SH-2 doesn't have separate caches | 38 | * SH-2 doesn't have separate caches |
39 | */ | 39 | */ |
40 | cpu_data->dcache.flags |= SH_CACHE_COMBINED; | 40 | current_cpu_data.dcache.flags |= SH_CACHE_COMBINED; |
41 | cpu_data->icache = cpu_data->dcache; | 41 | current_cpu_data.icache = current_cpu_data.dcache; |
42 | 42 | ||
43 | return 0; | 43 | return 0; |
44 | } | 44 | } |
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c index 87c6c0542089..426f6db01fc6 100644 --- a/arch/sh/kernel/cpu/sh2a/probe.c +++ b/arch/sh/kernel/cpu/sh2a/probe.c | |||
@@ -17,14 +17,14 @@ | |||
17 | int __init detect_cpu_and_cache_system(void) | 17 | int __init detect_cpu_and_cache_system(void) |
18 | { | 18 | { |
19 | /* Just SH7206 for now .. */ | 19 | /* Just SH7206 for now .. */ |
20 | cpu_data->type = CPU_SH7206; | 20 | current_cpu_data.type = CPU_SH7206; |
21 | 21 | ||
22 | cpu_data->dcache.ways = 4; | 22 | current_cpu_data.dcache.ways = 4; |
23 | cpu_data->dcache.way_incr = (1 << 11); | 23 | current_cpu_data.dcache.way_incr = (1 << 11); |
24 | cpu_data->dcache.sets = 128; | 24 | current_cpu_data.dcache.sets = 128; |
25 | cpu_data->dcache.entry_shift = 4; | 25 | current_cpu_data.dcache.entry_shift = 4; |
26 | cpu_data->dcache.linesz = L1_CACHE_BYTES; | 26 | current_cpu_data.dcache.linesz = L1_CACHE_BYTES; |
27 | cpu_data->dcache.flags = 0; | 27 | current_cpu_data.dcache.flags = 0; |
28 | 28 | ||
29 | /* | 29 | /* |
30 | * The icache is the same as the dcache as far as this setup is | 30 | * The icache is the same as the dcache as far as this setup is |
@@ -32,7 +32,7 @@ int __init detect_cpu_and_cache_system(void) | |||
32 | * lacks the U bit that the dcache has, none of this has any bearing | 32 | * lacks the U bit that the dcache has, none of this has any bearing |
33 | * on the cache info. | 33 | * on the cache info. |
34 | */ | 34 | */ |
35 | cpu_data->icache = cpu_data->dcache; | 35 | current_cpu_data.icache = current_cpu_data.dcache; |
36 | 36 | ||
37 | return 0; | 37 | return 0; |
38 | } | 38 | } |
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c index e67098836290..821b0ab7b528 100644 --- a/arch/sh/kernel/cpu/sh3/probe.c +++ b/arch/sh/kernel/cpu/sh3/probe.c | |||
@@ -50,41 +50,41 @@ int __init detect_cpu_and_cache_system(void) | |||
50 | 50 | ||
51 | back_to_P1(); | 51 | back_to_P1(); |
52 | 52 | ||
53 | cpu_data->dcache.ways = 4; | 53 | current_cpu_data.dcache.ways = 4; |
54 | cpu_data->dcache.entry_shift = 4; | 54 | current_cpu_data.dcache.entry_shift = 4; |
55 | cpu_data->dcache.linesz = L1_CACHE_BYTES; | 55 | current_cpu_data.dcache.linesz = L1_CACHE_BYTES; |
56 | cpu_data->dcache.flags = 0; | 56 | current_cpu_data.dcache.flags = 0; |
57 | 57 | ||
58 | /* | 58 | /* |
59 | * 7709A/7729 has 16K cache (256-entry), while 7702 has only | 59 | * 7709A/7729 has 16K cache (256-entry), while 7702 has only |
60 | * 2K(direct) 7702 is not supported (yet) | 60 | * 2K(direct) 7702 is not supported (yet) |
61 | */ | 61 | */ |
62 | if (data0 == data1 && data2 == data3) { /* Shadow */ | 62 | if (data0 == data1 && data2 == data3) { /* Shadow */ |
63 | cpu_data->dcache.way_incr = (1 << 11); | 63 | current_cpu_data.dcache.way_incr = (1 << 11); |
64 | cpu_data->dcache.entry_mask = 0x7f0; | 64 | current_cpu_data.dcache.entry_mask = 0x7f0; |
65 | cpu_data->dcache.sets = 128; | 65 | current_cpu_data.dcache.sets = 128; |
66 | cpu_data->type = CPU_SH7708; | 66 | current_cpu_data.type = CPU_SH7708; |
67 | 67 | ||
68 | cpu_data->flags |= CPU_HAS_MMU_PAGE_ASSOC; | 68 | current_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC; |
69 | } else { /* 7709A or 7729 */ | 69 | } else { /* 7709A or 7729 */ |
70 | cpu_data->dcache.way_incr = (1 << 12); | 70 | current_cpu_data.dcache.way_incr = (1 << 12); |
71 | cpu_data->dcache.entry_mask = 0xff0; | 71 | current_cpu_data.dcache.entry_mask = 0xff0; |
72 | cpu_data->dcache.sets = 256; | 72 | current_cpu_data.dcache.sets = 256; |
73 | cpu_data->type = CPU_SH7729; | 73 | current_cpu_data.type = CPU_SH7729; |
74 | 74 | ||
75 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) | 75 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) |
76 | cpu_data->type = CPU_SH7706; | 76 | current_cpu_data.type = CPU_SH7706; |
77 | #endif | 77 | #endif |
78 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) | 78 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) |
79 | cpu_data->type = CPU_SH7710; | 79 | current_cpu_data.type = CPU_SH7710; |
80 | #endif | 80 | #endif |
81 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) | 81 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) |
82 | cpu_data->type = CPU_SH7705; | 82 | current_cpu_data.type = CPU_SH7705; |
83 | 83 | ||
84 | #if defined(CONFIG_SH7705_CACHE_32KB) | 84 | #if defined(CONFIG_SH7705_CACHE_32KB) |
85 | cpu_data->dcache.way_incr = (1 << 13); | 85 | current_cpu_data.dcache.way_incr = (1 << 13); |
86 | cpu_data->dcache.entry_mask = 0x1ff0; | 86 | current_cpu_data.dcache.entry_mask = 0x1ff0; |
87 | cpu_data->dcache.sets = 512; | 87 | current_cpu_data.dcache.sets = 512; |
88 | ctrl_outl(CCR_CACHE_32KB, CCR3); | 88 | ctrl_outl(CCR_CACHE_32KB, CCR3); |
89 | #else | 89 | #else |
90 | ctrl_outl(CCR_CACHE_16KB, CCR3); | 90 | ctrl_outl(CCR_CACHE_16KB, CCR3); |
@@ -95,8 +95,8 @@ int __init detect_cpu_and_cache_system(void) | |||
95 | /* | 95 | /* |
96 | * SH-3 doesn't have separate caches | 96 | * SH-3 doesn't have separate caches |
97 | */ | 97 | */ |
98 | cpu_data->dcache.flags |= SH_CACHE_COMBINED; | 98 | current_cpu_data.dcache.flags |= SH_CACHE_COMBINED; |
99 | cpu_data->icache = cpu_data->dcache; | 99 | current_cpu_data.icache = current_cpu_data.dcache; |
100 | 100 | ||
101 | return 0; | 101 | return 0; |
102 | } | 102 | } |
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index b26e2bc5894d..9d28c88d2f9d 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c | |||
@@ -10,11 +10,10 @@ | |||
10 | * License. See the file "COPYING" in the main directory of this archive | 10 | * License. See the file "COPYING" in the main directory of this archive |
11 | * for more details. | 11 | * for more details. |
12 | */ | 12 | */ |
13 | |||
14 | #include <linux/init.h> | 13 | #include <linux/init.h> |
14 | #include <linux/io.h> | ||
15 | #include <asm/processor.h> | 15 | #include <asm/processor.h> |
16 | #include <asm/cache.h> | 16 | #include <asm/cache.h> |
17 | #include <asm/io.h> | ||
18 | 17 | ||
19 | int __init detect_cpu_and_cache_system(void) | 18 | int __init detect_cpu_and_cache_system(void) |
20 | { | 19 | { |
@@ -36,20 +35,20 @@ int __init detect_cpu_and_cache_system(void) | |||
36 | /* | 35 | /* |
37 | * Setup some sane SH-4 defaults for the icache | 36 | * Setup some sane SH-4 defaults for the icache |
38 | */ | 37 | */ |
39 | cpu_data->icache.way_incr = (1 << 13); | 38 | current_cpu_data.icache.way_incr = (1 << 13); |
40 | cpu_data->icache.entry_shift = 5; | 39 | current_cpu_data.icache.entry_shift = 5; |
41 | cpu_data->icache.sets = 256; | 40 | current_cpu_data.icache.sets = 256; |
42 | cpu_data->icache.ways = 1; | 41 | current_cpu_data.icache.ways = 1; |
43 | cpu_data->icache.linesz = L1_CACHE_BYTES; | 42 | current_cpu_data.icache.linesz = L1_CACHE_BYTES; |
44 | 43 | ||
45 | /* | 44 | /* |
46 | * And again for the dcache .. | 45 | * And again for the dcache .. |
47 | */ | 46 | */ |
48 | cpu_data->dcache.way_incr = (1 << 14); | 47 | current_cpu_data.dcache.way_incr = (1 << 14); |
49 | cpu_data->dcache.entry_shift = 5; | 48 | current_cpu_data.dcache.entry_shift = 5; |
50 | cpu_data->dcache.sets = 512; | 49 | current_cpu_data.dcache.sets = 512; |
51 | cpu_data->dcache.ways = 1; | 50 | current_cpu_data.dcache.ways = 1; |
52 | cpu_data->dcache.linesz = L1_CACHE_BYTES; | 51 | current_cpu_data.dcache.linesz = L1_CACHE_BYTES; |
53 | 52 | ||
54 | /* | 53 | /* |
55 | * Setup some generic flags we can probe | 54 | * Setup some generic flags we can probe |
@@ -57,16 +56,16 @@ int __init detect_cpu_and_cache_system(void) | |||
57 | */ | 56 | */ |
58 | if (((pvr >> 16) & 0xff) == 0x10) { | 57 | if (((pvr >> 16) & 0xff) == 0x10) { |
59 | if ((cvr & 0x02000000) == 0) | 58 | if ((cvr & 0x02000000) == 0) |
60 | cpu_data->flags |= CPU_HAS_L2_CACHE; | 59 | current_cpu_data.flags |= CPU_HAS_L2_CACHE; |
61 | if ((cvr & 0x10000000) == 0) | 60 | if ((cvr & 0x10000000) == 0) |
62 | cpu_data->flags |= CPU_HAS_DSP; | 61 | current_cpu_data.flags |= CPU_HAS_DSP; |
63 | 62 | ||
64 | cpu_data->flags |= CPU_HAS_LLSC; | 63 | current_cpu_data.flags |= CPU_HAS_LLSC; |
65 | } | 64 | } |
66 | 65 | ||
67 | /* FPU detection works for everyone */ | 66 | /* FPU detection works for everyone */ |
68 | if ((cvr & 0x20000000) == 1) | 67 | if ((cvr & 0x20000000) == 1) |
69 | cpu_data->flags |= CPU_HAS_FPU; | 68 | current_cpu_data.flags |= CPU_HAS_FPU; |
70 | 69 | ||
71 | /* Mask off the upper chip ID */ | 70 | /* Mask off the upper chip ID */ |
72 | pvr &= 0xffff; | 71 | pvr &= 0xffff; |
@@ -77,147 +76,151 @@ int __init detect_cpu_and_cache_system(void) | |||
77 | */ | 76 | */ |
78 | switch (pvr) { | 77 | switch (pvr) { |
79 | case 0x205: | 78 | case 0x205: |
80 | cpu_data->type = CPU_SH7750; | 79 | current_cpu_data.type = CPU_SH7750; |
81 | cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | | 80 | current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | |
82 | CPU_HAS_PERF_COUNTER; | 81 | CPU_HAS_PERF_COUNTER; |
83 | break; | 82 | break; |
84 | case 0x206: | 83 | case 0x206: |
85 | cpu_data->type = CPU_SH7750S; | 84 | current_cpu_data.type = CPU_SH7750S; |
86 | cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | | 85 | current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | |
87 | CPU_HAS_PERF_COUNTER; | 86 | CPU_HAS_PERF_COUNTER; |
88 | break; | 87 | break; |
89 | case 0x1100: | 88 | case 0x1100: |
90 | cpu_data->type = CPU_SH7751; | 89 | current_cpu_data.type = CPU_SH7751; |
91 | cpu_data->flags |= CPU_HAS_FPU; | 90 | current_cpu_data.flags |= CPU_HAS_FPU; |
92 | break; | 91 | break; |
93 | case 0x2000: | 92 | case 0x2000: |
94 | cpu_data->type = CPU_SH73180; | 93 | current_cpu_data.type = CPU_SH73180; |
95 | cpu_data->icache.ways = 4; | 94 | current_cpu_data.icache.ways = 4; |
96 | cpu_data->dcache.ways = 4; | 95 | current_cpu_data.dcache.ways = 4; |
97 | cpu_data->flags |= CPU_HAS_LLSC; | 96 | current_cpu_data.flags |= CPU_HAS_LLSC; |
98 | break; | 97 | break; |
99 | case 0x2001: | 98 | case 0x2001: |
100 | case 0x2004: | 99 | case 0x2004: |
101 | cpu_data->type = CPU_SH7770; | 100 | current_cpu_data.type = CPU_SH7770; |
102 | cpu_data->icache.ways = 4; | 101 | current_cpu_data.icache.ways = 4; |
103 | cpu_data->dcache.ways = 4; | 102 | current_cpu_data.dcache.ways = 4; |
104 | 103 | ||
105 | cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_LLSC; | 104 | current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC; |
106 | break; | 105 | break; |
107 | case 0x2006: | 106 | case 0x2006: |
108 | case 0x200A: | 107 | case 0x200A: |
109 | if (prr == 0x61) | 108 | if (prr == 0x61) |
110 | cpu_data->type = CPU_SH7781; | 109 | current_cpu_data.type = CPU_SH7781; |
111 | else | 110 | else |
112 | cpu_data->type = CPU_SH7780; | 111 | current_cpu_data.type = CPU_SH7780; |
113 | 112 | ||
114 | cpu_data->icache.ways = 4; | 113 | current_cpu_data.icache.ways = 4; |
115 | cpu_data->dcache.ways = 4; | 114 | current_cpu_data.dcache.ways = 4; |
116 | 115 | ||
117 | cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | | 116 | current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | |
118 | CPU_HAS_LLSC; | 117 | CPU_HAS_LLSC; |
119 | break; | 118 | break; |
120 | case 0x3000: | 119 | case 0x3000: |
121 | case 0x3003: | 120 | case 0x3003: |
122 | case 0x3009: | 121 | case 0x3009: |
123 | cpu_data->type = CPU_SH7343; | 122 | current_cpu_data.type = CPU_SH7343; |
124 | cpu_data->icache.ways = 4; | 123 | current_cpu_data.icache.ways = 4; |
125 | cpu_data->dcache.ways = 4; | 124 | current_cpu_data.dcache.ways = 4; |
126 | cpu_data->flags |= CPU_HAS_LLSC; | 125 | current_cpu_data.flags |= CPU_HAS_LLSC; |
127 | break; | 126 | break; |
128 | case 0x3008: | 127 | case 0x3008: |
129 | if (prr == 0xa0) { | 128 | if (prr == 0xa0) { |
130 | cpu_data->type = CPU_SH7722; | 129 | current_cpu_data.type = CPU_SH7722; |
131 | cpu_data->icache.ways = 4; | 130 | current_cpu_data.icache.ways = 4; |
132 | cpu_data->dcache.ways = 4; | 131 | current_cpu_data.dcache.ways = 4; |
133 | cpu_data->flags |= CPU_HAS_LLSC; | 132 | current_cpu_data.flags |= CPU_HAS_LLSC; |
134 | } | 133 | } |
135 | break; | 134 | break; |
136 | case 0x8000: | 135 | case 0x8000: |
137 | cpu_data->type = CPU_ST40RA; | 136 | current_cpu_data.type = CPU_ST40RA; |
138 | cpu_data->flags |= CPU_HAS_FPU; | 137 | current_cpu_data.flags |= CPU_HAS_FPU; |
139 | break; | 138 | break; |
140 | case 0x8100: | 139 | case 0x8100: |
141 | cpu_data->type = CPU_ST40GX1; | 140 | current_cpu_data.type = CPU_ST40GX1; |
142 | cpu_data->flags |= CPU_HAS_FPU; | 141 | current_cpu_data.flags |= CPU_HAS_FPU; |
143 | break; | 142 | break; |
144 | case 0x700: | 143 | case 0x700: |
145 | cpu_data->type = CPU_SH4_501; | 144 | current_cpu_data.type = CPU_SH4_501; |
146 | cpu_data->icache.ways = 2; | 145 | current_cpu_data.icache.ways = 2; |
147 | cpu_data->dcache.ways = 2; | 146 | current_cpu_data.dcache.ways = 2; |
148 | break; | 147 | break; |
149 | case 0x600: | 148 | case 0x600: |
150 | cpu_data->type = CPU_SH4_202; | 149 | current_cpu_data.type = CPU_SH4_202; |
151 | cpu_data->icache.ways = 2; | 150 | current_cpu_data.icache.ways = 2; |
152 | cpu_data->dcache.ways = 2; | 151 | current_cpu_data.dcache.ways = 2; |
153 | cpu_data->flags |= CPU_HAS_FPU; | 152 | current_cpu_data.flags |= CPU_HAS_FPU; |
154 | break; | 153 | break; |
155 | case 0x500 ... 0x501: | 154 | case 0x500 ... 0x501: |
156 | switch (prr) { | 155 | switch (prr) { |
157 | case 0x10: | 156 | case 0x10: |
158 | cpu_data->type = CPU_SH7750R; | 157 | current_cpu_data.type = CPU_SH7750R; |
159 | break; | 158 | break; |
160 | case 0x11: | 159 | case 0x11: |
161 | cpu_data->type = CPU_SH7751R; | 160 | current_cpu_data.type = CPU_SH7751R; |
162 | break; | 161 | break; |
163 | case 0x50 ... 0x5f: | 162 | case 0x50 ... 0x5f: |
164 | cpu_data->type = CPU_SH7760; | 163 | current_cpu_data.type = CPU_SH7760; |
165 | break; | 164 | break; |
166 | } | 165 | } |
167 | 166 | ||
168 | cpu_data->icache.ways = 2; | 167 | current_cpu_data.icache.ways = 2; |
169 | cpu_data->dcache.ways = 2; | 168 | current_cpu_data.dcache.ways = 2; |
170 | 169 | ||
171 | cpu_data->flags |= CPU_HAS_FPU; | 170 | current_cpu_data.flags |= CPU_HAS_FPU; |
172 | 171 | ||
173 | break; | 172 | break; |
174 | default: | 173 | default: |
175 | cpu_data->type = CPU_SH_NONE; | 174 | current_cpu_data.type = CPU_SH_NONE; |
176 | break; | 175 | break; |
177 | } | 176 | } |
178 | 177 | ||
179 | #ifdef CONFIG_SH_DIRECT_MAPPED | 178 | #ifdef CONFIG_SH_DIRECT_MAPPED |
180 | cpu_data->icache.ways = 1; | 179 | current_cpu_data.icache.ways = 1; |
181 | cpu_data->dcache.ways = 1; | 180 | current_cpu_data.dcache.ways = 1; |
181 | #endif | ||
182 | |||
183 | #ifdef CONFIG_CPU_HAS_PTEA | ||
184 | current_cpu_data.flags |= CPU_HAS_PTEA; | ||
182 | #endif | 185 | #endif |
183 | 186 | ||
184 | /* | 187 | /* |
185 | * On anything that's not a direct-mapped cache, look to the CVR | 188 | * On anything that's not a direct-mapped cache, look to the CVR |
186 | * for I/D-cache specifics. | 189 | * for I/D-cache specifics. |
187 | */ | 190 | */ |
188 | if (cpu_data->icache.ways > 1) { | 191 | if (current_cpu_data.icache.ways > 1) { |
189 | size = sizes[(cvr >> 20) & 0xf]; | 192 | size = sizes[(cvr >> 20) & 0xf]; |
190 | cpu_data->icache.way_incr = (size >> 1); | 193 | current_cpu_data.icache.way_incr = (size >> 1); |
191 | cpu_data->icache.sets = (size >> 6); | 194 | current_cpu_data.icache.sets = (size >> 6); |
192 | 195 | ||
193 | } | 196 | } |
194 | 197 | ||
195 | /* Setup the rest of the I-cache info */ | 198 | /* Setup the rest of the I-cache info */ |
196 | cpu_data->icache.entry_mask = cpu_data->icache.way_incr - | 199 | current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - |
197 | cpu_data->icache.linesz; | 200 | current_cpu_data.icache.linesz; |
198 | 201 | ||
199 | cpu_data->icache.way_size = cpu_data->icache.sets * | 202 | current_cpu_data.icache.way_size = current_cpu_data.icache.sets * |
200 | cpu_data->icache.linesz; | 203 | current_cpu_data.icache.linesz; |
201 | 204 | ||
202 | /* And the rest of the D-cache */ | 205 | /* And the rest of the D-cache */ |
203 | if (cpu_data->dcache.ways > 1) { | 206 | if (current_cpu_data.dcache.ways > 1) { |
204 | size = sizes[(cvr >> 16) & 0xf]; | 207 | size = sizes[(cvr >> 16) & 0xf]; |
205 | cpu_data->dcache.way_incr = (size >> 1); | 208 | current_cpu_data.dcache.way_incr = (size >> 1); |
206 | cpu_data->dcache.sets = (size >> 6); | 209 | current_cpu_data.dcache.sets = (size >> 6); |
207 | } | 210 | } |
208 | 211 | ||
209 | cpu_data->dcache.entry_mask = cpu_data->dcache.way_incr - | 212 | current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - |
210 | cpu_data->dcache.linesz; | 213 | current_cpu_data.dcache.linesz; |
211 | 214 | ||
212 | cpu_data->dcache.way_size = cpu_data->dcache.sets * | 215 | current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * |
213 | cpu_data->dcache.linesz; | 216 | current_cpu_data.dcache.linesz; |
214 | 217 | ||
215 | /* | 218 | /* |
216 | * Setup the L2 cache desc | 219 | * Setup the L2 cache desc |
217 | * | 220 | * |
218 | * SH-4A's have an optional PIPT L2. | 221 | * SH-4A's have an optional PIPT L2. |
219 | */ | 222 | */ |
220 | if (cpu_data->flags & CPU_HAS_L2_CACHE) { | 223 | if (current_cpu_data.flags & CPU_HAS_L2_CACHE) { |
221 | /* | 224 | /* |
222 | * Size calculation is much more sensible | 225 | * Size calculation is much more sensible |
223 | * than it is for the L1. | 226 | * than it is for the L1. |
@@ -228,16 +231,22 @@ int __init detect_cpu_and_cache_system(void) | |||
228 | 231 | ||
229 | BUG_ON(!size); | 232 | BUG_ON(!size); |
230 | 233 | ||
231 | cpu_data->scache.way_incr = (1 << 16); | 234 | current_cpu_data.scache.way_incr = (1 << 16); |
232 | cpu_data->scache.entry_shift = 5; | 235 | current_cpu_data.scache.entry_shift = 5; |
233 | cpu_data->scache.ways = 4; | 236 | current_cpu_data.scache.ways = 4; |
234 | cpu_data->scache.linesz = L1_CACHE_BYTES; | 237 | current_cpu_data.scache.linesz = L1_CACHE_BYTES; |
235 | cpu_data->scache.entry_mask = | 238 | |
236 | (cpu_data->scache.way_incr - cpu_data->scache.linesz); | 239 | current_cpu_data.scache.entry_mask = |
237 | cpu_data->scache.sets = size / | 240 | (current_cpu_data.scache.way_incr - |
238 | (cpu_data->scache.linesz * cpu_data->scache.ways); | 241 | current_cpu_data.scache.linesz); |
239 | cpu_data->scache.way_size = | 242 | |
240 | (cpu_data->scache.sets * cpu_data->scache.linesz); | 243 | current_cpu_data.scache.sets = size / |
244 | (current_cpu_data.scache.linesz * | ||
245 | current_cpu_data.scache.ways); | ||
246 | |||
247 | current_cpu_data.scache.way_size = | ||
248 | (current_cpu_data.scache.sets * | ||
249 | current_cpu_data.scache.linesz); | ||
241 | } | 250 | } |
242 | 251 | ||
243 | return 0; | 252 | return 0; |
diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c index 0298f0faa6e6..9d6a438b3eaf 100644 --- a/arch/sh/kernel/process.c +++ b/arch/sh/kernel/process.c | |||
@@ -293,13 +293,14 @@ static void ubc_set_tracing(int asid, unsigned long pc) | |||
293 | 293 | ||
294 | #ifdef CONFIG_MMU | 294 | #ifdef CONFIG_MMU |
295 | /* We don't have any ASID settings for the SH-2! */ | 295 | /* We don't have any ASID settings for the SH-2! */ |
296 | if (cpu_data->type != CPU_SH7604) | 296 | if (current_cpu_data.type != CPU_SH7604) |
297 | ctrl_outb(asid, UBC_BASRA); | 297 | ctrl_outb(asid, UBC_BASRA); |
298 | #endif | 298 | #endif |
299 | 299 | ||
300 | ctrl_outl(0, UBC_BAMRA); | 300 | ctrl_outl(0, UBC_BAMRA); |
301 | 301 | ||
302 | if (cpu_data->type == CPU_SH7729 || cpu_data->type == CPU_SH7710) { | 302 | if (current_cpu_data.type == CPU_SH7729 || |
303 | current_cpu_data.type == CPU_SH7710) { | ||
303 | ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA); | 304 | ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA); |
304 | ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR); | 305 | ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR); |
305 | } else { | 306 | } else { |
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index d6b817aa568f..98802ab28211 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c | |||
@@ -1,14 +1,11 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/sh/kernel/setup.c | 2 | * arch/sh/kernel/setup.c |
3 | * | 3 | * |
4 | * Copyright (C) 1999 Niibe Yutaka | ||
5 | * Copyright (C) 2002, 2003 Paul Mundt | ||
6 | */ | ||
7 | |||
8 | /* | ||
9 | * This file handles the architecture-dependent parts of initialization | 4 | * This file handles the architecture-dependent parts of initialization |
5 | * | ||
6 | * Copyright (C) 1999 Niibe Yutaka | ||
7 | * Copyright (C) 2002 - 2006 Paul Mundt | ||
10 | */ | 8 | */ |
11 | |||
12 | #include <linux/screen_info.h> | 9 | #include <linux/screen_info.h> |
13 | #include <linux/ioport.h> | 10 | #include <linux/ioport.h> |
14 | #include <linux/init.h> | 11 | #include <linux/init.h> |
@@ -395,9 +392,9 @@ static const char *cpu_name[] = { | |||
395 | [CPU_SH_NONE] = "Unknown" | 392 | [CPU_SH_NONE] = "Unknown" |
396 | }; | 393 | }; |
397 | 394 | ||
398 | const char *get_cpu_subtype(void) | 395 | const char *get_cpu_subtype(struct sh_cpuinfo *c) |
399 | { | 396 | { |
400 | return cpu_name[boot_cpu_data.type]; | 397 | return cpu_name[c->type]; |
401 | } | 398 | } |
402 | 399 | ||
403 | #ifdef CONFIG_PROC_FS | 400 | #ifdef CONFIG_PROC_FS |
@@ -407,19 +404,19 @@ static const char *cpu_flags[] = { | |||
407 | "ptea", "llsc", "l2", NULL | 404 | "ptea", "llsc", "l2", NULL |
408 | }; | 405 | }; |
409 | 406 | ||
410 | static void show_cpuflags(struct seq_file *m) | 407 | static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c) |
411 | { | 408 | { |
412 | unsigned long i; | 409 | unsigned long i; |
413 | 410 | ||
414 | seq_printf(m, "cpu flags\t:"); | 411 | seq_printf(m, "cpu flags\t:"); |
415 | 412 | ||
416 | if (!cpu_data->flags) { | 413 | if (!c->flags) { |
417 | seq_printf(m, " %s\n", cpu_flags[0]); | 414 | seq_printf(m, " %s\n", cpu_flags[0]); |
418 | return; | 415 | return; |
419 | } | 416 | } |
420 | 417 | ||
421 | for (i = 0; cpu_flags[i]; i++) | 418 | for (i = 0; cpu_flags[i]; i++) |
422 | if ((cpu_data->flags & (1 << i))) | 419 | if ((c->flags & (1 << i))) |
423 | seq_printf(m, " %s", cpu_flags[i+1]); | 420 | seq_printf(m, " %s", cpu_flags[i+1]); |
424 | 421 | ||
425 | seq_printf(m, "\n"); | 422 | seq_printf(m, "\n"); |
@@ -441,16 +438,20 @@ static void show_cacheinfo(struct seq_file *m, const char *type, | |||
441 | */ | 438 | */ |
442 | static int show_cpuinfo(struct seq_file *m, void *v) | 439 | static int show_cpuinfo(struct seq_file *m, void *v) |
443 | { | 440 | { |
444 | unsigned int cpu = smp_processor_id(); | 441 | struct sh_cpuinfo *c = v; |
442 | unsigned int cpu = c - cpu_data; | ||
443 | |||
444 | if (!cpu_online(cpu)) | ||
445 | return 0; | ||
445 | 446 | ||
446 | if (!cpu && cpu_online(cpu)) | 447 | if (cpu == 0) |
447 | seq_printf(m, "machine\t\t: %s\n", get_system_type()); | 448 | seq_printf(m, "machine\t\t: %s\n", get_system_type()); |
448 | 449 | ||
449 | seq_printf(m, "processor\t: %d\n", cpu); | 450 | seq_printf(m, "processor\t: %d\n", cpu); |
450 | seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine); | 451 | seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine); |
451 | seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype()); | 452 | seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c)); |
452 | 453 | ||
453 | show_cpuflags(m); | 454 | show_cpuflags(m, c); |
454 | 455 | ||
455 | seq_printf(m, "cache type\t: "); | 456 | seq_printf(m, "cache type\t: "); |
456 | 457 | ||
@@ -459,22 +460,22 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
459 | * unified cache on the SH-2 and SH-3, as well as the harvard | 460 | * unified cache on the SH-2 and SH-3, as well as the harvard |
460 | * style cache on the SH-4. | 461 | * style cache on the SH-4. |
461 | */ | 462 | */ |
462 | if (boot_cpu_data.icache.flags & SH_CACHE_COMBINED) { | 463 | if (c->icache.flags & SH_CACHE_COMBINED) { |
463 | seq_printf(m, "unified\n"); | 464 | seq_printf(m, "unified\n"); |
464 | show_cacheinfo(m, "cache", boot_cpu_data.icache); | 465 | show_cacheinfo(m, "cache", c->icache); |
465 | } else { | 466 | } else { |
466 | seq_printf(m, "split (harvard)\n"); | 467 | seq_printf(m, "split (harvard)\n"); |
467 | show_cacheinfo(m, "icache", boot_cpu_data.icache); | 468 | show_cacheinfo(m, "icache", c->icache); |
468 | show_cacheinfo(m, "dcache", boot_cpu_data.dcache); | 469 | show_cacheinfo(m, "dcache", c->dcache); |
469 | } | 470 | } |
470 | 471 | ||
471 | /* Optional secondary cache */ | 472 | /* Optional secondary cache */ |
472 | if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) | 473 | if (c->flags & CPU_HAS_L2_CACHE) |
473 | show_cacheinfo(m, "scache", boot_cpu_data.scache); | 474 | show_cacheinfo(m, "scache", c->scache); |
474 | 475 | ||
475 | seq_printf(m, "bogomips\t: %lu.%02lu\n", | 476 | seq_printf(m, "bogomips\t: %lu.%02lu\n", |
476 | boot_cpu_data.loops_per_jiffy/(500000/HZ), | 477 | c->loops_per_jiffy/(500000/HZ), |
477 | (boot_cpu_data.loops_per_jiffy/(5000/HZ)) % 100); | 478 | (c->loops_per_jiffy/(5000/HZ)) % 100); |
478 | 479 | ||
479 | return show_clocks(m); | 480 | return show_clocks(m); |
480 | } | 481 | } |
diff --git a/arch/sh/kernel/signal.c b/arch/sh/kernel/signal.c index 379c88bf5d9a..32f10a03fbb5 100644 --- a/arch/sh/kernel/signal.c +++ b/arch/sh/kernel/signal.c | |||
@@ -127,7 +127,7 @@ static inline int restore_sigcontext_fpu(struct sigcontext __user *sc) | |||
127 | { | 127 | { |
128 | struct task_struct *tsk = current; | 128 | struct task_struct *tsk = current; |
129 | 129 | ||
130 | if (!(cpu_data->flags & CPU_HAS_FPU)) | 130 | if (!(current_cpu_data.flags & CPU_HAS_FPU)) |
131 | return 0; | 131 | return 0; |
132 | 132 | ||
133 | set_used_math(); | 133 | set_used_math(); |
@@ -140,7 +140,7 @@ static inline int save_sigcontext_fpu(struct sigcontext __user *sc, | |||
140 | { | 140 | { |
141 | struct task_struct *tsk = current; | 141 | struct task_struct *tsk = current; |
142 | 142 | ||
143 | if (!(cpu_data->flags & CPU_HAS_FPU)) | 143 | if (!(current_cpu_data.flags & CPU_HAS_FPU)) |
144 | return 0; | 144 | return 0; |
145 | 145 | ||
146 | if (!used_math()) { | 146 | if (!used_math()) { |
@@ -181,7 +181,7 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *r0_p | |||
181 | #undef COPY | 181 | #undef COPY |
182 | 182 | ||
183 | #ifdef CONFIG_SH_FPU | 183 | #ifdef CONFIG_SH_FPU |
184 | if (cpu_data->flags & CPU_HAS_FPU) { | 184 | if (current_cpu_data.flags & CPU_HAS_FPU) { |
185 | int owned_fp; | 185 | int owned_fp; |
186 | struct task_struct *tsk = current; | 186 | struct task_struct *tsk = current; |
187 | 187 | ||
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c index e91224faf6c4..e9f168f60f95 100644 --- a/arch/sh/kernel/traps.c +++ b/arch/sh/kernel/traps.c | |||
@@ -641,7 +641,7 @@ int is_dsp_inst(struct pt_regs *regs) | |||
641 | * Safe guard if DSP mode is already enabled or we're lacking | 641 | * Safe guard if DSP mode is already enabled or we're lacking |
642 | * the DSP altogether. | 642 | * the DSP altogether. |
643 | */ | 643 | */ |
644 | if (!(cpu_data->flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) | 644 | if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) |
645 | return 0; | 645 | return 0; |
646 | 646 | ||
647 | get_user(inst, ((unsigned short *) regs->pc)); | 647 | get_user(inst, ((unsigned short *) regs->pc)); |
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c index 909dcfa8c8c6..de6d2c9aa477 100644 --- a/arch/sh/mm/cache-debugfs.c +++ b/arch/sh/mm/cache-debugfs.c | |||
@@ -46,10 +46,10 @@ static int cache_seq_show(struct seq_file *file, void *iter) | |||
46 | 46 | ||
47 | if (cache_type == CACHE_TYPE_DCACHE) { | 47 | if (cache_type == CACHE_TYPE_DCACHE) { |
48 | base = CACHE_OC_ADDRESS_ARRAY; | 48 | base = CACHE_OC_ADDRESS_ARRAY; |
49 | cache = &cpu_data->dcache; | 49 | cache = ¤t_cpu_data.dcache; |
50 | } else { | 50 | } else { |
51 | base = CACHE_IC_ADDRESS_ARRAY; | 51 | base = CACHE_IC_ADDRESS_ARRAY; |
52 | cache = &cpu_data->icache; | 52 | cache = ¤t_cpu_data.icache; |
53 | } | 53 | } |
54 | 54 | ||
55 | /* | 55 | /* |
diff --git a/arch/sh/mm/cache-sh3.c b/arch/sh/mm/cache-sh3.c index 838731fc608d..6d1dbec08ad4 100644 --- a/arch/sh/mm/cache-sh3.c +++ b/arch/sh/mm/cache-sh3.c | |||
@@ -44,11 +44,11 @@ void __flush_wback_region(void *start, int size) | |||
44 | 44 | ||
45 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { | 45 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { |
46 | unsigned long addrstart = CACHE_OC_ADDRESS_ARRAY; | 46 | unsigned long addrstart = CACHE_OC_ADDRESS_ARRAY; |
47 | for (j = 0; j < cpu_data->dcache.ways; j++) { | 47 | for (j = 0; j < current_cpu_data.dcache.ways; j++) { |
48 | unsigned long data, addr, p; | 48 | unsigned long data, addr, p; |
49 | 49 | ||
50 | p = __pa(v); | 50 | p = __pa(v); |
51 | addr = addrstart | (v & cpu_data->dcache.entry_mask); | 51 | addr = addrstart | (v & current_cpu_data.dcache.entry_mask); |
52 | local_irq_save(flags); | 52 | local_irq_save(flags); |
53 | data = ctrl_inl(addr); | 53 | data = ctrl_inl(addr); |
54 | 54 | ||
@@ -60,7 +60,7 @@ void __flush_wback_region(void *start, int size) | |||
60 | break; | 60 | break; |
61 | } | 61 | } |
62 | local_irq_restore(flags); | 62 | local_irq_restore(flags); |
63 | addrstart += cpu_data->dcache.way_incr; | 63 | addrstart += current_cpu_data.dcache.way_incr; |
64 | } | 64 | } |
65 | } | 65 | } |
66 | } | 66 | } |
@@ -85,7 +85,7 @@ void __flush_purge_region(void *start, int size) | |||
85 | 85 | ||
86 | data = (v & 0xfffffc00); /* _Virtual_ address, ~U, ~V */ | 86 | data = (v & 0xfffffc00); /* _Virtual_ address, ~U, ~V */ |
87 | addr = CACHE_OC_ADDRESS_ARRAY | | 87 | addr = CACHE_OC_ADDRESS_ARRAY | |
88 | (v & cpu_data->dcache.entry_mask) | SH_CACHE_ASSOC; | 88 | (v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC; |
89 | ctrl_outl(data, addr); | 89 | ctrl_outl(data, addr); |
90 | } | 90 | } |
91 | } | 91 | } |
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c index 72bb48773337..e0cd4b7f4aeb 100644 --- a/arch/sh/mm/cache-sh4.c +++ b/arch/sh/mm/cache-sh4.c | |||
@@ -54,21 +54,21 @@ static void __init emit_cache_params(void) | |||
54 | ctrl_inl(CCN_CVR), | 54 | ctrl_inl(CCN_CVR), |
55 | ctrl_inl(CCN_PRR)); | 55 | ctrl_inl(CCN_PRR)); |
56 | printk("I-cache : n_ways=%d n_sets=%d way_incr=%d\n", | 56 | printk("I-cache : n_ways=%d n_sets=%d way_incr=%d\n", |
57 | cpu_data->icache.ways, | 57 | current_cpu_data.icache.ways, |
58 | cpu_data->icache.sets, | 58 | current_cpu_data.icache.sets, |
59 | cpu_data->icache.way_incr); | 59 | current_cpu_data.icache.way_incr); |
60 | printk("I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n", | 60 | printk("I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n", |
61 | cpu_data->icache.entry_mask, | 61 | current_cpu_data.icache.entry_mask, |
62 | cpu_data->icache.alias_mask, | 62 | current_cpu_data.icache.alias_mask, |
63 | cpu_data->icache.n_aliases); | 63 | current_cpu_data.icache.n_aliases); |
64 | printk("D-cache : n_ways=%d n_sets=%d way_incr=%d\n", | 64 | printk("D-cache : n_ways=%d n_sets=%d way_incr=%d\n", |
65 | cpu_data->dcache.ways, | 65 | current_cpu_data.dcache.ways, |
66 | cpu_data->dcache.sets, | 66 | current_cpu_data.dcache.sets, |
67 | cpu_data->dcache.way_incr); | 67 | current_cpu_data.dcache.way_incr); |
68 | printk("D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n", | 68 | printk("D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n", |
69 | cpu_data->dcache.entry_mask, | 69 | current_cpu_data.dcache.entry_mask, |
70 | cpu_data->dcache.alias_mask, | 70 | current_cpu_data.dcache.alias_mask, |
71 | cpu_data->dcache.n_aliases); | 71 | current_cpu_data.dcache.n_aliases); |
72 | 72 | ||
73 | if (!__flush_dcache_segment_fn) | 73 | if (!__flush_dcache_segment_fn) |
74 | panic("unknown number of cache ways\n"); | 74 | panic("unknown number of cache ways\n"); |
@@ -87,10 +87,10 @@ void __init p3_cache_init(void) | |||
87 | { | 87 | { |
88 | int i; | 88 | int i; |
89 | 89 | ||
90 | compute_alias(&cpu_data->icache); | 90 | compute_alias(¤t_cpu_data.icache); |
91 | compute_alias(&cpu_data->dcache); | 91 | compute_alias(¤t_cpu_data.dcache); |
92 | 92 | ||
93 | switch (cpu_data->dcache.ways) { | 93 | switch (current_cpu_data.dcache.ways) { |
94 | case 1: | 94 | case 1: |
95 | __flush_dcache_segment_fn = __flush_dcache_segment_1way; | 95 | __flush_dcache_segment_fn = __flush_dcache_segment_1way; |
96 | break; | 96 | break; |
@@ -110,7 +110,7 @@ void __init p3_cache_init(void) | |||
110 | if (ioremap_page_range(P3SEG, P3SEG + (PAGE_SIZE * 4), 0, PAGE_KERNEL)) | 110 | if (ioremap_page_range(P3SEG, P3SEG + (PAGE_SIZE * 4), 0, PAGE_KERNEL)) |
111 | panic("%s failed.", __FUNCTION__); | 111 | panic("%s failed.", __FUNCTION__); |
112 | 112 | ||
113 | for (i = 0; i < cpu_data->dcache.n_aliases; i++) | 113 | for (i = 0; i < current_cpu_data.dcache.n_aliases; i++) |
114 | mutex_init(&p3map_mutex[i]); | 114 | mutex_init(&p3map_mutex[i]); |
115 | } | 115 | } |
116 | 116 | ||
@@ -200,13 +200,14 @@ void flush_cache_sigtramp(unsigned long addr) | |||
200 | : /* no output */ | 200 | : /* no output */ |
201 | : "m" (__m(v))); | 201 | : "m" (__m(v))); |
202 | 202 | ||
203 | index = CACHE_IC_ADDRESS_ARRAY | (v & cpu_data->icache.entry_mask); | 203 | index = CACHE_IC_ADDRESS_ARRAY | |
204 | (v & current_cpu_data.icache.entry_mask); | ||
204 | 205 | ||
205 | local_irq_save(flags); | 206 | local_irq_save(flags); |
206 | jump_to_P2(); | 207 | jump_to_P2(); |
207 | 208 | ||
208 | for (i = 0; i < cpu_data->icache.ways; | 209 | for (i = 0; i < current_cpu_data.icache.ways; |
209 | i++, index += cpu_data->icache.way_incr) | 210 | i++, index += current_cpu_data.icache.way_incr) |
210 | ctrl_outl(0, index); /* Clear out Valid-bit */ | 211 | ctrl_outl(0, index); /* Clear out Valid-bit */ |
211 | 212 | ||
212 | back_to_P1(); | 213 | back_to_P1(); |
@@ -223,7 +224,7 @@ static inline void flush_cache_4096(unsigned long start, | |||
223 | * All types of SH-4 require PC to be in P2 to operate on the I-cache. | 224 | * All types of SH-4 require PC to be in P2 to operate on the I-cache. |
224 | * Some types of SH-4 require PC to be in P2 to operate on the D-cache. | 225 | * Some types of SH-4 require PC to be in P2 to operate on the D-cache. |
225 | */ | 226 | */ |
226 | if ((cpu_data->flags & CPU_HAS_P2_FLUSH_BUG) || | 227 | if ((current_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) || |
227 | (start < CACHE_OC_ADDRESS_ARRAY)) | 228 | (start < CACHE_OC_ADDRESS_ARRAY)) |
228 | exec_offset = 0x20000000; | 229 | exec_offset = 0x20000000; |
229 | 230 | ||
@@ -255,7 +256,7 @@ void flush_dcache_page(struct page *page) | |||
255 | int i, n; | 256 | int i, n; |
256 | 257 | ||
257 | /* Loop all the D-cache */ | 258 | /* Loop all the D-cache */ |
258 | n = cpu_data->dcache.n_aliases; | 259 | n = current_cpu_data.dcache.n_aliases; |
259 | for (i = 0; i < n; i++, addr += 4096) | 260 | for (i = 0; i < n; i++, addr += 4096) |
260 | flush_cache_4096(addr, phys); | 261 | flush_cache_4096(addr, phys); |
261 | } | 262 | } |
@@ -287,7 +288,7 @@ static inline void flush_icache_all(void) | |||
287 | 288 | ||
288 | void flush_dcache_all(void) | 289 | void flush_dcache_all(void) |
289 | { | 290 | { |
290 | (*__flush_dcache_segment_fn)(0UL, cpu_data->dcache.way_size); | 291 | (*__flush_dcache_segment_fn)(0UL, current_cpu_data.dcache.way_size); |
291 | wmb(); | 292 | wmb(); |
292 | } | 293 | } |
293 | 294 | ||
@@ -301,8 +302,8 @@ static void __flush_cache_mm(struct mm_struct *mm, unsigned long start, | |||
301 | unsigned long end) | 302 | unsigned long end) |
302 | { | 303 | { |
303 | unsigned long d = 0, p = start & PAGE_MASK; | 304 | unsigned long d = 0, p = start & PAGE_MASK; |
304 | unsigned long alias_mask = cpu_data->dcache.alias_mask; | 305 | unsigned long alias_mask = current_cpu_data.dcache.alias_mask; |
305 | unsigned long n_aliases = cpu_data->dcache.n_aliases; | 306 | unsigned long n_aliases = current_cpu_data.dcache.n_aliases; |
306 | unsigned long select_bit; | 307 | unsigned long select_bit; |
307 | unsigned long all_aliases_mask; | 308 | unsigned long all_aliases_mask; |
308 | unsigned long addr_offset; | 309 | unsigned long addr_offset; |
@@ -389,7 +390,7 @@ void flush_cache_mm(struct mm_struct *mm) | |||
389 | * If cache is only 4k-per-way, there are never any 'aliases'. Since | 390 | * If cache is only 4k-per-way, there are never any 'aliases'. Since |
390 | * the cache is physically tagged, the data can just be left in there. | 391 | * the cache is physically tagged, the data can just be left in there. |
391 | */ | 392 | */ |
392 | if (cpu_data->dcache.n_aliases == 0) | 393 | if (current_cpu_data.dcache.n_aliases == 0) |
393 | return; | 394 | return; |
394 | 395 | ||
395 | /* | 396 | /* |
@@ -426,7 +427,7 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long address, | |||
426 | unsigned long phys = pfn << PAGE_SHIFT; | 427 | unsigned long phys = pfn << PAGE_SHIFT; |
427 | unsigned int alias_mask; | 428 | unsigned int alias_mask; |
428 | 429 | ||
429 | alias_mask = cpu_data->dcache.alias_mask; | 430 | alias_mask = current_cpu_data.dcache.alias_mask; |
430 | 431 | ||
431 | /* We only need to flush D-cache when we have alias */ | 432 | /* We only need to flush D-cache when we have alias */ |
432 | if ((address^phys) & alias_mask) { | 433 | if ((address^phys) & alias_mask) { |
@@ -440,7 +441,7 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long address, | |||
440 | phys); | 441 | phys); |
441 | } | 442 | } |
442 | 443 | ||
443 | alias_mask = cpu_data->icache.alias_mask; | 444 | alias_mask = current_cpu_data.icache.alias_mask; |
444 | if (vma->vm_flags & VM_EXEC) { | 445 | if (vma->vm_flags & VM_EXEC) { |
445 | /* | 446 | /* |
446 | * Evict entries from the portion of the cache from which code | 447 | * Evict entries from the portion of the cache from which code |
@@ -472,7 +473,7 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, | |||
472 | * If cache is only 4k-per-way, there are never any 'aliases'. Since | 473 | * If cache is only 4k-per-way, there are never any 'aliases'. Since |
473 | * the cache is physically tagged, the data can just be left in there. | 474 | * the cache is physically tagged, the data can just be left in there. |
474 | */ | 475 | */ |
475 | if (cpu_data->dcache.n_aliases == 0) | 476 | if (current_cpu_data.dcache.n_aliases == 0) |
476 | return; | 477 | return; |
477 | 478 | ||
478 | /* | 479 | /* |
@@ -533,7 +534,7 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys, | |||
533 | unsigned long a, ea, p; | 534 | unsigned long a, ea, p; |
534 | unsigned long temp_pc; | 535 | unsigned long temp_pc; |
535 | 536 | ||
536 | dcache = &cpu_data->dcache; | 537 | dcache = ¤t_cpu_data.dcache; |
537 | /* Write this way for better assembly. */ | 538 | /* Write this way for better assembly. */ |
538 | way_count = dcache->ways; | 539 | way_count = dcache->ways; |
539 | way_incr = dcache->way_incr; | 540 | way_incr = dcache->way_incr; |
@@ -608,7 +609,7 @@ static void __flush_dcache_segment_1way(unsigned long start, | |||
608 | base_addr = ((base_addr >> 16) << 16); | 609 | base_addr = ((base_addr >> 16) << 16); |
609 | base_addr |= start; | 610 | base_addr |= start; |
610 | 611 | ||
611 | dcache = &cpu_data->dcache; | 612 | dcache = ¤t_cpu_data.dcache; |
612 | linesz = dcache->linesz; | 613 | linesz = dcache->linesz; |
613 | way_incr = dcache->way_incr; | 614 | way_incr = dcache->way_incr; |
614 | way_size = dcache->way_size; | 615 | way_size = dcache->way_size; |
@@ -650,7 +651,7 @@ static void __flush_dcache_segment_2way(unsigned long start, | |||
650 | base_addr = ((base_addr >> 16) << 16); | 651 | base_addr = ((base_addr >> 16) << 16); |
651 | base_addr |= start; | 652 | base_addr |= start; |
652 | 653 | ||
653 | dcache = &cpu_data->dcache; | 654 | dcache = ¤t_cpu_data.dcache; |
654 | linesz = dcache->linesz; | 655 | linesz = dcache->linesz; |
655 | way_incr = dcache->way_incr; | 656 | way_incr = dcache->way_incr; |
656 | way_size = dcache->way_size; | 657 | way_size = dcache->way_size; |
@@ -709,7 +710,7 @@ static void __flush_dcache_segment_4way(unsigned long start, | |||
709 | base_addr = ((base_addr >> 16) << 16); | 710 | base_addr = ((base_addr >> 16) << 16); |
710 | base_addr |= start; | 711 | base_addr |= start; |
711 | 712 | ||
712 | dcache = &cpu_data->dcache; | 713 | dcache = ¤t_cpu_data.dcache; |
713 | linesz = dcache->linesz; | 714 | linesz = dcache->linesz; |
714 | way_incr = dcache->way_incr; | 715 | way_incr = dcache->way_incr; |
715 | way_size = dcache->way_size; | 716 | way_size = dcache->way_size; |
diff --git a/arch/sh/mm/cache-sh7705.c b/arch/sh/mm/cache-sh7705.c index 2808b580d984..31f8deb7a158 100644 --- a/arch/sh/mm/cache-sh7705.c +++ b/arch/sh/mm/cache-sh7705.c | |||
@@ -32,9 +32,9 @@ static inline void cache_wback_all(void) | |||
32 | { | 32 | { |
33 | unsigned long ways, waysize, addrstart; | 33 | unsigned long ways, waysize, addrstart; |
34 | 34 | ||
35 | ways = cpu_data->dcache.ways; | 35 | ways = current_cpu_data.dcache.ways; |
36 | waysize = cpu_data->dcache.sets; | 36 | waysize = current_cpu_data.dcache.sets; |
37 | waysize <<= cpu_data->dcache.entry_shift; | 37 | waysize <<= current_cpu_data.dcache.entry_shift; |
38 | 38 | ||
39 | addrstart = CACHE_OC_ADDRESS_ARRAY; | 39 | addrstart = CACHE_OC_ADDRESS_ARRAY; |
40 | 40 | ||
@@ -43,7 +43,7 @@ static inline void cache_wback_all(void) | |||
43 | 43 | ||
44 | for (addr = addrstart; | 44 | for (addr = addrstart; |
45 | addr < addrstart + waysize; | 45 | addr < addrstart + waysize; |
46 | addr += cpu_data->dcache.linesz) { | 46 | addr += current_cpu_data.dcache.linesz) { |
47 | unsigned long data; | 47 | unsigned long data; |
48 | int v = SH_CACHE_UPDATED | SH_CACHE_VALID; | 48 | int v = SH_CACHE_UPDATED | SH_CACHE_VALID; |
49 | 49 | ||
@@ -53,7 +53,7 @@ static inline void cache_wback_all(void) | |||
53 | ctrl_outl(data & ~v, addr); | 53 | ctrl_outl(data & ~v, addr); |
54 | } | 54 | } |
55 | 55 | ||
56 | addrstart += cpu_data->dcache.way_incr; | 56 | addrstart += current_cpu_data.dcache.way_incr; |
57 | } while (--ways); | 57 | } while (--ways); |
58 | } | 58 | } |
59 | 59 | ||
@@ -93,9 +93,9 @@ static void __flush_dcache_page(unsigned long phys) | |||
93 | local_irq_save(flags); | 93 | local_irq_save(flags); |
94 | jump_to_P2(); | 94 | jump_to_P2(); |
95 | 95 | ||
96 | ways = cpu_data->dcache.ways; | 96 | ways = current_cpu_data.dcache.ways; |
97 | waysize = cpu_data->dcache.sets; | 97 | waysize = current_cpu_data.dcache.sets; |
98 | waysize <<= cpu_data->dcache.entry_shift; | 98 | waysize <<= current_cpu_data.dcache.entry_shift; |
99 | 99 | ||
100 | addrstart = CACHE_OC_ADDRESS_ARRAY; | 100 | addrstart = CACHE_OC_ADDRESS_ARRAY; |
101 | 101 | ||
@@ -104,7 +104,7 @@ static void __flush_dcache_page(unsigned long phys) | |||
104 | 104 | ||
105 | for (addr = addrstart; | 105 | for (addr = addrstart; |
106 | addr < addrstart + waysize; | 106 | addr < addrstart + waysize; |
107 | addr += cpu_data->dcache.linesz) { | 107 | addr += current_cpu_data.dcache.linesz) { |
108 | unsigned long data; | 108 | unsigned long data; |
109 | 109 | ||
110 | data = ctrl_inl(addr) & (0x1ffffC00 | SH_CACHE_VALID); | 110 | data = ctrl_inl(addr) & (0x1ffffC00 | SH_CACHE_VALID); |
@@ -114,7 +114,7 @@ static void __flush_dcache_page(unsigned long phys) | |||
114 | } | 114 | } |
115 | } | 115 | } |
116 | 116 | ||
117 | addrstart += cpu_data->dcache.way_incr; | 117 | addrstart += current_cpu_data.dcache.way_incr; |
118 | } while (--ways); | 118 | } while (--ways); |
119 | 119 | ||
120 | back_to_P1(); | 120 | back_to_P1(); |
diff --git a/arch/sh/mm/pg-sh4.c b/arch/sh/mm/pg-sh4.c index cfc323551741..b529d809dd4b 100644 --- a/arch/sh/mm/pg-sh4.c +++ b/arch/sh/mm/pg-sh4.c | |||
@@ -13,7 +13,7 @@ | |||
13 | 13 | ||
14 | extern struct mutex p3map_mutex[]; | 14 | extern struct mutex p3map_mutex[]; |
15 | 15 | ||
16 | #define CACHE_ALIAS (cpu_data->dcache.alias_mask) | 16 | #define CACHE_ALIAS (current_cpu_data.dcache.alias_mask) |
17 | 17 | ||
18 | /* | 18 | /* |
19 | * clear_user_page | 19 | * clear_user_page |
diff --git a/arch/sh/mm/pg-sh7705.c b/arch/sh/mm/pg-sh7705.c index b052d0fee827..887ab9d18ccd 100644 --- a/arch/sh/mm/pg-sh7705.c +++ b/arch/sh/mm/pg-sh7705.c | |||
@@ -43,13 +43,13 @@ static inline void __flush_purge_virtual_region(void *p1, void *virt, int size) | |||
43 | 43 | ||
44 | p = __pa(p1_begin); | 44 | p = __pa(p1_begin); |
45 | 45 | ||
46 | ways = cpu_data->dcache.ways; | 46 | ways = current_cpu_data.dcache.ways; |
47 | addr = CACHE_OC_ADDRESS_ARRAY; | 47 | addr = CACHE_OC_ADDRESS_ARRAY; |
48 | 48 | ||
49 | do { | 49 | do { |
50 | unsigned long data; | 50 | unsigned long data; |
51 | 51 | ||
52 | addr |= (v & cpu_data->dcache.entry_mask); | 52 | addr |= (v & current_cpu_data.dcache.entry_mask); |
53 | 53 | ||
54 | data = ctrl_inl(addr); | 54 | data = ctrl_inl(addr); |
55 | if ((data & CACHE_PHYSADDR_MASK) == | 55 | if ((data & CACHE_PHYSADDR_MASK) == |
@@ -58,7 +58,7 @@ static inline void __flush_purge_virtual_region(void *p1, void *virt, int size) | |||
58 | ctrl_outl(data, addr); | 58 | ctrl_outl(data, addr); |
59 | } | 59 | } |
60 | 60 | ||
61 | addr += cpu_data->dcache.way_incr; | 61 | addr += current_cpu_data.dcache.way_incr; |
62 | } while (--ways); | 62 | } while (--ways); |
63 | 63 | ||
64 | p1_begin += L1_CACHE_BYTES; | 64 | p1_begin += L1_CACHE_BYTES; |
diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c index 16627069c536..598c998dba5c 100644 --- a/arch/sh/mm/tlb-sh3.c +++ b/arch/sh/mm/tlb-sh3.c | |||
@@ -26,7 +26,7 @@ void __flush_tlb_page(unsigned long asid, unsigned long page) | |||
26 | addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000); | 26 | addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000); |
27 | data = (page & 0xfffe0000) | asid; /* VALID bit is off */ | 27 | data = (page & 0xfffe0000) | asid; /* VALID bit is off */ |
28 | 28 | ||
29 | if ((cpu_data->flags & CPU_HAS_MMU_PAGE_ASSOC)) { | 29 | if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) { |
30 | addr |= MMU_PAGE_ASSOC_BIT; | 30 | addr |= MMU_PAGE_ASSOC_BIT; |
31 | ways = 1; /* we already know the way .. */ | 31 | ways = 1; /* we already know the way .. */ |
32 | } | 32 | } |
diff --git a/arch/sh/oprofile/op_model_sh7750.c b/arch/sh/oprofile/op_model_sh7750.c index 0104e44bc76a..ebee7e24ede9 100644 --- a/arch/sh/oprofile/op_model_sh7750.c +++ b/arch/sh/oprofile/op_model_sh7750.c | |||
@@ -259,7 +259,7 @@ static struct oprofile_operations sh7750_perf_counter_ops = { | |||
259 | 259 | ||
260 | int __init oprofile_arch_init(struct oprofile_operations **ops) | 260 | int __init oprofile_arch_init(struct oprofile_operations **ops) |
261 | { | 261 | { |
262 | if (!(cpu_data->flags & CPU_HAS_PERF_COUNTER)) | 262 | if (!(current_cpu_data.flags & CPU_HAS_PERF_COUNTER)) |
263 | return -ENODEV; | 263 | return -ENODEV; |
264 | 264 | ||
265 | sh7750_perf_counter_ops.cpu_type = (char *)get_cpu_subtype(); | 265 | sh7750_perf_counter_ops.cpu_type = (char *)get_cpu_subtype(); |