aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorRussell King <rmk+kernel@arm.linux.org.uk>2010-10-19 15:12:24 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-10-19 15:12:24 -0400
commitf779b7dd3259ec138c7aba793f0602b20262af83 (patch)
tree7ed94961b196c81fcd413e2b04d1e6945d6d227a /arch
parent3c00079b31f910309b30ed5c2fd2b7a2d86bba60 (diff)
parentfe0cdec8bad919fd91cd344123906a55f3857209 (diff)
Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into devel-stable
Conflicts: arch/arm/mach-at91/include/mach/system.h arch/arm/mach-imx/mach-cpuimx27.c AT91 conflict resolution: Acked-by: Anders Larsen <al@alarsen.net> IMX conflict resolution confirmed by Uwe Kleine-König.
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig25
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/configs/s5p64x0_defconfig (renamed from arch/arm/configs/s5p6440_defconfig)3
-rw-r--r--arch/arm/kernel/kprobes-decode.c7
-rw-r--r--arch/arm/mach-at91/include/mach/system.h7
-rw-r--r--arch/arm/mach-ep93xx/dma-m2p.c2
-rw-r--r--arch/arm/mach-imx/Kconfig1
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c2
-rw-r--r--arch/arm/mach-s5p6440/Kconfig33
-rw-r--r--arch/arm/mach-s5p6440/Makefile25
-rw-r--r--arch/arm/mach-s5p6440/clock.c846
-rw-r--r--arch/arm/mach-s5p6440/cpu.c116
-rw-r--r--arch/arm/mach-s5p6440/dev-audio.c127
-rw-r--r--arch/arm/mach-s5p6440/dev-spi.c176
-rw-r--r--arch/arm/mach-s5p6440/include/mach/debug-macro.S37
-rw-r--r--arch/arm/mach-s5p6440/include/mach/gpio.h80
-rw-r--r--arch/arm/mach-s5p6440/include/mach/io.h18
-rw-r--r--arch/arm/mach-s5p6440/include/mach/map.h86
-rw-r--r--arch/arm/mach-s5p6440/include/mach/regs-clock.h130
-rw-r--r--arch/arm/mach-s5p6440/include/mach/spi-clocks.h17
-rw-r--r--arch/arm/mach-s5p6440/include/mach/uncompress.h24
-rw-r--r--arch/arm/mach-s5p6440/init.c52
-rw-r--r--arch/arm/mach-s5p6442/cpu.c28
-rw-r--r--arch/arm/mach-s5p6442/include/mach/map.h6
-rw-r--r--arch/arm/mach-s5p64x0/Kconfig57
-rw-r--r--arch/arm/mach-s5p64x0/Makefile30
-rw-r--r--arch/arm/mach-s5p64x0/Makefile.boot (renamed from arch/arm/mach-s5p6440/Makefile.boot)0
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c626
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c655
-rw-r--r--arch/arm/mach-s5p64x0/clock.c253
-rw-r--r--arch/arm/mach-s5p64x0/cpu.c209
-rw-r--r--arch/arm/mach-s5p64x0/dev-audio.c164
-rw-r--r--arch/arm/mach-s5p64x0/dev-spi.c232
-rw-r--r--arch/arm/mach-s5p64x0/dma.c (renamed from arch/arm/mach-s5p6440/dma.c)86
-rw-r--r--arch/arm/mach-s5p64x0/gpio.c (renamed from arch/arm/mach-s5p6440/gpio.c)104
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/debug-macro.S33
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/dma.h (renamed from arch/arm/mach-s5p6440/include/mach/dma.h)0
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/entry-macro.S (renamed from arch/arm/mach-s5p6440/include/mach/entry-macro.S)8
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/gpio.h139
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/hardware.h (renamed from arch/arm/mach-s5p6440/include/mach/hardware.h)8
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/i2c.h17
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/io.h25
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/irqs.h (renamed from arch/arm/mach-s5p6440/include/mach/irqs.h)48
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/map.h83
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/memory.h (renamed from arch/arm/mach-s5p6440/include/mach/memory.h)12
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/pwm-clock.h (renamed from arch/arm/mach-s5p6440/include/mach/pwm-clock.h)10
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-clock.h63
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-gpio.h (renamed from arch/arm/mach-s5p6440/include/mach/regs-gpio.h)28
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-irq.h (renamed from arch/arm/mach-s5p6440/include/mach/regs-irq.h)8
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h46
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/spi-clocks.h20
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/system.h (renamed from arch/arm/mach-s5p6440/include/mach/system.h)8
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/tick.h (renamed from arch/arm/mach-s5p6440/include/mach/tick.h)13
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/timex.h (renamed from arch/arm/mach-s5p6440/include/mach/timex.h)7
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/uncompress.h212
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/vmalloc.h (renamed from arch/arm/mach-s5p6440/include/mach/vmalloc.h)5
-rw-r--r--arch/arm/mach-s5p64x0/init.c73
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6440.c (renamed from arch/arm/mach-s5p6440/mach-smdk6440.c)87
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6450.c182
-rw-r--r--arch/arm/mach-s5p64x0/setup-i2c0.c (renamed from arch/arm/mach-s5p6440/setup-i2c0.c)24
-rw-r--r--arch/arm/mach-s5p64x0/setup-i2c1.c (renamed from arch/arm/mach-s5p6440/setup-i2c1.c)20
-rw-r--r--arch/arm/mach-s5pc100/cpu.c26
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h11
-rw-r--r--arch/arm/mach-s5pv210/Kconfig9
-rw-r--r--arch/arm/mach-s5pv210/Makefile1
-rw-r--r--arch/arm/mach-s5pv210/clock.c5
-rw-r--r--arch/arm/mach-s5pv210/cpu.c23
-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h11
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c2
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c2
-rw-r--r--arch/arm/mach-s5pv310/cpu.c26
-rw-r--r--arch/arm/mach-s5pv310/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s5pv310/include/mach/map.h7
-rw-r--r--arch/arm/mach-vexpress/ct-ca9x4.c4
-rw-r--r--arch/arm/mach-vexpress/v2m.c2
-rw-r--r--arch/arm/mm/ioremap.c8
-rw-r--r--arch/arm/mm/mmu.c4
-rw-r--r--arch/arm/mm/proc-v7.S10
-rw-r--r--arch/arm/plat-omap/iommu.c1
-rw-r--r--arch/arm/plat-s5p/Kconfig9
-rw-r--r--arch/arm/plat-s5p/Makefile1
-rw-r--r--arch/arm/plat-s5p/clock.c19
-rw-r--r--arch/arm/plat-s5p/cpu.c34
-rw-r--r--arch/arm/plat-s5p/dev-onenand.c (renamed from arch/arm/mach-s5pv210/dev-onenand.c)28
-rw-r--r--arch/arm/plat-s5p/dev-uart.c58
-rw-r--r--arch/arm/plat-s5p/include/plat/pll.h7
-rw-r--r--arch/arm/plat-s5p/include/plat/s5p-clock.h8
-rw-r--r--arch/arm/plat-s5p/include/plat/s5p6440.h7
-rw-r--r--arch/arm/plat-s5p/include/plat/s5p6450.h36
-rw-r--r--arch/arm/plat-samsung/adc.c1
-rw-r--r--arch/arm/plat-samsung/clock.c27
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h7
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h20
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h2
-rw-r--r--arch/mips/include/asm/siginfo.h1
-rw-r--r--arch/x86/ia32/ia32_aout.c22
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_amd.c9
-rw-r--r--arch/x86/kernel/cpu/mcheck/therm_throt.c3
-rw-r--r--arch/x86/kvm/svm.c2
-rw-r--r--arch/x86/mm/srat_64.c8
101 files changed, 3815 insertions, 2095 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7949fe65ecd4..b27f8abf163c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -680,8 +680,8 @@ config ARCH_S3C64XX
680 help 680 help
681 Samsung S3C64XX series based systems 681 Samsung S3C64XX series based systems
682 682
683config ARCH_S5P6440 683config ARCH_S5P64X0
684 bool "Samsung S5P6440" 684 bool "Samsung S5P6440 S5P6450"
685 select CPU_V6 685 select CPU_V6
686 select GENERIC_GPIO 686 select GENERIC_GPIO
687 select HAVE_CLK 687 select HAVE_CLK
@@ -690,7 +690,8 @@ config ARCH_S5P6440
690 select HAVE_S3C2410_I2C 690 select HAVE_S3C2410_I2C
691 select HAVE_S3C_RTC 691 select HAVE_S3C_RTC
692 help 692 help
693 Samsung S5P6440 CPU based systems 693 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
694 SMDK6450.
694 695
695config ARCH_S5P6442 696config ARCH_S5P6442
696 bool "Samsung S5P6442" 697 bool "Samsung S5P6442"
@@ -941,7 +942,7 @@ if ARCH_S3C64XX
941source "arch/arm/mach-s3c64xx/Kconfig" 942source "arch/arm/mach-s3c64xx/Kconfig"
942endif 943endif
943 944
944source "arch/arm/mach-s5p6440/Kconfig" 945source "arch/arm/mach-s5p64x0/Kconfig"
945 946
946source "arch/arm/mach-s5p6442/Kconfig" 947source "arch/arm/mach-s5p6442/Kconfig"
947 948
@@ -1114,6 +1115,20 @@ config ARM_ERRATA_720789
1114 invalidated are not, resulting in an incoherency in the system page 1115 invalidated are not, resulting in an incoherency in the system page
1115 tables. The workaround changes the TLB flushing routines to invalidate 1116 tables. The workaround changes the TLB flushing routines to invalidate
1116 entries regardless of the ASID. 1117 entries regardless of the ASID.
1118
1119config ARM_ERRATA_743622
1120 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1121 depends on CPU_V7
1122 help
1123 This option enables the workaround for the 743622 Cortex-A9
1124 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1125 optimisation in the Cortex-A9 Store Buffer may lead to data
1126 corruption. This workaround sets a specific bit in the diagnostic
1127 register of the Cortex-A9 which disables the Store Buffer
1128 optimisation, preventing the defect from occurring. This has no
1129 visible impact on the overall performance or power consumption of the
1130 processor.
1131
1117endmenu 1132endmenu
1118 1133
1119source "arch/arm/common/Kconfig" 1134source "arch/arm/common/Kconfig"
@@ -1270,7 +1285,7 @@ source kernel/Kconfig.preempt
1270 1285
1271config HZ 1286config HZ
1272 int 1287 int
1273 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || \ 1288 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1274 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310 1289 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1275 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1290 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1276 default AT91_TIMER_HZ if ARCH_AT91 1291 default AT91_TIMER_HZ if ARCH_AT91
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 502255905c4e..b87aed028eef 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -173,7 +173,7 @@ machine-$(CONFIG_ARCH_RPC) := rpc
173machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443 173machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
174machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 174machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
175machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx 175machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
176machine-$(CONFIG_ARCH_S5P6440) := s5p6440 176machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
177machine-$(CONFIG_ARCH_S5P6442) := s5p6442 177machine-$(CONFIG_ARCH_S5P6442) := s5p6442
178machine-$(CONFIG_ARCH_S5PC100) := s5pc100 178machine-$(CONFIG_ARCH_S5PC100) := s5pc100
179machine-$(CONFIG_ARCH_S5PV210) := s5pv210 179machine-$(CONFIG_ARCH_S5PV210) := s5pv210
diff --git a/arch/arm/configs/s5p6440_defconfig b/arch/arm/configs/s5p64x0_defconfig
index 0b0266c6d326..2993ecd35145 100644
--- a/arch/arm/configs/s5p6440_defconfig
+++ b/arch/arm/configs/s5p64x0_defconfig
@@ -5,10 +5,11 @@ CONFIG_KALLSYMS_ALL=y
5CONFIG_MODULES=y 5CONFIG_MODULES=y
6CONFIG_MODULE_UNLOAD=y 6CONFIG_MODULE_UNLOAD=y
7# CONFIG_BLK_DEV_BSG is not set 7# CONFIG_BLK_DEV_BSG is not set
8CONFIG_ARCH_S5P6440=y 8CONFIG_ARCH_S5P64X0=y
9CONFIG_S3C_BOOT_ERROR_RESET=y 9CONFIG_S3C_BOOT_ERROR_RESET=y
10CONFIG_S3C_LOWLEVEL_UART_PORT=1 10CONFIG_S3C_LOWLEVEL_UART_PORT=1
11CONFIG_MACH_SMDK6440=y 11CONFIG_MACH_SMDK6440=y
12CONFIG_MACH_SMDK6450=y
12CONFIG_CPU_32v6K=y 13CONFIG_CPU_32v6K=y
13CONFIG_AEABI=y 14CONFIG_AEABI=y
14CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" 15CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c
index 8bccbfa693ff..2c1f0050c9c4 100644
--- a/arch/arm/kernel/kprobes-decode.c
+++ b/arch/arm/kernel/kprobes-decode.c
@@ -1162,11 +1162,12 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1162{ 1162{
1163 /* 1163 /*
1164 * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx 1164 * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx
1165 * Undef : cccc 0011 0x00 xxxx xxxx xxxx xxxx xxxx 1165 * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx
1166 * ALU op with S bit and Rd == 15 : 1166 * ALU op with S bit and Rd == 15 :
1167 * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx 1167 * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx
1168 */ 1168 */
1169 if ((insn & 0x0f900000) == 0x03200000 || /* MSR & Undef */ 1169 if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */
1170 (insn & 0x0ff00000) == 0x03400000 || /* Undef */
1170 (insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */ 1171 (insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */
1171 return INSN_REJECTED; 1172 return INSN_REJECTED;
1172 1173
@@ -1177,7 +1178,7 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1177 * *S (bit 20) updates condition codes 1178 * *S (bit 20) updates condition codes
1178 * ADC/SBC/RSC reads the C flag 1179 * ADC/SBC/RSC reads the C flag
1179 */ 1180 */
1180 insn &= 0xfff00fff; /* Rn = r0, Rd = r0 */ 1181 insn &= 0xffff0fff; /* Rd = r0 */
1181 asi->insn[0] = insn; 1182 asi->insn[0] = insn;
1182 asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ 1183 asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
1183 emulate_alu_imm_rwflags : emulate_alu_imm_rflags; 1184 emulate_alu_imm_rwflags : emulate_alu_imm_rflags;
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
index bfbb612265d6..36af14bc13bb 100644
--- a/arch/arm/mach-at91/include/mach/system.h
+++ b/arch/arm/mach-at91/include/mach/system.h
@@ -28,7 +28,6 @@
28 28
29static inline void arch_idle(void) 29static inline void arch_idle(void)
30{ 30{
31#ifndef CONFIG_DEBUG_KERNEL
32 /* 31 /*
33 * Disable the processor clock. The processor will be automatically 32 * Disable the processor clock. The processor will be automatically
34 * re-enabled by an interrupt or by a reset. 33 * re-enabled by an interrupt or by a reset.
@@ -38,11 +37,11 @@ static inline void arch_idle(void)
38#else 37#else
39 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); 38 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
40#endif 39#endif
41#else 40#ifndef CONFIG_CPU_ARM920T
42 /* 41 /*
43 * Set the processor (CP15) into 'Wait for Interrupt' mode. 42 * Set the processor (CP15) into 'Wait for Interrupt' mode.
44 * Unlike disabling the processor clock via the PMC (above) 43 * Post-RM9200 processors need this in conjunction with the above
45 * this allows the processor to be woken via JTAG. 44 * to save power when idle.
46 */ 45 */
47 cpu_do_idle(); 46 cpu_do_idle();
48#endif 47#endif
diff --git a/arch/arm/mach-ep93xx/dma-m2p.c b/arch/arm/mach-ep93xx/dma-m2p.c
index 8904ca4e2e24..a696d354b1f8 100644
--- a/arch/arm/mach-ep93xx/dma-m2p.c
+++ b/arch/arm/mach-ep93xx/dma-m2p.c
@@ -276,7 +276,7 @@ static void channel_disable(struct m2p_channel *ch)
276 v &= ~(M2P_CONTROL_STALL_IRQ_EN | M2P_CONTROL_NFB_IRQ_EN); 276 v &= ~(M2P_CONTROL_STALL_IRQ_EN | M2P_CONTROL_NFB_IRQ_EN);
277 m2p_set_control(ch, v); 277 m2p_set_control(ch, v);
278 278
279 while (m2p_channel_state(ch) == STATE_ON) 279 while (m2p_channel_state(ch) >= STATE_ON)
280 cpu_relax(); 280 cpu_relax();
281 281
282 m2p_set_control(ch, 0x0); 282 m2p_set_control(ch, 0x0);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 9b45f1f523fa..197f9e241cff 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -122,6 +122,7 @@ config MACH_CPUIMX27
122 select IMX_HAVE_PLATFORM_IMX_I2C 122 select IMX_HAVE_PLATFORM_IMX_I2C
123 select IMX_HAVE_PLATFORM_IMX_UART 123 select IMX_HAVE_PLATFORM_IMX_UART
124 select IMX_HAVE_PLATFORM_MXC_NAND 124 select IMX_HAVE_PLATFORM_MXC_NAND
125 select MXC_ULPI if USB_ULPI
125 help 126 help
126 Include support for Eukrea CPUIMX27 platform. This includes 127 Include support for Eukrea CPUIMX27 platform. This includes
127 specific configurations for the module and its peripherals. 128 specific configurations for the module and its peripherals.
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 28f73a1c79f7..a1681fc9d9b0 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -258,7 +258,7 @@ static void __init eukrea_cpuimx27_init(void)
258 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, 258 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
259 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); 259 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
260 260
261 imx27_add_imx_i2c(1, &cpuimx27_i2c1_data); 261 imx27_add_imx_i2c(0, &cpuimx27_i2c1_data);
262 262
263 imx27_add_fec(NULL); 263 imx27_add_fec(NULL);
264 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 264 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig
deleted file mode 100644
index 6a4af7f57584..000000000000
--- a/arch/arm/mach-s5p6440/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
1# arch/arm/mach-s5p6440/Kconfig
2#
3# Copyright (c) 2009 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8if ARCH_S5P6440
9
10config CPU_S5P6440
11 bool
12 select S3C_PL330_DMA
13 help
14 Enable S5P6440 CPU support
15
16config S5P6440_SETUP_I2C1
17 bool
18 help
19 Common setup code for i2c bus 1.
20
21config MACH_SMDK6440
22 bool "SMDK6440"
23 select CPU_S5P6440
24 select S3C_DEV_I2C1
25 select S3C_DEV_RTC
26 select S3C_DEV_WDT
27 select SAMSUNG_DEV_ADC
28 select SAMSUNG_DEV_TS
29 select S5P6440_SETUP_I2C1
30 help
31 Machine support for the Samsung SMDK6440
32
33endif
diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile
deleted file mode 100644
index c3fe4d3662a9..000000000000
--- a/arch/arm/mach-s5p6440/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
1# arch/arm/mach-s5p6440/Makefile
2#
3# Copyright (c) 2009 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for S5P6440 system
14
15obj-$(CONFIG_CPU_S5P6440) += cpu.o init.o clock.o gpio.o dma.o
16obj-$(CONFIG_CPU_S5P6440) += setup-i2c0.o
17
18# machine support
19
20obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o
21
22# device support
23obj-y += dev-audio.o
24obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
25obj-$(CONFIG_S5P6440_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c
deleted file mode 100644
index ca6e48dce777..000000000000
--- a/arch/arm/mach-s5p6440/clock.c
+++ /dev/null
@@ -1,846 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/clock.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/sysdev.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25
26#include <plat/cpu-freq.h>
27#include <mach/regs-clock.h>
28#include <plat/clock.h>
29#include <plat/cpu.h>
30#include <plat/clock-clksrc.h>
31#include <plat/s5p-clock.h>
32#include <plat/pll.h>
33#include <plat/s5p6440.h>
34
35/* APLL Mux output clock */
36static struct clksrc_clk clk_mout_apll = {
37 .clk = {
38 .name = "mout_apll",
39 .id = -1,
40 },
41 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
43};
44
45static int s5p6440_epll_enable(struct clk *clk, int enable)
46{
47 unsigned int ctrlbit = clk->ctrlbit;
48 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
49
50 if (enable)
51 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
52 else
53 __raw_writel(epll_con, S5P_EPLL_CON);
54
55 return 0;
56}
57
58static unsigned long s5p6440_epll_get_rate(struct clk *clk)
59{
60 return clk->rate;
61}
62
63static u32 epll_div[][5] = {
64 { 36000000, 0, 48, 1, 4 },
65 { 48000000, 0, 32, 1, 3 },
66 { 60000000, 0, 40, 1, 3 },
67 { 72000000, 0, 48, 1, 3 },
68 { 84000000, 0, 28, 1, 2 },
69 { 96000000, 0, 32, 1, 2 },
70 { 32768000, 45264, 43, 1, 4 },
71 { 45158000, 6903, 30, 1, 3 },
72 { 49152000, 50332, 32, 1, 3 },
73 { 67738000, 10398, 45, 1, 3 },
74 { 73728000, 9961, 49, 1, 3 }
75};
76
77static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
78{
79 unsigned int epll_con, epll_con_k;
80 unsigned int i;
81
82 if (clk->rate == rate) /* Return if nothing changed */
83 return 0;
84
85 epll_con = __raw_readl(S5P_EPLL_CON);
86 epll_con_k = __raw_readl(S5P_EPLL_CON_K);
87
88 epll_con_k &= ~(PLL90XX_KDIV_MASK);
89 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
90
91 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
92 if (epll_div[i][0] == rate) {
93 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
94 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
95 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
96 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
97 break;
98 }
99 }
100
101 if (i == ARRAY_SIZE(epll_div)) {
102 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
103 return -EINVAL;
104 }
105
106 __raw_writel(epll_con, S5P_EPLL_CON);
107 __raw_writel(epll_con_k, S5P_EPLL_CON_K);
108
109 clk->rate = rate;
110
111 return 0;
112}
113
114static struct clk_ops s5p6440_epll_ops = {
115 .get_rate = s5p6440_epll_get_rate,
116 .set_rate = s5p6440_epll_set_rate,
117};
118
119static struct clksrc_clk clk_mout_epll = {
120 .clk = {
121 .name = "mout_epll",
122 .id = -1,
123 },
124 .sources = &clk_src_epll,
125 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 2, .size = 1 },
126};
127
128static struct clksrc_clk clk_mout_mpll = {
129 .clk = {
130 .name = "mout_mpll",
131 .id = -1,
132 },
133 .sources = &clk_src_mpll,
134 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
135};
136
137enum perf_level {
138 L0 = 532*1000,
139 L1 = 266*1000,
140 L2 = 133*1000,
141};
142
143static const u32 clock_table[][3] = {
144 /*{ARM_CLK, DIVarm, DIVhclk}*/
145 {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P_CLKDIV0_HCLK_SHIFT)},
146 {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P_CLKDIV0_HCLK_SHIFT)},
147 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P_CLKDIV0_HCLK_SHIFT)},
148};
149
150static unsigned long s5p6440_armclk_get_rate(struct clk *clk)
151{
152 unsigned long rate = clk_get_rate(clk->parent);
153 u32 clkdiv;
154
155 /* divisor mask starts at bit0, so no need to shift */
156 clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
157
158 return rate / (clkdiv + 1);
159}
160
161static unsigned long s5p6440_armclk_round_rate(struct clk *clk,
162 unsigned long rate)
163{
164 u32 iter;
165
166 for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
167 if (rate > clock_table[iter][0])
168 return clock_table[iter-1][0];
169 }
170
171 return clock_table[ARRAY_SIZE(clock_table) - 1][0];
172}
173
174static int s5p6440_armclk_set_rate(struct clk *clk, unsigned long rate)
175{
176 u32 round_tmp;
177 u32 iter;
178 u32 clk_div0_tmp;
179 u32 cur_rate = clk->ops->get_rate(clk);
180 unsigned long flags;
181
182 round_tmp = clk->ops->round_rate(clk, rate);
183 if (round_tmp == cur_rate)
184 return 0;
185
186
187 for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
188 if (round_tmp == clock_table[iter][0])
189 break;
190 }
191
192 if (iter >= ARRAY_SIZE(clock_table))
193 iter = ARRAY_SIZE(clock_table) - 1;
194
195 local_irq_save(flags);
196 if (cur_rate > round_tmp) {
197 /* Frequency Down */
198 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
199 clk_div0_tmp |= clock_table[iter][1];
200 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
201
202 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
203 ~(S5P_CLKDIV0_HCLK_MASK);
204 clk_div0_tmp |= clock_table[iter][2];
205 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
206
207
208 } else {
209 /* Frequency Up */
210 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
211 ~(S5P_CLKDIV0_HCLK_MASK);
212 clk_div0_tmp |= clock_table[iter][2];
213 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
214
215 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
216 clk_div0_tmp |= clock_table[iter][1];
217 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
218 }
219 local_irq_restore(flags);
220
221 clk->rate = clock_table[iter][0];
222
223 return 0;
224}
225
226static struct clk_ops s5p6440_clkarm_ops = {
227 .get_rate = s5p6440_armclk_get_rate,
228 .set_rate = s5p6440_armclk_set_rate,
229 .round_rate = s5p6440_armclk_round_rate,
230};
231
232static struct clksrc_clk clk_armclk = {
233 .clk = {
234 .name = "armclk",
235 .id = 1,
236 .parent = &clk_mout_apll.clk,
237 .ops = &s5p6440_clkarm_ops,
238 },
239 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
240};
241
242static struct clksrc_clk clk_dout_mpll = {
243 .clk = {
244 .name = "dout_mpll",
245 .id = -1,
246 .parent = &clk_mout_mpll.clk,
247 },
248 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
249};
250
251static struct clksrc_clk clk_hclk = {
252 .clk = {
253 .name = "clk_hclk",
254 .id = -1,
255 .parent = &clk_armclk.clk,
256 },
257 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
258};
259
260static struct clksrc_clk clk_pclk = {
261 .clk = {
262 .name = "clk_pclk",
263 .id = -1,
264 .parent = &clk_hclk.clk,
265 },
266 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
267};
268
269static struct clk *clkset_hclklow_list[] = {
270 &clk_mout_apll.clk,
271 &clk_mout_mpll.clk,
272};
273
274static struct clksrc_sources clkset_hclklow = {
275 .sources = clkset_hclklow_list,
276 .nr_sources = ARRAY_SIZE(clkset_hclklow_list),
277};
278
279static struct clksrc_clk clk_hclk_low = {
280 .clk = {
281 .name = "hclk_low",
282 .id = -1,
283 },
284 .sources = &clkset_hclklow,
285 .reg_src = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
286 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
287};
288
289static struct clksrc_clk clk_pclk_low = {
290 .clk = {
291 .name = "pclk_low",
292 .id = -1,
293 .parent = &clk_hclk_low.clk,
294 },
295 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
296};
297
298int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
299{
300 unsigned long flags;
301 u32 val;
302
303 /* can't rely on clock lock, this register has other usages */
304 local_irq_save(flags);
305
306 val = __raw_readl(S5P_OTHERS);
307 if (enable)
308 val |= S5P_OTHERS_USB_SIG_MASK;
309 else
310 val &= ~S5P_OTHERS_USB_SIG_MASK;
311
312 __raw_writel(val, S5P_OTHERS);
313
314 local_irq_restore(flags);
315
316 return 0;
317}
318
319static int s5p6440_pclk_ctrl(struct clk *clk, int enable)
320{
321 return s5p_gatectrl(S5P_CLK_GATE_PCLK, clk, enable);
322}
323
324static int s5p6440_hclk0_ctrl(struct clk *clk, int enable)
325{
326 return s5p_gatectrl(S5P_CLK_GATE_HCLK0, clk, enable);
327}
328
329static int s5p6440_hclk1_ctrl(struct clk *clk, int enable)
330{
331 return s5p_gatectrl(S5P_CLK_GATE_HCLK1, clk, enable);
332}
333
334static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
335{
336 return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
337}
338
339static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
340{
341 return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
342}
343
344static int s5p6440_mem_ctrl(struct clk *clk, int enable)
345{
346 return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
347}
348
349/*
350 * The following clocks will be disabled during clock initialization. It is
351 * recommended to keep the following clocks disabled until the driver requests
352 * for enabling the clock.
353 */
354static struct clk init_clocks_disable[] = {
355 {
356 .name = "nand",
357 .id = -1,
358 .parent = &clk_hclk.clk,
359 .enable = s5p6440_mem_ctrl,
360 .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON,
361 }, {
362 .name = "adc",
363 .id = -1,
364 .parent = &clk_pclk_low.clk,
365 .enable = s5p6440_pclk_ctrl,
366 .ctrlbit = S5P_CLKCON_PCLK_TSADC,
367 }, {
368 .name = "i2c",
369 .id = -1,
370 .parent = &clk_pclk_low.clk,
371 .enable = s5p6440_pclk_ctrl,
372 .ctrlbit = S5P_CLKCON_PCLK_IIC0,
373 }, {
374 .name = "i2s_v40",
375 .id = 0,
376 .parent = &clk_pclk_low.clk,
377 .enable = s5p6440_pclk_ctrl,
378 .ctrlbit = S5P_CLKCON_PCLK_IIS2,
379 }, {
380 .name = "spi",
381 .id = 0,
382 .parent = &clk_pclk_low.clk,
383 .enable = s5p6440_pclk_ctrl,
384 .ctrlbit = S5P_CLKCON_PCLK_SPI0,
385 }, {
386 .name = "spi",
387 .id = 1,
388 .parent = &clk_pclk_low.clk,
389 .enable = s5p6440_pclk_ctrl,
390 .ctrlbit = S5P_CLKCON_PCLK_SPI1,
391 }, {
392 .name = "sclk_spi_48",
393 .id = 0,
394 .parent = &clk_48m,
395 .enable = s5p6440_sclk_ctrl,
396 .ctrlbit = S5P_CLKCON_SCLK0_SPI0_48,
397 }, {
398 .name = "sclk_spi_48",
399 .id = 1,
400 .parent = &clk_48m,
401 .enable = s5p6440_sclk_ctrl,
402 .ctrlbit = S5P_CLKCON_SCLK0_SPI1_48,
403 }, {
404 .name = "mmc_48m",
405 .id = 0,
406 .parent = &clk_48m,
407 .enable = s5p6440_sclk_ctrl,
408 .ctrlbit = S5P_CLKCON_SCLK0_MMC0_48,
409 }, {
410 .name = "mmc_48m",
411 .id = 1,
412 .parent = &clk_48m,
413 .enable = s5p6440_sclk_ctrl,
414 .ctrlbit = S5P_CLKCON_SCLK0_MMC1_48,
415 }, {
416 .name = "mmc_48m",
417 .id = 2,
418 .parent = &clk_48m,
419 .enable = s5p6440_sclk_ctrl,
420 .ctrlbit = S5P_CLKCON_SCLK0_MMC2_48,
421 }, {
422 .name = "otg",
423 .id = -1,
424 .parent = &clk_hclk_low.clk,
425 .enable = s5p6440_hclk0_ctrl,
426 .ctrlbit = S5P_CLKCON_HCLK0_USB
427 }, {
428 .name = "post",
429 .id = -1,
430 .parent = &clk_hclk_low.clk,
431 .enable = s5p6440_hclk0_ctrl,
432 .ctrlbit = S5P_CLKCON_HCLK0_POST0
433 }, {
434 .name = "lcd",
435 .id = -1,
436 .parent = &clk_hclk_low.clk,
437 .enable = s5p6440_hclk1_ctrl,
438 .ctrlbit = S5P_CLKCON_HCLK1_DISPCON,
439 }, {
440 .name = "hsmmc",
441 .id = 0,
442 .parent = &clk_hclk_low.clk,
443 .enable = s5p6440_hclk0_ctrl,
444 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0,
445 }, {
446 .name = "hsmmc",
447 .id = 1,
448 .parent = &clk_hclk_low.clk,
449 .enable = s5p6440_hclk0_ctrl,
450 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1,
451 }, {
452 .name = "hsmmc",
453 .id = 2,
454 .parent = &clk_hclk_low.clk,
455 .enable = s5p6440_hclk0_ctrl,
456 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2,
457 }, {
458 .name = "rtc",
459 .id = -1,
460 .parent = &clk_pclk_low.clk,
461 .enable = s5p6440_pclk_ctrl,
462 .ctrlbit = S5P_CLKCON_PCLK_RTC,
463 }, {
464 .name = "watchdog",
465 .id = -1,
466 .parent = &clk_pclk_low.clk,
467 .enable = s5p6440_pclk_ctrl,
468 .ctrlbit = S5P_CLKCON_PCLK_WDT,
469 }, {
470 .name = "timers",
471 .id = -1,
472 .parent = &clk_pclk_low.clk,
473 .enable = s5p6440_pclk_ctrl,
474 .ctrlbit = S5P_CLKCON_PCLK_PWM,
475 }, {
476 .name = "hclk_fimgvg",
477 .id = -1,
478 .parent = &clk_hclk.clk,
479 .enable = s5p6440_hclk1_ctrl,
480 .ctrlbit = (1 << 2),
481 }, {
482 .name = "tsi",
483 .id = -1,
484 .parent = &clk_hclk_low.clk,
485 .enable = s5p6440_hclk1_ctrl,
486 .ctrlbit = (1 << 0),
487 }, {
488 .name = "pclk_fimgvg",
489 .id = -1,
490 .parent = &clk_pclk.clk,
491 .enable = s5p6440_pclk_ctrl,
492 .ctrlbit = (1 << 31),
493 }, {
494 .name = "dmc0",
495 .id = -1,
496 .parent = &clk_pclk.clk,
497 .enable = s5p6440_pclk_ctrl,
498 .ctrlbit = (1 << 30),
499 }, {
500 .name = "etm",
501 .id = -1,
502 .parent = &clk_pclk.clk,
503 .enable = s5p6440_pclk_ctrl,
504 .ctrlbit = (1 << 29),
505 }, {
506 .name = "dsim",
507 .id = -1,
508 .parent = &clk_pclk_low.clk,
509 .enable = s5p6440_pclk_ctrl,
510 .ctrlbit = (1 << 28),
511 }, {
512 .name = "gps",
513 .id = -1,
514 .parent = &clk_pclk_low.clk,
515 .enable = s5p6440_pclk_ctrl,
516 .ctrlbit = (1 << 25),
517 }, {
518 .name = "pcm",
519 .id = -1,
520 .parent = &clk_pclk_low.clk,
521 .enable = s5p6440_pclk_ctrl,
522 .ctrlbit = (1 << 8),
523 }, {
524 .name = "irom",
525 .id = -1,
526 .parent = &clk_hclk.clk,
527 .enable = s5p6440_hclk0_ctrl,
528 .ctrlbit = (1 << 25),
529 }, {
530 .name = "dma",
531 .id = -1,
532 .parent = &clk_hclk_low.clk,
533 .enable = s5p6440_hclk0_ctrl,
534 .ctrlbit = (1 << 12),
535 }, {
536 .name = "2d",
537 .id = -1,
538 .parent = &clk_hclk.clk,
539 .enable = s5p6440_hclk0_ctrl,
540 .ctrlbit = (1 << 8),
541 },
542};
543
544/*
545 * The following clocks will be enabled during clock initialization.
546 */
547static struct clk init_clocks[] = {
548 {
549 .name = "gpio",
550 .id = -1,
551 .parent = &clk_pclk_low.clk,
552 .enable = s5p6440_pclk_ctrl,
553 .ctrlbit = S5P_CLKCON_PCLK_GPIO,
554 }, {
555 .name = "uart",
556 .id = 0,
557 .parent = &clk_pclk_low.clk,
558 .enable = s5p6440_pclk_ctrl,
559 .ctrlbit = S5P_CLKCON_PCLK_UART0,
560 }, {
561 .name = "uart",
562 .id = 1,
563 .parent = &clk_pclk_low.clk,
564 .enable = s5p6440_pclk_ctrl,
565 .ctrlbit = S5P_CLKCON_PCLK_UART1,
566 }, {
567 .name = "uart",
568 .id = 2,
569 .parent = &clk_pclk_low.clk,
570 .enable = s5p6440_pclk_ctrl,
571 .ctrlbit = S5P_CLKCON_PCLK_UART2,
572 }, {
573 .name = "uart",
574 .id = 3,
575 .parent = &clk_pclk_low.clk,
576 .enable = s5p6440_pclk_ctrl,
577 .ctrlbit = S5P_CLKCON_PCLK_UART3,
578 }, {
579 .name = "mem",
580 .id = -1,
581 .parent = &clk_hclk.clk,
582 .enable = s5p6440_hclk0_ctrl,
583 .ctrlbit = (1 << 21),
584 }, {
585 .name = "intc",
586 .id = -1,
587 .parent = &clk_hclk.clk,
588 .enable = s5p6440_hclk0_ctrl,
589 .ctrlbit = (1 << 1),
590 },
591};
592
593static struct clk clk_iis_cd_v40 = {
594 .name = "iis_cdclk_v40",
595 .id = -1,
596};
597
598static struct clk clk_pcm_cd = {
599 .name = "pcm_cdclk",
600 .id = -1,
601};
602
603static struct clk *clkset_group1_list[] = {
604 &clk_mout_epll.clk,
605 &clk_dout_mpll.clk,
606 &clk_fin_epll,
607};
608
609static struct clksrc_sources clkset_group1 = {
610 .sources = clkset_group1_list,
611 .nr_sources = ARRAY_SIZE(clkset_group1_list),
612};
613
614static struct clk *clkset_uart_list[] = {
615 &clk_mout_epll.clk,
616 &clk_dout_mpll.clk,
617};
618
619static struct clksrc_sources clkset_uart = {
620 .sources = clkset_uart_list,
621 .nr_sources = ARRAY_SIZE(clkset_uart_list),
622};
623
624static struct clk *clkset_audio_list[] = {
625 &clk_mout_epll.clk,
626 &clk_dout_mpll.clk,
627 &clk_fin_epll,
628 &clk_iis_cd_v40,
629 &clk_pcm_cd,
630};
631
632static struct clksrc_sources clkset_audio = {
633 .sources = clkset_audio_list,
634 .nr_sources = ARRAY_SIZE(clkset_audio_list),
635};
636
637static struct clksrc_clk clksrcs[] = {
638 {
639 .clk = {
640 .name = "mmc_bus",
641 .id = 0,
642 .ctrlbit = S5P_CLKCON_SCLK0_MMC0,
643 .enable = s5p6440_sclk_ctrl,
644 },
645 .sources = &clkset_group1,
646 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
647 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
648 }, {
649 .clk = {
650 .name = "mmc_bus",
651 .id = 1,
652 .ctrlbit = S5P_CLKCON_SCLK0_MMC1,
653 .enable = s5p6440_sclk_ctrl,
654 },
655 .sources = &clkset_group1,
656 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
657 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
658 }, {
659 .clk = {
660 .name = "mmc_bus",
661 .id = 2,
662 .ctrlbit = S5P_CLKCON_SCLK0_MMC2,
663 .enable = s5p6440_sclk_ctrl,
664 },
665 .sources = &clkset_group1,
666 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
667 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
668 }, {
669 .clk = {
670 .name = "uclk1",
671 .id = -1,
672 .ctrlbit = S5P_CLKCON_SCLK0_UART,
673 .enable = s5p6440_sclk_ctrl,
674 },
675 .sources = &clkset_uart,
676 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 13, .size = 1 },
677 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
678 }, {
679 .clk = {
680 .name = "spi_epll",
681 .id = 0,
682 .ctrlbit = S5P_CLKCON_SCLK0_SPI0,
683 .enable = s5p6440_sclk_ctrl,
684 },
685 .sources = &clkset_group1,
686 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
687 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
688 }, {
689 .clk = {
690 .name = "spi_epll",
691 .id = 1,
692 .ctrlbit = S5P_CLKCON_SCLK0_SPI1,
693 .enable = s5p6440_sclk_ctrl,
694 },
695 .sources = &clkset_group1,
696 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
697 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
698 }, {
699 .clk = {
700 .name = "sclk_post",
701 .id = -1,
702 .ctrlbit = (1 << 10),
703 .enable = s5p6440_sclk_ctrl,
704 },
705 .sources = &clkset_group1,
706 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
707 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
708 }, {
709 .clk = {
710 .name = "sclk_dispcon",
711 .id = -1,
712 .ctrlbit = (1 << 1),
713 .enable = s5p6440_sclk1_ctrl,
714 },
715 .sources = &clkset_group1,
716 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
717 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
718 }, {
719 .clk = {
720 .name = "sclk_fimgvg",
721 .id = -1,
722 .ctrlbit = (1 << 2),
723 .enable = s5p6440_sclk1_ctrl,
724 },
725 .sources = &clkset_group1,
726 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
727 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
728 }, {
729 .clk = {
730 .name = "sclk_audio2",
731 .id = -1,
732 .ctrlbit = (1 << 11),
733 .enable = s5p6440_sclk_ctrl,
734 },
735 .sources = &clkset_audio,
736 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
737 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
738 },
739};
740
741/* Clock initialisation code */
742static struct clksrc_clk *sysclks[] = {
743 &clk_mout_apll,
744 &clk_mout_epll,
745 &clk_mout_mpll,
746 &clk_dout_mpll,
747 &clk_armclk,
748 &clk_hclk,
749 &clk_pclk,
750 &clk_hclk_low,
751 &clk_pclk_low,
752};
753
754void __init_or_cpufreq s5p6440_setup_clocks(void)
755{
756 struct clk *xtal_clk;
757 unsigned long xtal;
758 unsigned long fclk;
759 unsigned long hclk;
760 unsigned long hclk_low;
761 unsigned long pclk;
762 unsigned long pclk_low;
763 unsigned long epll;
764 unsigned long apll;
765 unsigned long mpll;
766 unsigned int ptr;
767
768 /* Set S5P6440 functions for clk_fout_epll */
769 clk_fout_epll.enable = s5p6440_epll_enable;
770 clk_fout_epll.ops = &s5p6440_epll_ops;
771
772 clk_48m.enable = s5p6440_clk48m_ctrl;
773
774 xtal_clk = clk_get(NULL, "ext_xtal");
775 BUG_ON(IS_ERR(xtal_clk));
776
777 xtal = clk_get_rate(xtal_clk);
778 clk_put(xtal_clk);
779
780 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON),
781 __raw_readl(S5P_EPLL_CON_K));
782 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
783 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
784
785 clk_fout_mpll.rate = mpll;
786 clk_fout_epll.rate = epll;
787 clk_fout_apll.rate = apll;
788
789 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
790 " E=%ld.%ldMHz\n",
791 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
792
793 fclk = clk_get_rate(&clk_armclk.clk);
794 hclk = clk_get_rate(&clk_hclk.clk);
795 pclk = clk_get_rate(&clk_pclk.clk);
796 hclk_low = clk_get_rate(&clk_hclk_low.clk);
797 pclk_low = clk_get_rate(&clk_pclk_low.clk);
798
799 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
800 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
801 print_mhz(hclk), print_mhz(hclk_low),
802 print_mhz(pclk), print_mhz(pclk_low));
803
804 clk_f.rate = fclk;
805 clk_h.rate = hclk;
806 clk_p.rate = pclk;
807
808 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
809 s3c_set_clksrc(&clksrcs[ptr], true);
810}
811
812static struct clk *clks[] __initdata = {
813 &clk_ext,
814 &clk_iis_cd_v40,
815 &clk_pcm_cd,
816};
817
818void __init s5p6440_register_clocks(void)
819{
820 struct clk *clkp;
821 int ret;
822 int ptr;
823
824 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
825 if (ret > 0)
826 printk(KERN_ERR "Failed to register %u clocks\n", ret);
827
828 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
829 s3c_register_clksrc(sysclks[ptr], 1);
830
831 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
832 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
833
834 clkp = init_clocks_disable;
835 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
836
837 ret = s3c24xx_register_clock(clkp);
838 if (ret < 0) {
839 printk(KERN_ERR "Failed to register clock %s (%d)\n",
840 clkp->name, ret);
841 }
842 (clkp->enable)(clkp, 0);
843 }
844
845 s3c_pwmclk_init();
846}
diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c
deleted file mode 100644
index 526f33adb31d..000000000000
--- a/arch/arm/mach-s5p6440/cpu.c
+++ /dev/null
@@ -1,116 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/cpu.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/sysdev.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26
27#include <asm/proc-fns.h>
28
29#include <mach/hardware.h>
30#include <mach/map.h>
31#include <asm/irq.h>
32
33#include <plat/regs-serial.h>
34#include <mach/regs-clock.h>
35
36#include <plat/cpu.h>
37#include <plat/devs.h>
38#include <plat/clock.h>
39#include <plat/s5p6440.h>
40#include <plat/adc-core.h>
41
42static void s5p6440_idle(void)
43{
44 unsigned long val;
45
46 if (!need_resched()) {
47 val = __raw_readl(S5P_PWR_CFG);
48 val &= ~(0x3<<5);
49 val |= (0x1<<5);
50 __raw_writel(val, S5P_PWR_CFG);
51
52 cpu_do_idle();
53 }
54 local_irq_enable();
55}
56
57/* s5p6440_map_io
58 *
59 * register the standard cpu IO areas
60*/
61
62void __init s5p6440_map_io(void)
63{
64 /* initialize any device information early */
65 s3c_adc_setname("s3c64xx-adc");
66}
67
68void __init s5p6440_init_clocks(int xtal)
69{
70 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
71
72 s3c24xx_register_baseclocks(xtal);
73 s5p_register_clocks(xtal);
74 s5p6440_register_clocks();
75 s5p6440_setup_clocks();
76}
77
78void __init s5p6440_init_irq(void)
79{
80 /* S5P6440 supports only 2 VIC */
81 u32 vic[2];
82
83 /*
84 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
85 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
86 */
87 vic[0] = 0xff800ae7;
88 vic[1] = 0xffbf23e5;
89
90 s5p_init_irq(vic, ARRAY_SIZE(vic));
91}
92
93struct sysdev_class s5p6440_sysclass = {
94 .name = "s5p6440-core",
95};
96
97static struct sys_device s5p6440_sysdev = {
98 .cls = &s5p6440_sysclass,
99};
100
101static int __init s5p6440_core_init(void)
102{
103 return sysdev_class_register(&s5p6440_sysclass);
104}
105
106core_initcall(s5p6440_core_init);
107
108int __init s5p6440_init(void)
109{
110 printk(KERN_INFO "S5P6440: Initializing architecture\n");
111
112 /* set idle function */
113 pm_idle = s5p6440_idle;
114
115 return sysdev_register(&s5p6440_sysdev);
116}
diff --git a/arch/arm/mach-s5p6440/dev-audio.c b/arch/arm/mach-s5p6440/dev-audio.c
deleted file mode 100644
index 3ca0d2b8275d..000000000000
--- a/arch/arm/mach-s5p6440/dev-audio.c
+++ /dev/null
@@ -1,127 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/audio.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static int s5p6440_cfg_i2s(struct platform_device *pdev)
23{
24 /* configure GPIO for i2s port */
25 switch (pdev->id) {
26 case -1:
27 s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
28 s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
29 s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
30 s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
31 s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
32 s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
33 s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
34 break;
35
36 default:
37 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
38 return -EINVAL;
39 }
40
41 return 0;
42}
43
44static struct s3c_audio_pdata s3c_i2s_pdata = {
45 .cfg_gpio = s5p6440_cfg_i2s,
46};
47
48static struct resource s5p6440_iis0_resource[] = {
49 [0] = {
50 .start = S5P6440_PA_I2S,
51 .end = S5P6440_PA_I2S + 0x100 - 1,
52 .flags = IORESOURCE_MEM,
53 },
54 [1] = {
55 .start = DMACH_I2S0_TX,
56 .end = DMACH_I2S0_TX,
57 .flags = IORESOURCE_DMA,
58 },
59 [2] = {
60 .start = DMACH_I2S0_RX,
61 .end = DMACH_I2S0_RX,
62 .flags = IORESOURCE_DMA,
63 },
64};
65
66struct platform_device s5p6440_device_iis = {
67 .name = "s3c64xx-iis-v4",
68 .id = -1,
69 .num_resources = ARRAY_SIZE(s5p6440_iis0_resource),
70 .resource = s5p6440_iis0_resource,
71 .dev = {
72 .platform_data = &s3c_i2s_pdata,
73 },
74};
75
76/* PCM Controller platform_devices */
77
78static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
79{
80 switch (pdev->id) {
81 case 0:
82 s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
83 s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
84 s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
85 s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
86 s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
87 break;
88
89 default:
90 printk(KERN_DEBUG "Invalid PCM Controller number!");
91 return -EINVAL;
92 }
93
94 return 0;
95}
96
97static struct s3c_audio_pdata s3c_pcm_pdata = {
98 .cfg_gpio = s5p6440_pcm_cfg_gpio,
99};
100
101static struct resource s5p6440_pcm0_resource[] = {
102 [0] = {
103 .start = S5P6440_PA_PCM,
104 .end = S5P6440_PA_PCM + 0x100 - 1,
105 .flags = IORESOURCE_MEM,
106 },
107 [1] = {
108 .start = DMACH_PCM0_TX,
109 .end = DMACH_PCM0_TX,
110 .flags = IORESOURCE_DMA,
111 },
112 [2] = {
113 .start = DMACH_PCM0_RX,
114 .end = DMACH_PCM0_RX,
115 .flags = IORESOURCE_DMA,
116 },
117};
118
119struct platform_device s5p6440_device_pcm = {
120 .name = "samsung-pcm",
121 .id = 0,
122 .num_resources = ARRAY_SIZE(s5p6440_pcm0_resource),
123 .resource = s5p6440_pcm0_resource,
124 .dev = {
125 .platform_data = &s3c_pcm_pdata,
126 },
127};
diff --git a/arch/arm/mach-s5p6440/dev-spi.c b/arch/arm/mach-s5p6440/dev-spi.c
deleted file mode 100644
index 510af44d180c..000000000000
--- a/arch/arm/mach-s5p6440/dev-spi.c
+++ /dev/null
@@ -1,176 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/irqs.h>
18#include <mach/spi-clocks.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22
23static char *spi_src_clks[] = {
24 [S5P6440_SPI_SRCCLK_PCLK] = "pclk",
25 [S5P6440_SPI_SRCCLK_SCLK] = "spi_epll",
26};
27
28/* SPI Controller platform_devices */
29
30/* Since we emulate multi-cs capability, we do not touch the CS.
31 * The emulated CS is toggled by board specific mechanism, as it can
32 * be either some immediate GPIO or some signal out of some other
33 * chip in between ... or some yet another way.
34 * We simply do not assume anything about CS.
35 */
36static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
37{
38 switch (pdev->id) {
39 case 0:
40 s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
41 s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
42 s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
43 s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
44 s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
45 s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
46 break;
47
48 case 1:
49 s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
50 s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
51 s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
52 s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
53 s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
54 s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
55 break;
56
57 default:
58 dev_err(&pdev->dev, "Invalid SPI Controller number!");
59 return -EINVAL;
60 }
61
62 return 0;
63}
64
65static struct resource s5p6440_spi0_resource[] = {
66 [0] = {
67 .start = S5P6440_PA_SPI0,
68 .end = S5P6440_PA_SPI0 + 0x100 - 1,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = DMACH_SPI0_TX,
73 .end = DMACH_SPI0_TX,
74 .flags = IORESOURCE_DMA,
75 },
76 [2] = {
77 .start = DMACH_SPI0_RX,
78 .end = DMACH_SPI0_RX,
79 .flags = IORESOURCE_DMA,
80 },
81 [3] = {
82 .start = IRQ_SPI0,
83 .end = IRQ_SPI0,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
89 .cfg_gpio = s5p6440_spi_cfg_gpio,
90 .fifo_lvl_mask = 0x1ff,
91 .rx_lvl_offset = 15,
92};
93
94static u64 spi_dmamask = DMA_BIT_MASK(32);
95
96struct platform_device s5p6440_device_spi0 = {
97 .name = "s3c64xx-spi",
98 .id = 0,
99 .num_resources = ARRAY_SIZE(s5p6440_spi0_resource),
100 .resource = s5p6440_spi0_resource,
101 .dev = {
102 .dma_mask = &spi_dmamask,
103 .coherent_dma_mask = DMA_BIT_MASK(32),
104 .platform_data = &s5p6440_spi0_pdata,
105 },
106};
107
108static struct resource s5p6440_spi1_resource[] = {
109 [0] = {
110 .start = S5P6440_PA_SPI1,
111 .end = S5P6440_PA_SPI1 + 0x100 - 1,
112 .flags = IORESOURCE_MEM,
113 },
114 [1] = {
115 .start = DMACH_SPI1_TX,
116 .end = DMACH_SPI1_TX,
117 .flags = IORESOURCE_DMA,
118 },
119 [2] = {
120 .start = DMACH_SPI1_RX,
121 .end = DMACH_SPI1_RX,
122 .flags = IORESOURCE_DMA,
123 },
124 [3] = {
125 .start = IRQ_SPI1,
126 .end = IRQ_SPI1,
127 .flags = IORESOURCE_IRQ,
128 },
129};
130
131static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
132 .cfg_gpio = s5p6440_spi_cfg_gpio,
133 .fifo_lvl_mask = 0x7f,
134 .rx_lvl_offset = 15,
135};
136
137struct platform_device s5p6440_device_spi1 = {
138 .name = "s3c64xx-spi",
139 .id = 1,
140 .num_resources = ARRAY_SIZE(s5p6440_spi1_resource),
141 .resource = s5p6440_spi1_resource,
142 .dev = {
143 .dma_mask = &spi_dmamask,
144 .coherent_dma_mask = DMA_BIT_MASK(32),
145 .platform_data = &s5p6440_spi1_pdata,
146 },
147};
148
149void __init s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
150{
151 struct s3c64xx_spi_info *pd;
152
153 /* Reject invalid configuration */
154 if (!num_cs || src_clk_nr < 0
155 || src_clk_nr > S5P6440_SPI_SRCCLK_SCLK) {
156 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
157 return;
158 }
159
160 switch (cntrlr) {
161 case 0:
162 pd = &s5p6440_spi0_pdata;
163 break;
164 case 1:
165 pd = &s5p6440_spi1_pdata;
166 break;
167 default:
168 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
169 __func__, cntrlr);
170 return;
171 }
172
173 pd->num_cs = num_cs;
174 pd->src_clk_nr = src_clk_nr;
175 pd->src_clk_name = spi_src_clks[src_clk_nr];
176}
diff --git a/arch/arm/mach-s5p6440/include/mach/debug-macro.S b/arch/arm/mach-s5p6440/include/mach/debug-macro.S
deleted file mode 100644
index 1347d7f99079..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/debug-macro.S
+++ /dev/null
@@ -1,37 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/* pull in the relevant register and map files. */
12
13#include <mach/map.h>
14#include <plat/regs-serial.h>
15
16 /* note, for the boot process to work we have to keep the UART
17 * virtual address aligned to an 1MiB boundary for the L1
18 * mapping the head code makes. We keep the UART virtual address
19 * aligned and add in the offset when we load the value here.
20 */
21
22 .macro addruart, rx, rtmp
23 mrc p15, 0, \rx, c1, c0
24 tst \rx, #1
25 ldreq \rx, = S3C_PA_UART
26 ldrne \rx, = S3C_VA_UART
27#if CONFIG_DEBUG_S3C_UART != 0
28 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
29#endif
30 .endm
31
32/* include the reset of the code which will do the work, we're only
33 * compiling for a single cpu processor type so the default of s3c2440
34 * will be fine with us.
35 */
36
37#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5p6440/include/mach/gpio.h b/arch/arm/mach-s5p6440/include/mach/gpio.h
deleted file mode 100644
index 21783834f2a2..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/gpio.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/gpio.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* GPIO bank sizes */
22#define S5P6440_GPIO_A_NR (6)
23#define S5P6440_GPIO_B_NR (7)
24#define S5P6440_GPIO_C_NR (8)
25#define S5P6440_GPIO_F_NR (2)
26#define S5P6440_GPIO_G_NR (7)
27#define S5P6440_GPIO_H_NR (10)
28#define S5P6440_GPIO_I_NR (16)
29#define S5P6440_GPIO_J_NR (12)
30#define S5P6440_GPIO_N_NR (16)
31#define S5P6440_GPIO_P_NR (8)
32#define S5P6440_GPIO_R_NR (15)
33
34/* GPIO bank numbers */
35
36/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
37 * space for debugging purposes so that any accidental
38 * change from one gpio bank to another can be caught.
39*/
40#define S5P6440_GPIO_NEXT(__gpio) \
41 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
42
43enum s5p_gpio_number {
44 S5P6440_GPIO_A_START = 0,
45 S5P6440_GPIO_B_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_A),
46 S5P6440_GPIO_C_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_B),
47 S5P6440_GPIO_F_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_C),
48 S5P6440_GPIO_G_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_F),
49 S5P6440_GPIO_H_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_G),
50 S5P6440_GPIO_I_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_H),
51 S5P6440_GPIO_J_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_I),
52 S5P6440_GPIO_N_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_J),
53 S5P6440_GPIO_P_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_N),
54 S5P6440_GPIO_R_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_P),
55};
56
57/* S5P6440 GPIO number definitions. */
58#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
59#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
60#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
61#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
62#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
63#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
64#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
65#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
66#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
67#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
68#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
69
70/* the end of the S5P6440 specific gpios */
71#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
72#define S3C_GPIO_END S5P6440_GPIO_END
73
74/* define the number of gpios we need to the one after the GPR() range */
75#define ARCH_NR_GPIOS (S5P6440_GPR(S5P6440_GPIO_R_NR) + \
76 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
77
78#include <asm-generic/gpio.h>
79
80#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/io.h b/arch/arm/mach-s5p6440/include/mach/io.h
deleted file mode 100644
index fa2d69cb1ad7..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* arch/arm/mach-s5p6440/include/mach/io.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben-linux@fluff.org>
5 *
6 * Default IO routines for S3C64XX based
7 */
8
9#ifndef __ASM_ARM_ARCH_IO_H
10#define __ASM_ARM_ARCH_IO_H
11
12/* No current ISA/PCI bus support. */
13#define __io(a) __typesafe_io(a)
14#define __mem_pci(a) (a)
15
16#define IO_SPACE_LIMIT (0xFFFFFFFF)
17
18#endif
diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h
deleted file mode 100644
index 6cc5cbc88ffb..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/map.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/map.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
18
19#define S5P6440_PA_CHIPID (0xE0000000)
20#define S5P_PA_CHIPID S5P6440_PA_CHIPID
21
22#define S5P6440_PA_SYSCON (0xE0100000)
23#define S5P6440_PA_CLK (S5P6440_PA_SYSCON + 0x0)
24#define S5P_PA_SYSCON S5P6440_PA_SYSCON
25
26#define S5P6440_PA_GPIO (0xE0308000)
27#define S5P_PA_GPIO S5P6440_PA_GPIO
28
29#define S5P6440_PA_VIC0 (0xE4000000)
30#define S5P_PA_VIC0 S5P6440_PA_VIC0
31
32#define S5P6440_PA_PDMA 0xE9000000
33
34#define S5P6440_PA_VIC1 (0xE4100000)
35#define S5P_PA_VIC1 S5P6440_PA_VIC1
36
37#define S5P6440_PA_TIMER (0xEA000000)
38#define S5P_PA_TIMER S5P6440_PA_TIMER
39
40#define S5P6440_PA_RTC (0xEA100000)
41
42#define S5P6440_PA_WDT (0xEA200000)
43#define S5P_PA_WDT S5P6440_PA_WDT
44
45#define S5P6440_PA_UART (0xEC000000)
46
47#define S5P_PA_UART0 (S5P6440_PA_UART + 0x0)
48#define S5P_PA_UART1 (S5P6440_PA_UART + 0x400)
49#define S5P_PA_UART2 (S5P6440_PA_UART + 0x800)
50#define S5P_PA_UART3 (S5P6440_PA_UART + 0xC00)
51
52#define S5P_SZ_UART SZ_256
53
54#define S5P6440_PA_IIC0 (0xEC104000)
55#define S5P6440_PA_IIC1 (0xEC20F000)
56
57#define S5P6440_PA_SPI0 0xEC400000
58#define S5P6440_PA_SPI1 0xEC500000
59
60#define S5P6440_PA_HSOTG (0xED100000)
61
62#define S5P6440_PA_HSMMC0 (0xED800000)
63#define S5P6440_PA_HSMMC1 (0xED900000)
64#define S5P6440_PA_HSMMC2 (0xEDA00000)
65
66#define S5P6440_PA_SDRAM (0x20000000)
67#define S5P_PA_SDRAM S5P6440_PA_SDRAM
68
69/* I2S */
70#define S5P6440_PA_I2S 0xF2000000
71
72/* PCM */
73#define S5P6440_PA_PCM 0xF2100000
74
75#define S5P6440_PA_ADC (0xF3000000)
76
77/* compatibiltiy defines. */
78#define S3C_PA_UART S5P6440_PA_UART
79#define S3C_PA_IIC S5P6440_PA_IIC0
80#define S3C_PA_RTC S5P6440_PA_RTC
81#define S3C_PA_IIC1 S5P6440_PA_IIC1
82#define S3C_PA_WDT S5P6440_PA_WDT
83
84#define SAMSUNG_PA_ADC S5P6440_PA_ADC
85
86#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-clock.h b/arch/arm/mach-s5p6440/include/mach/regs-clock.h
deleted file mode 100644
index c783ecc9f193..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/regs-clock.h
+++ /dev/null
@@ -1,130 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S5P_APLL_LOCK S5P_CLKREG(0x00)
21#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
22#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
23#define S5P_APLL_CON S5P_CLKREG(0x0C)
24#define S5P_MPLL_CON S5P_CLKREG(0x10)
25#define S5P_EPLL_CON S5P_CLKREG(0x14)
26#define S5P_EPLL_CON_K S5P_CLKREG(0x18)
27#define S5P_CLK_SRC0 S5P_CLKREG(0x1C)
28#define S5P_CLK_DIV0 S5P_CLKREG(0x20)
29#define S5P_CLK_DIV1 S5P_CLKREG(0x24)
30#define S5P_CLK_DIV2 S5P_CLKREG(0x28)
31#define S5P_CLK_OUT S5P_CLKREG(0x2C)
32#define S5P_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
33#define S5P_CLK_GATE_PCLK S5P_CLKREG(0x34)
34#define S5P_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
35#define S5P_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
36#define S5P_CLK_DIV3 S5P_CLKREG(0x40)
37#define S5P_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
38#define S5P_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
39#define S5P_AHB_CON0 S5P_CLKREG(0x100)
40#define S5P_CLK_SRC1 S5P_CLKREG(0x10C)
41#define S5P_SWRESET S5P_CLKREG(0x114)
42#define S5P_SYS_ID S5P_CLKREG(0x118)
43#define S5P_SYS_OTHERS S5P_CLKREG(0x11C)
44#define S5P_MEM_CFG_STAT S5P_CLKREG(0x12C)
45#define S5P_PWR_CFG S5P_CLKREG(0x804)
46#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
47#define S5P_NORMAL_CFG S5P_CLKREG(0x810)
48#define S5P_STOP_CFG S5P_CLKREG(0x814)
49#define S5P_SLEEP_CFG S5P_CLKREG(0x818)
50#define S5P_OSC_FREQ S5P_CLKREG(0x820)
51#define S5P_OSC_STABLE S5P_CLKREG(0x824)
52#define S5P_PWR_STABLE S5P_CLKREG(0x828)
53#define S5P_MTC_STABLE S5P_CLKREG(0x830)
54#define S5P_OTHERS S5P_CLKREG(0x900)
55#define S5P_RST_STAT S5P_CLKREG(0x904)
56#define S5P_WAKEUP_STAT S5P_CLKREG(0x908)
57#define S5P_SLPEN S5P_CLKREG(0x930)
58#define S5P_INFORM0 S5P_CLKREG(0xA00)
59#define S5P_INFORM1 S5P_CLKREG(0xA04)
60#define S5P_INFORM2 S5P_CLKREG(0xA08)
61#define S5P_INFORM3 S5P_CLKREG(0xA0C)
62
63/* CLKDIV0 */
64#define S5P_CLKDIV0_PCLK_MASK (0xf << 12)
65#define S5P_CLKDIV0_PCLK_SHIFT (12)
66#define S5P_CLKDIV0_HCLK_MASK (0xf << 8)
67#define S5P_CLKDIV0_HCLK_SHIFT (8)
68#define S5P_CLKDIV0_MPLL_MASK (0x1 << 4)
69#define S5P_CLKDIV0_ARM_MASK (0xf << 0)
70#define S5P_CLKDIV0_ARM_SHIFT (0)
71
72/* CLKDIV3 */
73#define S5P_CLKDIV3_PCLK_LOW_MASK (0xf << 12)
74#define S5P_CLKDIV3_PCLK_LOW_SHIFT (12)
75#define S5P_CLKDIV3_HCLK_LOW_MASK (0xf << 8)
76#define S5P_CLKDIV3_HCLK_LOW_SHIFT (8)
77
78/* HCLK0 GATE Registers */
79#define S5P_CLKCON_HCLK0_USB (1<<20)
80#define S5P_CLKCON_HCLK0_HSMMC2 (1<<19)
81#define S5P_CLKCON_HCLK0_HSMMC1 (1<<18)
82#define S5P_CLKCON_HCLK0_HSMMC0 (1<<17)
83#define S5P_CLKCON_HCLK0_POST0 (1<<5)
84
85/* HCLK1 GATE Registers */
86#define S5P_CLKCON_HCLK1_DISPCON (1<<1)
87
88/* PCLK GATE Registers */
89#define S5P_CLKCON_PCLK_IIS2 (1<<26)
90#define S5P_CLKCON_PCLK_SPI1 (1<<22)
91#define S5P_CLKCON_PCLK_SPI0 (1<<21)
92#define S5P_CLKCON_PCLK_GPIO (1<<18)
93#define S5P_CLKCON_PCLK_IIC0 (1<<17)
94#define S5P_CLKCON_PCLK_TSADC (1<<12)
95#define S5P_CLKCON_PCLK_PWM (1<<7)
96#define S5P_CLKCON_PCLK_RTC (1<<6)
97#define S5P_CLKCON_PCLK_WDT (1<<5)
98#define S5P_CLKCON_PCLK_UART3 (1<<4)
99#define S5P_CLKCON_PCLK_UART2 (1<<3)
100#define S5P_CLKCON_PCLK_UART1 (1<<2)
101#define S5P_CLKCON_PCLK_UART0 (1<<1)
102
103/* SCLK0 GATE Registers */
104#define S5P_CLKCON_SCLK0_MMC2_48 (1<<29)
105#define S5P_CLKCON_SCLK0_MMC1_48 (1<<28)
106#define S5P_CLKCON_SCLK0_MMC0_48 (1<<27)
107#define S5P_CLKCON_SCLK0_MMC2 (1<<26)
108#define S5P_CLKCON_SCLK0_MMC1 (1<<25)
109#define S5P_CLKCON_SCLK0_MMC0 (1<<24)
110#define S5P_CLKCON_SCLK0_SPI1_48 (1<<23)
111#define S5P_CLKCON_SCLK0_SPI0_48 (1<<22)
112#define S5P_CLKCON_SCLK0_SPI1 (1<<21)
113#define S5P_CLKCON_SCLK0_SPI0 (1<<20)
114#define S5P_CLKCON_SCLK0_UART (1<<5)
115
116/* SCLK1 GATE Registers */
117
118/* MEM0 GATE Registers */
119#define S5P_CLKCON_MEM0_HCLK_NFCON (1<<2)
120
121/*OTHERS Resgister */
122#define S5P_OTHERS_USB_SIG_MASK (1<<16)
123#define S5P_OTHERS_HCLK_LOW_SEL_MPLL (1<<6)
124
125/* Compatibility defines */
126#define ARM_CLK_DIV S5P_CLK_DIV0
127#define ARM_DIV_RATIO_SHIFT 0
128#define ARM_DIV_MASK (0xf << ARM_DIV_RATIO_SHIFT)
129
130#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/spi-clocks.h b/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
deleted file mode 100644
index 5fbca50d1cfb..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S5P6440_PLAT_SPI_CLKS_H
12#define __S5P6440_PLAT_SPI_CLKS_H __FILE__
13
14#define S5P6440_SPI_SRCCLK_PCLK 0
15#define S5P6440_SPI_SRCCLK_SCLK 1
16
17#endif /* __S5P6440_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/uncompress.h b/arch/arm/mach-s5p6440/include/mach/uncompress.h
deleted file mode 100644
index 7c1f600d65c0..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/uncompress.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/uncompress.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - uncompress code
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H
15
16#include <mach/map.h>
17#include <plat/uncompress.h>
18
19static void arch_detect_cpu(void)
20{
21 /* we do not need to do any cpu detection here at the moment. */
22}
23
24#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p6440/init.c b/arch/arm/mach-s5p6440/init.c
deleted file mode 100644
index a1f3727e4021..000000000000
--- a/arch/arm/mach-s5p6440/init.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/init.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Init support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/serial_core.h>
17
18#include <plat/cpu.h>
19#include <plat/devs.h>
20#include <plat/s5p6440.h>
21#include <plat/regs-serial.h>
22
23static struct s3c24xx_uart_clksrc s5p6440_serial_clocks[] = {
24 [0] = {
25 .name = "pclk_low",
26 .divisor = 1,
27 .min_baud = 0,
28 .max_baud = 0,
29 },
30 [1] = {
31 .name = "uclk1",
32 .divisor = 1,
33 .min_baud = 0,
34 .max_baud = 0,
35 },
36};
37
38/* uart registration process */
39void __init s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
40{
41 struct s3c2410_uartcfg *tcfg = cfg;
42 u32 ucnt;
43
44 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
45 if (!tcfg->clocks) {
46 tcfg->clocks = s5p6440_serial_clocks;
47 tcfg->clocks_size = ARRAY_SIZE(s5p6440_serial_clocks);
48 }
49 }
50
51 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
52}
diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c
index a48fb553fd01..842af86bda6d 100644
--- a/arch/arm/mach-s5p6442/cpu.c
+++ b/arch/arm/mach-s5p6442/cpu.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5p6442/cpu.c 1/* linux/arch/arm/mach-s5p6442/cpu.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -19,6 +19,7 @@
19#include <linux/sysdev.h> 19#include <linux/sysdev.h>
20#include <linux/serial_core.h> 20#include <linux/serial_core.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/sched.h>
22 23
23#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
24#include <asm/mach/map.h> 25#include <asm/mach/map.h>
@@ -47,10 +48,30 @@ static struct map_desc s5p6442_iodesc[] __initdata = {
47 .length = SZ_16K, 48 .length = SZ_16K,
48 .type = MT_DEVICE, 49 .type = MT_DEVICE,
49 }, { 50 }, {
51 .virtual = (unsigned long)S5P_VA_GPIO,
52 .pfn = __phys_to_pfn(S5P6442_PA_GPIO),
53 .length = SZ_4K,
54 .type = MT_DEVICE,
55 }, {
56 .virtual = (unsigned long)VA_VIC0,
57 .pfn = __phys_to_pfn(S5P6442_PA_VIC0),
58 .length = SZ_16K,
59 .type = MT_DEVICE,
60 }, {
61 .virtual = (unsigned long)VA_VIC1,
62 .pfn = __phys_to_pfn(S5P6442_PA_VIC1),
63 .length = SZ_16K,
64 .type = MT_DEVICE,
65 }, {
50 .virtual = (unsigned long)VA_VIC2, 66 .virtual = (unsigned long)VA_VIC2,
51 .pfn = __phys_to_pfn(S5P6442_PA_VIC2), 67 .pfn = __phys_to_pfn(S5P6442_PA_VIC2),
52 .length = SZ_16K, 68 .length = SZ_16K,
53 .type = MT_DEVICE, 69 .type = MT_DEVICE,
70 }, {
71 .virtual = (unsigned long)S3C_VA_UART,
72 .pfn = __phys_to_pfn(S3C_PA_UART),
73 .length = SZ_512K,
74 .type = MT_DEVICE,
54 } 75 }
55}; 76};
56 77
@@ -62,10 +83,11 @@ static void s5p6442_idle(void)
62 local_irq_enable(); 83 local_irq_enable();
63} 84}
64 85
65/* s5p6442_map_io 86/*
87 * s5p6442_map_io
66 * 88 *
67 * register the standard cpu IO areas 89 * register the standard cpu IO areas
68*/ 90 */
69 91
70void __init s5p6442_map_io(void) 92void __init s5p6442_map_io(void)
71{ 93{
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
index 281d256faafb..31fb2e68d527 100644
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ b/arch/arm/mach-s5p6442/include/mach/map.h
@@ -23,16 +23,10 @@
23#define S5P_PA_SYSCON S5P6442_PA_SYSCON 23#define S5P_PA_SYSCON S5P6442_PA_SYSCON
24 24
25#define S5P6442_PA_GPIO (0xE0200000) 25#define S5P6442_PA_GPIO (0xE0200000)
26#define S5P_PA_GPIO S5P6442_PA_GPIO
27 26
28#define S5P6442_PA_VIC0 (0xE4000000) 27#define S5P6442_PA_VIC0 (0xE4000000)
29#define S5P_PA_VIC0 S5P6442_PA_VIC0
30
31#define S5P6442_PA_VIC1 (0xE4100000) 28#define S5P6442_PA_VIC1 (0xE4100000)
32#define S5P_PA_VIC1 S5P6442_PA_VIC1
33
34#define S5P6442_PA_VIC2 (0xE4200000) 29#define S5P6442_PA_VIC2 (0xE4200000)
35#define S5P_PA_VIC2 S5P6442_PA_VIC2
36 30
37#define S5P6442_PA_MDMA 0xE8000000 31#define S5P6442_PA_MDMA 0xE8000000
38#define S5P6442_PA_PDMA 0xE9000000 32#define S5P6442_PA_PDMA 0xE9000000
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
new file mode 100644
index 000000000000..fbcae9352022
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -0,0 +1,57 @@
1# arch/arm/mach-s5p64x0/Kconfig
2#
3# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8if ARCH_S5P64X0
9
10config CPU_S5P6440
11 bool
12 select PLAT_S5P
13 select S3C_PL330_DMA
14 help
15 Enable S5P6440 CPU support
16
17config CPU_S5P6450
18 bool
19 select PLAT_S5P
20 select S3C_PL330_DMA
21 help
22 Enable S5P6450 CPU support
23
24config S5P64X0_SETUP_I2C1
25 bool
26 help
27 Common setup code for i2c bus 1.
28
29# machine support
30
31config MACH_SMDK6440
32 bool "SMDK6440"
33 select CPU_S5P6440
34 select S3C_DEV_I2C1
35 select S3C_DEV_RTC
36 select S3C_DEV_WDT
37 select S3C64XX_DEV_SPI
38 select SAMSUNG_DEV_ADC
39 select SAMSUNG_DEV_TS
40 select S5P64X0_SETUP_I2C1
41 help
42 Machine support for the Samsung SMDK6440
43
44config MACH_SMDK6450
45 bool "SMDK6450"
46 select CPU_S5P6450
47 select S3C_DEV_I2C1
48 select S3C_DEV_RTC
49 select S3C_DEV_WDT
50 select S3C64XX_DEV_SPI
51 select SAMSUNG_DEV_ADC
52 select SAMSUNG_DEV_TS
53 select S5P64X0_SETUP_I2C1
54 help
55 Machine support for the Samsung SMDK6450
56
57endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
new file mode 100644
index 000000000000..2655829e6bf8
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -0,0 +1,30 @@
1# arch/arm/mach-s5p64x0/Makefile
2#
3# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for S5P64X0 system
14
15obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o
16obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o
17obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o gpio.o
18obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
19
20# machine support
21
22obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o
23obj-$(CONFIG_MACH_SMDK6450) += mach-smdk6450.o
24
25# device support
26
27obj-y += dev-audio.o
28obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
29
30obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-s5p6440/Makefile.boot b/arch/arm/mach-s5p64x0/Makefile.boot
index ff90aa13bd67..ff90aa13bd67 100644
--- a/arch/arm/mach-s5p6440/Makefile.boot
+++ b/arch/arm/mach-s5p64x0/Makefile.boot
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
new file mode 100644
index 000000000000..f93dcd8b4d6a
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -0,0 +1,626 @@
1/* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P6440 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/sysdev.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26#include <mach/s5p64x0-clock.h>
27
28#include <plat/cpu-freq.h>
29#include <plat/clock.h>
30#include <plat/cpu.h>
31#include <plat/pll.h>
32#include <plat/s5p-clock.h>
33#include <plat/clock-clksrc.h>
34#include <plat/s5p6440.h>
35
36static u32 epll_div[][5] = {
37 { 36000000, 0, 48, 1, 4 },
38 { 48000000, 0, 32, 1, 3 },
39 { 60000000, 0, 40, 1, 3 },
40 { 72000000, 0, 48, 1, 3 },
41 { 84000000, 0, 28, 1, 2 },
42 { 96000000, 0, 32, 1, 2 },
43 { 32768000, 45264, 43, 1, 4 },
44 { 45158000, 6903, 30, 1, 3 },
45 { 49152000, 50332, 32, 1, 3 },
46 { 67738000, 10398, 45, 1, 3 },
47 { 73728000, 9961, 49, 1, 3 }
48};
49
50static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
51{
52 unsigned int epll_con, epll_con_k;
53 unsigned int i;
54
55 if (clk->rate == rate) /* Return if nothing changed */
56 return 0;
57
58 epll_con = __raw_readl(S5P64X0_EPLL_CON);
59 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
60
61 epll_con_k &= ~(PLL90XX_KDIV_MASK);
62 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
63
64 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
65 if (epll_div[i][0] == rate) {
66 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
67 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
68 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
69 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
70 break;
71 }
72 }
73
74 if (i == ARRAY_SIZE(epll_div)) {
75 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
76 return -EINVAL;
77 }
78
79 __raw_writel(epll_con, S5P64X0_EPLL_CON);
80 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
81
82 clk->rate = rate;
83
84 return 0;
85}
86
87static struct clk_ops s5p6440_epll_ops = {
88 .get_rate = s5p64x0_epll_get_rate,
89 .set_rate = s5p6440_epll_set_rate,
90};
91
92static struct clksrc_clk clk_hclk = {
93 .clk = {
94 .name = "clk_hclk",
95 .id = -1,
96 .parent = &clk_armclk.clk,
97 },
98 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
99};
100
101static struct clksrc_clk clk_pclk = {
102 .clk = {
103 .name = "clk_pclk",
104 .id = -1,
105 .parent = &clk_hclk.clk,
106 },
107 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
108};
109static struct clksrc_clk clk_hclk_low = {
110 .clk = {
111 .name = "clk_hclk_low",
112 .id = -1,
113 },
114 .sources = &clkset_hclk_low,
115 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
116 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
117};
118
119static struct clksrc_clk clk_pclk_low = {
120 .clk = {
121 .name = "clk_pclk_low",
122 .id = -1,
123 .parent = &clk_hclk_low.clk,
124 },
125 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
126};
127
128/*
129 * The following clocks will be disabled during clock initialization. It is
130 * recommended to keep the following clocks disabled until the driver requests
131 * for enabling the clock.
132 */
133static struct clk init_clocks_disable[] = {
134 {
135 .name = "nand",
136 .id = -1,
137 .parent = &clk_hclk.clk,
138 .enable = s5p64x0_mem_ctrl,
139 .ctrlbit = (1 << 2),
140 }, {
141 .name = "post",
142 .id = -1,
143 .parent = &clk_hclk_low.clk,
144 .enable = s5p64x0_hclk0_ctrl,
145 .ctrlbit = (1 << 5)
146 }, {
147 .name = "2d",
148 .id = -1,
149 .parent = &clk_hclk.clk,
150 .enable = s5p64x0_hclk0_ctrl,
151 .ctrlbit = (1 << 8),
152 }, {
153 .name = "hsmmc",
154 .id = 0,
155 .parent = &clk_hclk_low.clk,
156 .enable = s5p64x0_hclk0_ctrl,
157 .ctrlbit = (1 << 17),
158 }, {
159 .name = "hsmmc",
160 .id = 1,
161 .parent = &clk_hclk_low.clk,
162 .enable = s5p64x0_hclk0_ctrl,
163 .ctrlbit = (1 << 18),
164 }, {
165 .name = "hsmmc",
166 .id = 2,
167 .parent = &clk_hclk_low.clk,
168 .enable = s5p64x0_hclk0_ctrl,
169 .ctrlbit = (1 << 19),
170 }, {
171 .name = "otg",
172 .id = -1,
173 .parent = &clk_hclk_low.clk,
174 .enable = s5p64x0_hclk0_ctrl,
175 .ctrlbit = (1 << 20)
176 }, {
177 .name = "irom",
178 .id = -1,
179 .parent = &clk_hclk.clk,
180 .enable = s5p64x0_hclk0_ctrl,
181 .ctrlbit = (1 << 25),
182 }, {
183 .name = "lcd",
184 .id = -1,
185 .parent = &clk_hclk_low.clk,
186 .enable = s5p64x0_hclk1_ctrl,
187 .ctrlbit = (1 << 1),
188 }, {
189 .name = "hclk_fimgvg",
190 .id = -1,
191 .parent = &clk_hclk.clk,
192 .enable = s5p64x0_hclk1_ctrl,
193 .ctrlbit = (1 << 2),
194 }, {
195 .name = "tsi",
196 .id = -1,
197 .parent = &clk_hclk_low.clk,
198 .enable = s5p64x0_hclk1_ctrl,
199 .ctrlbit = (1 << 0),
200 }, {
201 .name = "watchdog",
202 .id = -1,
203 .parent = &clk_pclk_low.clk,
204 .enable = s5p64x0_pclk_ctrl,
205 .ctrlbit = (1 << 5),
206 }, {
207 .name = "rtc",
208 .id = -1,
209 .parent = &clk_pclk_low.clk,
210 .enable = s5p64x0_pclk_ctrl,
211 .ctrlbit = (1 << 6),
212 }, {
213 .name = "timers",
214 .id = -1,
215 .parent = &clk_pclk_low.clk,
216 .enable = s5p64x0_pclk_ctrl,
217 .ctrlbit = (1 << 7),
218 }, {
219 .name = "pcm",
220 .id = -1,
221 .parent = &clk_pclk_low.clk,
222 .enable = s5p64x0_pclk_ctrl,
223 .ctrlbit = (1 << 8),
224 }, {
225 .name = "adc",
226 .id = -1,
227 .parent = &clk_pclk_low.clk,
228 .enable = s5p64x0_pclk_ctrl,
229 .ctrlbit = (1 << 12),
230 }, {
231 .name = "i2c",
232 .id = -1,
233 .parent = &clk_pclk_low.clk,
234 .enable = s5p64x0_pclk_ctrl,
235 .ctrlbit = (1 << 17),
236 }, {
237 .name = "spi",
238 .id = 0,
239 .parent = &clk_pclk_low.clk,
240 .enable = s5p64x0_pclk_ctrl,
241 .ctrlbit = (1 << 21),
242 }, {
243 .name = "spi",
244 .id = 1,
245 .parent = &clk_pclk_low.clk,
246 .enable = s5p64x0_pclk_ctrl,
247 .ctrlbit = (1 << 22),
248 }, {
249 .name = "gps",
250 .id = -1,
251 .parent = &clk_pclk_low.clk,
252 .enable = s5p64x0_pclk_ctrl,
253 .ctrlbit = (1 << 25),
254 }, {
255 .name = "i2s_v40",
256 .id = 0,
257 .parent = &clk_pclk_low.clk,
258 .enable = s5p64x0_pclk_ctrl,
259 .ctrlbit = (1 << 26),
260 }, {
261 .name = "dsim",
262 .id = -1,
263 .parent = &clk_pclk_low.clk,
264 .enable = s5p64x0_pclk_ctrl,
265 .ctrlbit = (1 << 28),
266 }, {
267 .name = "etm",
268 .id = -1,
269 .parent = &clk_pclk.clk,
270 .enable = s5p64x0_pclk_ctrl,
271 .ctrlbit = (1 << 29),
272 }, {
273 .name = "dmc0",
274 .id = -1,
275 .parent = &clk_pclk.clk,
276 .enable = s5p64x0_pclk_ctrl,
277 .ctrlbit = (1 << 30),
278 }, {
279 .name = "pclk_fimgvg",
280 .id = -1,
281 .parent = &clk_pclk.clk,
282 .enable = s5p64x0_pclk_ctrl,
283 .ctrlbit = (1 << 31),
284 }, {
285 .name = "sclk_spi_48",
286 .id = 0,
287 .parent = &clk_48m,
288 .enable = s5p64x0_sclk_ctrl,
289 .ctrlbit = (1 << 22),
290 }, {
291 .name = "sclk_spi_48",
292 .id = 1,
293 .parent = &clk_48m,
294 .enable = s5p64x0_sclk_ctrl,
295 .ctrlbit = (1 << 23),
296 }, {
297 .name = "mmc_48m",
298 .id = 0,
299 .parent = &clk_48m,
300 .enable = s5p64x0_sclk_ctrl,
301 .ctrlbit = (1 << 27),
302 }, {
303 .name = "mmc_48m",
304 .id = 1,
305 .parent = &clk_48m,
306 .enable = s5p64x0_sclk_ctrl,
307 .ctrlbit = (1 << 28),
308 }, {
309 .name = "mmc_48m",
310 .id = 2,
311 .parent = &clk_48m,
312 .enable = s5p64x0_sclk_ctrl,
313 .ctrlbit = (1 << 29),
314 },
315};
316
317/*
318 * The following clocks will be enabled during clock initialization.
319 */
320static struct clk init_clocks[] = {
321 {
322 .name = "intc",
323 .id = -1,
324 .parent = &clk_hclk.clk,
325 .enable = s5p64x0_hclk0_ctrl,
326 .ctrlbit = (1 << 1),
327 }, {
328 .name = "mem",
329 .id = -1,
330 .parent = &clk_hclk.clk,
331 .enable = s5p64x0_hclk0_ctrl,
332 .ctrlbit = (1 << 21),
333 }, {
334 .name = "dma",
335 .id = -1,
336 .parent = &clk_hclk_low.clk,
337 .enable = s5p64x0_hclk0_ctrl,
338 .ctrlbit = (1 << 12),
339 }, {
340 .name = "uart",
341 .id = 0,
342 .parent = &clk_pclk_low.clk,
343 .enable = s5p64x0_pclk_ctrl,
344 .ctrlbit = (1 << 1),
345 }, {
346 .name = "uart",
347 .id = 1,
348 .parent = &clk_pclk_low.clk,
349 .enable = s5p64x0_pclk_ctrl,
350 .ctrlbit = (1 << 2),
351 }, {
352 .name = "uart",
353 .id = 2,
354 .parent = &clk_pclk_low.clk,
355 .enable = s5p64x0_pclk_ctrl,
356 .ctrlbit = (1 << 3),
357 }, {
358 .name = "uart",
359 .id = 3,
360 .parent = &clk_pclk_low.clk,
361 .enable = s5p64x0_pclk_ctrl,
362 .ctrlbit = (1 << 4),
363 }, {
364 .name = "gpio",
365 .id = -1,
366 .parent = &clk_pclk_low.clk,
367 .enable = s5p64x0_pclk_ctrl,
368 .ctrlbit = (1 << 18),
369 },
370};
371
372static struct clk clk_iis_cd_v40 = {
373 .name = "iis_cdclk_v40",
374 .id = -1,
375};
376
377static struct clk clk_pcm_cd = {
378 .name = "pcm_cdclk",
379 .id = -1,
380};
381
382static struct clk *clkset_group1_list[] = {
383 &clk_mout_epll.clk,
384 &clk_dout_mpll.clk,
385 &clk_fin_epll,
386};
387
388static struct clksrc_sources clkset_group1 = {
389 .sources = clkset_group1_list,
390 .nr_sources = ARRAY_SIZE(clkset_group1_list),
391};
392
393static struct clk *clkset_uart_list[] = {
394 &clk_mout_epll.clk,
395 &clk_dout_mpll.clk,
396};
397
398static struct clksrc_sources clkset_uart = {
399 .sources = clkset_uart_list,
400 .nr_sources = ARRAY_SIZE(clkset_uart_list),
401};
402
403static struct clk *clkset_audio_list[] = {
404 &clk_mout_epll.clk,
405 &clk_dout_mpll.clk,
406 &clk_fin_epll,
407 &clk_iis_cd_v40,
408 &clk_pcm_cd,
409};
410
411static struct clksrc_sources clkset_audio = {
412 .sources = clkset_audio_list,
413 .nr_sources = ARRAY_SIZE(clkset_audio_list),
414};
415
416static struct clksrc_clk clksrcs[] = {
417 {
418 .clk = {
419 .name = "mmc_bus",
420 .id = 0,
421 .ctrlbit = (1 << 24),
422 .enable = s5p64x0_sclk_ctrl,
423 },
424 .sources = &clkset_group1,
425 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
426 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
427 }, {
428 .clk = {
429 .name = "mmc_bus",
430 .id = 1,
431 .ctrlbit = (1 << 25),
432 .enable = s5p64x0_sclk_ctrl,
433 },
434 .sources = &clkset_group1,
435 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
436 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
437 }, {
438 .clk = {
439 .name = "mmc_bus",
440 .id = 2,
441 .ctrlbit = (1 << 26),
442 .enable = s5p64x0_sclk_ctrl,
443 },
444 .sources = &clkset_group1,
445 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
446 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
447 }, {
448 .clk = {
449 .name = "uclk1",
450 .id = -1,
451 .ctrlbit = (1 << 5),
452 .enable = s5p64x0_sclk_ctrl,
453 },
454 .sources = &clkset_uart,
455 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
456 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
457 }, {
458 .clk = {
459 .name = "sclk_spi",
460 .id = 0,
461 .ctrlbit = (1 << 20),
462 .enable = s5p64x0_sclk_ctrl,
463 },
464 .sources = &clkset_group1,
465 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
466 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
467 }, {
468 .clk = {
469 .name = "sclk_spi",
470 .id = 1,
471 .ctrlbit = (1 << 21),
472 .enable = s5p64x0_sclk_ctrl,
473 },
474 .sources = &clkset_group1,
475 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
476 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
477 }, {
478 .clk = {
479 .name = "sclk_post",
480 .id = -1,
481 .ctrlbit = (1 << 10),
482 .enable = s5p64x0_sclk_ctrl,
483 },
484 .sources = &clkset_group1,
485 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
486 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
487 }, {
488 .clk = {
489 .name = "sclk_dispcon",
490 .id = -1,
491 .ctrlbit = (1 << 1),
492 .enable = s5p64x0_sclk1_ctrl,
493 },
494 .sources = &clkset_group1,
495 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
496 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
497 }, {
498 .clk = {
499 .name = "sclk_fimgvg",
500 .id = -1,
501 .ctrlbit = (1 << 2),
502 .enable = s5p64x0_sclk1_ctrl,
503 },
504 .sources = &clkset_group1,
505 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
506 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
507 }, {
508 .clk = {
509 .name = "sclk_audio2",
510 .id = -1,
511 .ctrlbit = (1 << 11),
512 .enable = s5p64x0_sclk_ctrl,
513 },
514 .sources = &clkset_audio,
515 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
516 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
517 },
518};
519
520/* Clock initialization code */
521static struct clksrc_clk *sysclks[] = {
522 &clk_mout_apll,
523 &clk_mout_epll,
524 &clk_mout_mpll,
525 &clk_dout_mpll,
526 &clk_armclk,
527 &clk_hclk,
528 &clk_pclk,
529 &clk_hclk_low,
530 &clk_pclk_low,
531};
532
533void __init_or_cpufreq s5p6440_setup_clocks(void)
534{
535 struct clk *xtal_clk;
536
537 unsigned long xtal;
538 unsigned long fclk;
539 unsigned long hclk;
540 unsigned long hclk_low;
541 unsigned long pclk;
542 unsigned long pclk_low;
543
544 unsigned long apll;
545 unsigned long mpll;
546 unsigned long epll;
547 unsigned int ptr;
548
549 /* Set S5P6440 functions for clk_fout_epll */
550
551 clk_fout_epll.enable = s5p64x0_epll_enable;
552 clk_fout_epll.ops = &s5p6440_epll_ops;
553
554 clk_48m.enable = s5p64x0_clk48m_ctrl;
555
556 xtal_clk = clk_get(NULL, "ext_xtal");
557 BUG_ON(IS_ERR(xtal_clk));
558
559 xtal = clk_get_rate(xtal_clk);
560 clk_put(xtal_clk);
561
562 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
563 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
564 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
565 __raw_readl(S5P64X0_EPLL_CON_K));
566
567 clk_fout_apll.rate = apll;
568 clk_fout_mpll.rate = mpll;
569 clk_fout_epll.rate = epll;
570
571 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
572 " E=%ld.%ldMHz\n",
573 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
574
575 fclk = clk_get_rate(&clk_armclk.clk);
576 hclk = clk_get_rate(&clk_hclk.clk);
577 pclk = clk_get_rate(&clk_pclk.clk);
578 hclk_low = clk_get_rate(&clk_hclk_low.clk);
579 pclk_low = clk_get_rate(&clk_pclk_low.clk);
580
581 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
582 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
583 print_mhz(hclk), print_mhz(hclk_low),
584 print_mhz(pclk), print_mhz(pclk_low));
585
586 clk_f.rate = fclk;
587 clk_h.rate = hclk;
588 clk_p.rate = pclk;
589
590 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
591 s3c_set_clksrc(&clksrcs[ptr], true);
592}
593
594static struct clk *clks[] __initdata = {
595 &clk_ext,
596 &clk_iis_cd_v40,
597 &clk_pcm_cd,
598};
599
600void __init s5p6440_register_clocks(void)
601{
602 struct clk *clkp;
603 int ret;
604 int ptr;
605
606 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
607
608 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
609 s3c_register_clksrc(sysclks[ptr], 1);
610
611 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
612 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
613
614 clkp = init_clocks_disable;
615 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
616
617 ret = s3c24xx_register_clock(clkp);
618 if (ret < 0) {
619 printk(KERN_ERR "Failed to register clock %s (%d)\n",
620 clkp->name, ret);
621 }
622 (clkp->enable)(clkp, 0);
623 }
624
625 s3c_pwmclk_init();
626}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
new file mode 100644
index 000000000000..f9afb05b217c
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -0,0 +1,655 @@
1/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P6450 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/sysdev.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26#include <mach/s5p64x0-clock.h>
27
28#include <plat/cpu-freq.h>
29#include <plat/clock.h>
30#include <plat/cpu.h>
31#include <plat/pll.h>
32#include <plat/s5p-clock.h>
33#include <plat/clock-clksrc.h>
34#include <plat/s5p6450.h>
35
36static struct clksrc_clk clk_mout_dpll = {
37 .clk = {
38 .name = "mout_dpll",
39 .id = -1,
40 },
41 .sources = &clk_src_dpll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
43};
44
45static u32 epll_div[][5] = {
46 { 133000000, 27307, 55, 2, 2 },
47 { 100000000, 43691, 41, 2, 2 },
48 { 480000000, 0, 80, 2, 0 },
49};
50
51static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
52{
53 unsigned int epll_con, epll_con_k;
54 unsigned int i;
55
56 if (clk->rate == rate) /* Return if nothing changed */
57 return 0;
58
59 epll_con = __raw_readl(S5P64X0_EPLL_CON);
60 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
61
62 epll_con_k &= ~(PLL90XX_KDIV_MASK);
63 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
64
65 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
66 if (epll_div[i][0] == rate) {
67 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
68 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
69 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
70 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
71 break;
72 }
73 }
74
75 if (i == ARRAY_SIZE(epll_div)) {
76 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
77 return -EINVAL;
78 }
79
80 __raw_writel(epll_con, S5P64X0_EPLL_CON);
81 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
82
83 clk->rate = rate;
84
85 return 0;
86}
87
88static struct clk_ops s5p6450_epll_ops = {
89 .get_rate = s5p64x0_epll_get_rate,
90 .set_rate = s5p6450_epll_set_rate,
91};
92
93static struct clksrc_clk clk_dout_epll = {
94 .clk = {
95 .name = "dout_epll",
96 .id = -1,
97 .parent = &clk_mout_epll.clk,
98 },
99 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
100};
101
102static struct clksrc_clk clk_mout_hclk_sel = {
103 .clk = {
104 .name = "mout_hclk_sel",
105 .id = -1,
106 },
107 .sources = &clkset_hclk_low,
108 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
109};
110
111static struct clk *clkset_hclk_list[] = {
112 &clk_mout_hclk_sel.clk,
113 &clk_armclk.clk,
114};
115
116static struct clksrc_sources clkset_hclk = {
117 .sources = clkset_hclk_list,
118 .nr_sources = ARRAY_SIZE(clkset_hclk_list),
119};
120
121static struct clksrc_clk clk_hclk = {
122 .clk = {
123 .name = "clk_hclk",
124 .id = -1,
125 },
126 .sources = &clkset_hclk,
127 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
128 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
129};
130
131static struct clksrc_clk clk_pclk = {
132 .clk = {
133 .name = "clk_pclk",
134 .id = -1,
135 .parent = &clk_hclk.clk,
136 },
137 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
138};
139static struct clksrc_clk clk_dout_pwm_ratio0 = {
140 .clk = {
141 .name = "clk_dout_pwm_ratio0",
142 .id = -1,
143 .parent = &clk_mout_hclk_sel.clk,
144 },
145 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
146};
147
148static struct clksrc_clk clk_pclk_to_wdt_pwm = {
149 .clk = {
150 .name = "clk_pclk_to_wdt_pwm",
151 .id = -1,
152 .parent = &clk_dout_pwm_ratio0.clk,
153 },
154 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
155};
156
157static struct clksrc_clk clk_hclk_low = {
158 .clk = {
159 .name = "clk_hclk_low",
160 .id = -1,
161 },
162 .sources = &clkset_hclk_low,
163 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
164 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
165};
166
167static struct clksrc_clk clk_pclk_low = {
168 .clk = {
169 .name = "clk_pclk_low",
170 .id = -1,
171 .parent = &clk_hclk_low.clk,
172 },
173 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
174};
175
176/*
177 * The following clocks will be disabled during clock initialization. It is
178 * recommended to keep the following clocks disabled until the driver requests
179 * for enabling the clock.
180 */
181static struct clk init_clocks_disable[] = {
182 {
183 .name = "usbhost",
184 .id = -1,
185 .parent = &clk_hclk_low.clk,
186 .enable = s5p64x0_hclk0_ctrl,
187 .ctrlbit = (1 << 3),
188 }, {
189 .name = "hsmmc",
190 .id = 0,
191 .parent = &clk_hclk_low.clk,
192 .enable = s5p64x0_hclk0_ctrl,
193 .ctrlbit = (1 << 17),
194 }, {
195 .name = "hsmmc",
196 .id = 1,
197 .parent = &clk_hclk_low.clk,
198 .enable = s5p64x0_hclk0_ctrl,
199 .ctrlbit = (1 << 18),
200 }, {
201 .name = "hsmmc",
202 .id = 2,
203 .parent = &clk_hclk_low.clk,
204 .enable = s5p64x0_hclk0_ctrl,
205 .ctrlbit = (1 << 19),
206 }, {
207 .name = "usbotg",
208 .id = -1,
209 .parent = &clk_hclk_low.clk,
210 .enable = s5p64x0_hclk0_ctrl,
211 .ctrlbit = (1 << 20),
212 }, {
213 .name = "lcd",
214 .id = -1,
215 .parent = &clk_h,
216 .enable = s5p64x0_hclk1_ctrl,
217 .ctrlbit = (1 << 1),
218 }, {
219 .name = "watchdog",
220 .id = -1,
221 .parent = &clk_pclk_low.clk,
222 .enable = s5p64x0_pclk_ctrl,
223 .ctrlbit = (1 << 5),
224 }, {
225 .name = "adc",
226 .id = -1,
227 .parent = &clk_pclk_low.clk,
228 .enable = s5p64x0_pclk_ctrl,
229 .ctrlbit = (1 << 12),
230 }, {
231 .name = "i2c",
232 .id = 0,
233 .parent = &clk_pclk_low.clk,
234 .enable = s5p64x0_pclk_ctrl,
235 .ctrlbit = (1 << 17),
236 }, {
237 .name = "spi",
238 .id = 0,
239 .parent = &clk_pclk_low.clk,
240 .enable = s5p64x0_pclk_ctrl,
241 .ctrlbit = (1 << 21),
242 }, {
243 .name = "spi",
244 .id = 1,
245 .parent = &clk_pclk_low.clk,
246 .enable = s5p64x0_pclk_ctrl,
247 .ctrlbit = (1 << 22),
248 }, {
249 .name = "iis",
250 .id = -1,
251 .parent = &clk_pclk_low.clk,
252 .enable = s5p64x0_pclk_ctrl,
253 .ctrlbit = (1 << 26),
254 }, {
255 .name = "i2c",
256 .id = 1,
257 .parent = &clk_pclk_low.clk,
258 .enable = s5p64x0_pclk_ctrl,
259 .ctrlbit = (1 << 27),
260 }, {
261 .name = "dmc0",
262 .id = -1,
263 .parent = &clk_pclk.clk,
264 .enable = s5p64x0_pclk_ctrl,
265 .ctrlbit = (1 << 30),
266 }
267};
268
269/*
270 * The following clocks will be enabled during clock initialization.
271 */
272static struct clk init_clocks[] = {
273 {
274 .name = "intc",
275 .id = -1,
276 .parent = &clk_hclk.clk,
277 .enable = s5p64x0_hclk0_ctrl,
278 .ctrlbit = (1 << 1),
279 }, {
280 .name = "mem",
281 .id = -1,
282 .parent = &clk_hclk.clk,
283 .enable = s5p64x0_hclk0_ctrl,
284 .ctrlbit = (1 << 21),
285 }, {
286 .name = "dma",
287 .id = -1,
288 .parent = &clk_hclk_low.clk,
289 .enable = s5p64x0_hclk0_ctrl,
290 .ctrlbit = (1 << 12),
291 }, {
292 .name = "uart",
293 .id = 0,
294 .parent = &clk_pclk_low.clk,
295 .enable = s5p64x0_pclk_ctrl,
296 .ctrlbit = (1 << 1),
297 }, {
298 .name = "uart",
299 .id = 1,
300 .parent = &clk_pclk_low.clk,
301 .enable = s5p64x0_pclk_ctrl,
302 .ctrlbit = (1 << 2),
303 }, {
304 .name = "uart",
305 .id = 2,
306 .parent = &clk_pclk_low.clk,
307 .enable = s5p64x0_pclk_ctrl,
308 .ctrlbit = (1 << 3),
309 }, {
310 .name = "uart",
311 .id = 3,
312 .parent = &clk_pclk_low.clk,
313 .enable = s5p64x0_pclk_ctrl,
314 .ctrlbit = (1 << 4),
315 }, {
316 .name = "timers",
317 .id = -1,
318 .parent = &clk_pclk_to_wdt_pwm.clk,
319 .enable = s5p64x0_pclk_ctrl,
320 .ctrlbit = (1 << 7),
321 }, {
322 .name = "gpio",
323 .id = -1,
324 .parent = &clk_pclk_low.clk,
325 .enable = s5p64x0_pclk_ctrl,
326 .ctrlbit = (1 << 18),
327 },
328};
329
330static struct clk *clkset_uart_list[] = {
331 &clk_dout_epll.clk,
332 &clk_dout_mpll.clk,
333};
334
335static struct clksrc_sources clkset_uart = {
336 .sources = clkset_uart_list,
337 .nr_sources = ARRAY_SIZE(clkset_uart_list),
338};
339
340static struct clk *clkset_mali_list[] = {
341 &clk_mout_epll.clk,
342 &clk_mout_apll.clk,
343 &clk_mout_mpll.clk,
344};
345
346static struct clksrc_sources clkset_mali = {
347 .sources = clkset_mali_list,
348 .nr_sources = ARRAY_SIZE(clkset_mali_list),
349};
350
351static struct clk *clkset_group2_list[] = {
352 &clk_dout_epll.clk,
353 &clk_dout_mpll.clk,
354 &clk_ext_xtal_mux,
355};
356
357static struct clksrc_sources clkset_group2 = {
358 .sources = clkset_group2_list,
359 .nr_sources = ARRAY_SIZE(clkset_group2_list),
360};
361
362static struct clk *clkset_dispcon_list[] = {
363 &clk_dout_epll.clk,
364 &clk_dout_mpll.clk,
365 &clk_ext_xtal_mux,
366 &clk_mout_dpll.clk,
367};
368
369static struct clksrc_sources clkset_dispcon = {
370 .sources = clkset_dispcon_list,
371 .nr_sources = ARRAY_SIZE(clkset_dispcon_list),
372};
373
374static struct clk *clkset_hsmmc44_list[] = {
375 &clk_dout_epll.clk,
376 &clk_dout_mpll.clk,
377 &clk_ext_xtal_mux,
378 &s5p_clk_27m,
379 &clk_48m,
380};
381
382static struct clksrc_sources clkset_hsmmc44 = {
383 .sources = clkset_hsmmc44_list,
384 .nr_sources = ARRAY_SIZE(clkset_hsmmc44_list),
385};
386
387static struct clk *clkset_sclk_audio0_list[] = {
388 [0] = &clk_dout_epll.clk,
389 [1] = &clk_dout_mpll.clk,
390 [2] = &clk_ext_xtal_mux,
391 [3] = NULL,
392 [4] = NULL,
393};
394
395static struct clksrc_sources clkset_sclk_audio0 = {
396 .sources = clkset_sclk_audio0_list,
397 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
398};
399
400static struct clksrc_clk clk_sclk_audio0 = {
401 .clk = {
402 .name = "audio-bus",
403 .id = -1,
404 .enable = s5p64x0_sclk_ctrl,
405 .ctrlbit = (1 << 8),
406 .parent = &clk_dout_epll.clk,
407 },
408 .sources = &clkset_sclk_audio0,
409 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
410 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
411};
412
413static struct clksrc_clk clksrcs[] = {
414 {
415 .clk = {
416 .name = "sclk_mmc",
417 .id = 0,
418 .ctrlbit = (1 << 24),
419 .enable = s5p64x0_sclk_ctrl,
420 },
421 .sources = &clkset_group2,
422 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
423 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
424 }, {
425 .clk = {
426 .name = "sclk_mmc",
427 .id = 1,
428 .ctrlbit = (1 << 25),
429 .enable = s5p64x0_sclk_ctrl,
430 },
431 .sources = &clkset_group2,
432 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
433 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
434 }, {
435 .clk = {
436 .name = "sclk_mmc",
437 .id = 2,
438 .ctrlbit = (1 << 26),
439 .enable = s5p64x0_sclk_ctrl,
440 },
441 .sources = &clkset_group2,
442 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
444 }, {
445 .clk = {
446 .name = "uclk1",
447 .id = -1,
448 .ctrlbit = (1 << 5),
449 .enable = s5p64x0_sclk_ctrl,
450 },
451 .sources = &clkset_uart,
452 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
453 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
454 }, {
455 .clk = {
456 .name = "sclk_spi",
457 .id = 0,
458 .ctrlbit = (1 << 20),
459 .enable = s5p64x0_sclk_ctrl,
460 },
461 .sources = &clkset_group2,
462 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
463 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
464 }, {
465 .clk = {
466 .name = "sclk_spi",
467 .id = 1,
468 .ctrlbit = (1 << 21),
469 .enable = s5p64x0_sclk_ctrl,
470 },
471 .sources = &clkset_group2,
472 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
473 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
474 }, {
475 .clk = {
476 .name = "sclk_fimc",
477 .id = -1,
478 .ctrlbit = (1 << 10),
479 .enable = s5p64x0_sclk_ctrl,
480 },
481 .sources = &clkset_group2,
482 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
483 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
484 }, {
485 .clk = {
486 .name = "aclk_mali",
487 .id = -1,
488 .ctrlbit = (1 << 2),
489 .enable = s5p64x0_sclk1_ctrl,
490 },
491 .sources = &clkset_mali,
492 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
493 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
494 }, {
495 .clk = {
496 .name = "sclk_2d",
497 .id = -1,
498 .ctrlbit = (1 << 12),
499 .enable = s5p64x0_sclk_ctrl,
500 },
501 .sources = &clkset_mali,
502 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
503 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
504 }, {
505 .clk = {
506 .name = "sclk_usi",
507 .id = -1,
508 .ctrlbit = (1 << 7),
509 .enable = s5p64x0_sclk_ctrl,
510 },
511 .sources = &clkset_group2,
512 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
513 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
514 }, {
515 .clk = {
516 .name = "sclk_camif",
517 .id = -1,
518 .ctrlbit = (1 << 6),
519 .enable = s5p64x0_sclk_ctrl,
520 },
521 .sources = &clkset_group2,
522 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
523 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
524 }, {
525 .clk = {
526 .name = "sclk_dispcon",
527 .id = -1,
528 .ctrlbit = (1 << 1),
529 .enable = s5p64x0_sclk1_ctrl,
530 },
531 .sources = &clkset_dispcon,
532 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
533 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
534 }, {
535 .clk = {
536 .name = "sclk_hsmmc44",
537 .id = -1,
538 .ctrlbit = (1 << 30),
539 .enable = s5p64x0_sclk_ctrl,
540 },
541 .sources = &clkset_hsmmc44,
542 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
543 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
544 },
545};
546
547/* Clock initialization code */
548static struct clksrc_clk *sysclks[] = {
549 &clk_mout_apll,
550 &clk_mout_epll,
551 &clk_dout_epll,
552 &clk_mout_mpll,
553 &clk_dout_mpll,
554 &clk_armclk,
555 &clk_mout_hclk_sel,
556 &clk_dout_pwm_ratio0,
557 &clk_pclk_to_wdt_pwm,
558 &clk_hclk,
559 &clk_pclk,
560 &clk_hclk_low,
561 &clk_pclk_low,
562 &clk_sclk_audio0,
563};
564
565void __init_or_cpufreq s5p6450_setup_clocks(void)
566{
567 struct clk *xtal_clk;
568
569 unsigned long xtal;
570 unsigned long fclk;
571 unsigned long hclk;
572 unsigned long hclk_low;
573 unsigned long pclk;
574 unsigned long pclk_low;
575
576 unsigned long apll;
577 unsigned long mpll;
578 unsigned long epll;
579 unsigned long dpll;
580 unsigned int ptr;
581
582 /* Set S5P6450 functions for clk_fout_epll */
583
584 clk_fout_epll.enable = s5p64x0_epll_enable;
585 clk_fout_epll.ops = &s5p6450_epll_ops;
586
587 clk_48m.enable = s5p64x0_clk48m_ctrl;
588
589 xtal_clk = clk_get(NULL, "ext_xtal");
590 BUG_ON(IS_ERR(xtal_clk));
591
592 xtal = clk_get_rate(xtal_clk);
593 clk_put(xtal_clk);
594
595 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
596 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
597 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
598 __raw_readl(S5P64X0_EPLL_CON_K));
599 dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
600 __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
601
602 clk_fout_apll.rate = apll;
603 clk_fout_mpll.rate = mpll;
604 clk_fout_epll.rate = epll;
605 clk_fout_dpll.rate = dpll;
606
607 printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
608 " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
609 print_mhz(apll), print_mhz(mpll), print_mhz(epll),
610 print_mhz(dpll));
611
612 fclk = clk_get_rate(&clk_armclk.clk);
613 hclk = clk_get_rate(&clk_hclk.clk);
614 pclk = clk_get_rate(&clk_pclk.clk);
615 hclk_low = clk_get_rate(&clk_hclk_low.clk);
616 pclk_low = clk_get_rate(&clk_pclk_low.clk);
617
618 printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
619 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
620 print_mhz(hclk), print_mhz(hclk_low),
621 print_mhz(pclk), print_mhz(pclk_low));
622
623 clk_f.rate = fclk;
624 clk_h.rate = hclk;
625 clk_p.rate = pclk;
626
627 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
628 s3c_set_clksrc(&clksrcs[ptr], true);
629}
630
631void __init s5p6450_register_clocks(void)
632{
633 struct clk *clkp;
634 int ret;
635 int ptr;
636
637 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
638 s3c_register_clksrc(sysclks[ptr], 1);
639
640 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
641 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
642
643 clkp = init_clocks_disable;
644 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
645
646 ret = s3c24xx_register_clock(clkp);
647 if (ret < 0) {
648 printk(KERN_ERR "Failed to register clock %s (%d)\n",
649 clkp->name, ret);
650 }
651 (clkp->enable)(clkp, 0);
652 }
653
654 s3c_pwmclk_init();
655}
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
new file mode 100644
index 000000000000..523ba8039ac2
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -0,0 +1,253 @@
1/* linux/arch/arm/mach-s5p64x0/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/sysdev.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26
27#include <plat/cpu-freq.h>
28#include <plat/clock.h>
29#include <plat/cpu.h>
30#include <plat/pll.h>
31#include <plat/s5p-clock.h>
32#include <plat/clock-clksrc.h>
33#include <plat/s5p6440.h>
34#include <plat/s5p6450.h>
35
36struct clksrc_clk clk_mout_apll = {
37 .clk = {
38 .name = "mout_apll",
39 .id = -1,
40 },
41 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 },
43};
44
45struct clksrc_clk clk_mout_mpll = {
46 .clk = {
47 .name = "mout_mpll",
48 .id = -1,
49 },
50 .sources = &clk_src_mpll,
51 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 },
52};
53
54struct clksrc_clk clk_mout_epll = {
55 .clk = {
56 .name = "mout_epll",
57 .id = -1,
58 },
59 .sources = &clk_src_epll,
60 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 },
61};
62
63enum perf_level {
64 L0 = 532*1000,
65 L1 = 266*1000,
66 L2 = 133*1000,
67};
68
69static const u32 clock_table[][3] = {
70 /*{ARM_CLK, DIVarm, DIVhclk}*/
71 {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
72 {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
73 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
74};
75
76int s5p64x0_epll_enable(struct clk *clk, int enable)
77{
78 unsigned int ctrlbit = clk->ctrlbit;
79 unsigned int epll_con = __raw_readl(S5P64X0_EPLL_CON) & ~ctrlbit;
80
81 if (enable)
82 __raw_writel(epll_con | ctrlbit, S5P64X0_EPLL_CON);
83 else
84 __raw_writel(epll_con, S5P64X0_EPLL_CON);
85
86 return 0;
87}
88
89unsigned long s5p64x0_epll_get_rate(struct clk *clk)
90{
91 return clk->rate;
92}
93
94unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
95{
96 unsigned long rate = clk_get_rate(clk->parent);
97 u32 clkdiv;
98
99 /* divisor mask starts at bit0, so no need to shift */
100 clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
101
102 return rate / (clkdiv + 1);
103}
104
105unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
106{
107 u32 iter;
108
109 for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
110 if (rate > clock_table[iter][0])
111 return clock_table[iter-1][0];
112 }
113
114 return clock_table[ARRAY_SIZE(clock_table) - 1][0];
115}
116
117int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
118{
119 u32 round_tmp;
120 u32 iter;
121 u32 clk_div0_tmp;
122 u32 cur_rate = clk->ops->get_rate(clk);
123 unsigned long flags;
124
125 round_tmp = clk->ops->round_rate(clk, rate);
126 if (round_tmp == cur_rate)
127 return 0;
128
129
130 for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
131 if (round_tmp == clock_table[iter][0])
132 break;
133 }
134
135 if (iter >= ARRAY_SIZE(clock_table))
136 iter = ARRAY_SIZE(clock_table) - 1;
137
138 local_irq_save(flags);
139 if (cur_rate > round_tmp) {
140 /* Frequency Down */
141 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
142 clk_div0_tmp |= clock_table[iter][1];
143 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
144
145 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
146 ~(S5P64X0_CLKDIV0_HCLK_MASK);
147 clk_div0_tmp |= clock_table[iter][2];
148 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
149
150
151 } else {
152 /* Frequency Up */
153 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
154 ~(S5P64X0_CLKDIV0_HCLK_MASK);
155 clk_div0_tmp |= clock_table[iter][2];
156 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
157
158 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
159 clk_div0_tmp |= clock_table[iter][1];
160 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
161 }
162 local_irq_restore(flags);
163
164 clk->rate = clock_table[iter][0];
165
166 return 0;
167}
168
169struct clk_ops s5p64x0_clkarm_ops = {
170 .get_rate = s5p64x0_armclk_get_rate,
171 .set_rate = s5p64x0_armclk_set_rate,
172 .round_rate = s5p64x0_armclk_round_rate,
173};
174
175struct clksrc_clk clk_armclk = {
176 .clk = {
177 .name = "armclk",
178 .id = 1,
179 .parent = &clk_mout_apll.clk,
180 .ops = &s5p64x0_clkarm_ops,
181 },
182 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 },
183};
184
185struct clksrc_clk clk_dout_mpll = {
186 .clk = {
187 .name = "dout_mpll",
188 .id = -1,
189 .parent = &clk_mout_mpll.clk,
190 },
191 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
192};
193
194struct clk *clkset_hclk_low_list[] = {
195 &clk_mout_apll.clk,
196 &clk_mout_mpll.clk,
197};
198
199struct clksrc_sources clkset_hclk_low = {
200 .sources = clkset_hclk_low_list,
201 .nr_sources = ARRAY_SIZE(clkset_hclk_low_list),
202};
203
204int s5p64x0_pclk_ctrl(struct clk *clk, int enable)
205{
206 return s5p_gatectrl(S5P64X0_CLK_GATE_PCLK, clk, enable);
207}
208
209int s5p64x0_hclk0_ctrl(struct clk *clk, int enable)
210{
211 return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK0, clk, enable);
212}
213
214int s5p64x0_hclk1_ctrl(struct clk *clk, int enable)
215{
216 return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK1, clk, enable);
217}
218
219int s5p64x0_sclk_ctrl(struct clk *clk, int enable)
220{
221 return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK0, clk, enable);
222}
223
224int s5p64x0_sclk1_ctrl(struct clk *clk, int enable)
225{
226 return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK1, clk, enable);
227}
228
229int s5p64x0_mem_ctrl(struct clk *clk, int enable)
230{
231 return s5p_gatectrl(S5P64X0_CLK_GATE_MEM0, clk, enable);
232}
233
234int s5p64x0_clk48m_ctrl(struct clk *clk, int enable)
235{
236 unsigned long flags;
237 u32 val;
238
239 /* can't rely on clock lock, this register has other usages */
240 local_irq_save(flags);
241
242 val = __raw_readl(S5P64X0_OTHERS);
243 if (enable)
244 val |= S5P64X0_OTHERS_USB_SIG_MASK;
245 else
246 val &= ~S5P64X0_OTHERS_USB_SIG_MASK;
247
248 __raw_writel(val, S5P64X0_OTHERS);
249
250 local_irq_restore(flags);
251
252 return 0;
253}
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
new file mode 100644
index 000000000000..b8d02eb4cf30
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -0,0 +1,209 @@
1/* linux/arch/arm/mach-s5p64x0/cpu.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/sysdev.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/sched.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/mach/irq.h>
27#include <asm/proc-fns.h>
28#include <asm/irq.h>
29
30#include <mach/hardware.h>
31#include <mach/map.h>
32#include <mach/regs-clock.h>
33
34#include <plat/regs-serial.h>
35#include <plat/cpu.h>
36#include <plat/devs.h>
37#include <plat/clock.h>
38#include <plat/s5p6440.h>
39#include <plat/s5p6450.h>
40#include <plat/adc-core.h>
41
42/* Initial IO mappings */
43
44static struct map_desc s5p64x0_iodesc[] __initdata = {
45 {
46 .virtual = (unsigned long)S5P_VA_GPIO,
47 .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
48 .length = SZ_4K,
49 .type = MT_DEVICE,
50 }, {
51 .virtual = (unsigned long)VA_VIC0,
52 .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
53 .length = SZ_16K,
54 .type = MT_DEVICE,
55 }, {
56 .virtual = (unsigned long)VA_VIC1,
57 .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
58 .length = SZ_16K,
59 .type = MT_DEVICE,
60 },
61};
62
63static struct map_desc s5p6440_iodesc[] __initdata = {
64 {
65 .virtual = (unsigned long)S3C_VA_UART,
66 .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
67 .length = SZ_4K,
68 .type = MT_DEVICE,
69 },
70};
71
72static struct map_desc s5p6450_iodesc[] __initdata = {
73 {
74 .virtual = (unsigned long)S3C_VA_UART,
75 .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
76 .length = SZ_512K,
77 .type = MT_DEVICE,
78 }, {
79 .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
80 .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
81 .length = SZ_4K,
82 .type = MT_DEVICE,
83 },
84};
85
86static void s5p64x0_idle(void)
87{
88 unsigned long val;
89
90 if (!need_resched()) {
91 val = __raw_readl(S5P64X0_PWR_CFG);
92 val &= ~(0x3 << 5);
93 val |= (0x1 << 5);
94 __raw_writel(val, S5P64X0_PWR_CFG);
95
96 cpu_do_idle();
97 }
98 local_irq_enable();
99}
100
101/*
102 * s5p64x0_map_io
103 *
104 * register the standard CPU IO areas
105 */
106
107void __init s5p6440_map_io(void)
108{
109 /* initialize any device information early */
110 s3c_adc_setname("s3c64xx-adc");
111
112 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
113 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
114}
115
116void __init s5p6450_map_io(void)
117{
118 /* initialize any device information early */
119 s3c_adc_setname("s3c64xx-adc");
120
121 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
122 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6440_iodesc));
123}
124
125/*
126 * s5p64x0_init_clocks
127 *
128 * register and setup the CPU clocks
129 */
130
131void __init s5p6440_init_clocks(int xtal)
132{
133 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
134
135 s3c24xx_register_baseclocks(xtal);
136 s5p_register_clocks(xtal);
137 s5p6440_register_clocks();
138 s5p6440_setup_clocks();
139}
140
141void __init s5p6450_init_clocks(int xtal)
142{
143 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
144
145 s3c24xx_register_baseclocks(xtal);
146 s5p_register_clocks(xtal);
147 s5p6450_register_clocks();
148 s5p6450_setup_clocks();
149}
150
151/*
152 * s5p64x0_init_irq
153 *
154 * register the CPU interrupts
155 */
156
157void __init s5p6440_init_irq(void)
158{
159 /* S5P6440 supports 2 VIC */
160 u32 vic[2];
161
162 /*
163 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
164 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
165 */
166 vic[0] = 0xff800ae7;
167 vic[1] = 0xffbf23e5;
168
169 s5p_init_irq(vic, ARRAY_SIZE(vic));
170}
171
172void __init s5p6450_init_irq(void)
173{
174 /* S5P6450 supports only 2 VIC */
175 u32 vic[2];
176
177 /*
178 * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
179 * VIC1 is missing IRQ VIC1[12, 14, 23]
180 */
181 vic[0] = 0xff9f1fff;
182 vic[1] = 0xff7fafff;
183
184 s5p_init_irq(vic, ARRAY_SIZE(vic));
185}
186
187struct sysdev_class s5p64x0_sysclass = {
188 .name = "s5p64x0-core",
189};
190
191static struct sys_device s5p64x0_sysdev = {
192 .cls = &s5p64x0_sysclass,
193};
194
195static int __init s5p64x0_core_init(void)
196{
197 return sysdev_class_register(&s5p64x0_sysclass);
198}
199core_initcall(s5p64x0_core_init);
200
201int __init s5p64x0_init(void)
202{
203 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
204
205 /* set idle function */
206 pm_idle = s5p64x0_idle;
207
208 return sysdev_register(&s5p64x0_sysdev);
209}
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
new file mode 100644
index 000000000000..fa097bd68ca4
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/dev-audio.c
@@ -0,0 +1,164 @@
1/* linux/arch/arm/mach-s5p64x0/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/audio.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static int s5p6440_cfg_i2s(struct platform_device *pdev)
23{
24 /* configure GPIO for i2s port */
25 switch (pdev->id) {
26 case -1:
27 s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
28 s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
29 s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
30 s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
31 s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
32 s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
33 s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
34 break;
35
36 default:
37 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
38 return -EINVAL;
39 }
40
41 return 0;
42}
43
44static int s5p6450_cfg_i2s(struct platform_device *pdev)
45{
46 /* configure GPIO for i2s port */
47 switch (pdev->id) {
48 case -1:
49 s3c_gpio_cfgpin(S5P6450_GPB(4), S3C_GPIO_SFN(5));
50 s3c_gpio_cfgpin(S5P6450_GPR(4), S3C_GPIO_SFN(5));
51 s3c_gpio_cfgpin(S5P6450_GPR(5), S3C_GPIO_SFN(5));
52 s3c_gpio_cfgpin(S5P6450_GPR(6), S3C_GPIO_SFN(5));
53 s3c_gpio_cfgpin(S5P6450_GPR(7), S3C_GPIO_SFN(5));
54 s3c_gpio_cfgpin(S5P6450_GPR(8), S3C_GPIO_SFN(5));
55 s3c_gpio_cfgpin(S5P6450_GPR(13), S3C_GPIO_SFN(5));
56 s3c_gpio_cfgpin(S5P6450_GPR(14), S3C_GPIO_SFN(5));
57 break;
58
59 default:
60 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
61 return -EINVAL;
62 }
63
64 return 0;
65}
66
67static struct s3c_audio_pdata s5p6440_i2s_pdata = {
68 .cfg_gpio = s5p6440_cfg_i2s,
69};
70
71static struct s3c_audio_pdata s5p6450_i2s_pdata = {
72 .cfg_gpio = s5p6450_cfg_i2s,
73};
74
75static struct resource s5p64x0_iis0_resource[] = {
76 [0] = {
77 .start = S5P64X0_PA_I2S,
78 .end = S5P64X0_PA_I2S + 0x100 - 1,
79 .flags = IORESOURCE_MEM,
80 },
81 [1] = {
82 .start = DMACH_I2S0_TX,
83 .end = DMACH_I2S0_TX,
84 .flags = IORESOURCE_DMA,
85 },
86 [2] = {
87 .start = DMACH_I2S0_RX,
88 .end = DMACH_I2S0_RX,
89 .flags = IORESOURCE_DMA,
90 },
91};
92
93struct platform_device s5p6440_device_iis = {
94 .name = "s3c64xx-iis-v4",
95 .id = -1,
96 .num_resources = ARRAY_SIZE(s5p64x0_iis0_resource),
97 .resource = s5p64x0_iis0_resource,
98 .dev = {
99 .platform_data = &s5p6440_i2s_pdata,
100 },
101};
102
103struct platform_device s5p6450_device_iis0 = {
104 .name = "s3c64xx-iis-v4",
105 .id = -1,
106 .num_resources = ARRAY_SIZE(s5p64x0_iis0_resource),
107 .resource = s5p64x0_iis0_resource,
108 .dev = {
109 .platform_data = &s5p6450_i2s_pdata,
110 },
111};
112
113/* PCM Controller platform_devices */
114
115static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
116{
117 switch (pdev->id) {
118 case 0:
119 s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
120 s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
121 s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
122 s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
123 s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
124 break;
125
126 default:
127 printk(KERN_DEBUG "Invalid PCM Controller number!");
128 return -EINVAL;
129 }
130
131 return 0;
132}
133
134static struct s3c_audio_pdata s5p6440_pcm_pdata = {
135 .cfg_gpio = s5p6440_pcm_cfg_gpio,
136};
137
138static struct resource s5p6440_pcm0_resource[] = {
139 [0] = {
140 .start = S5P64X0_PA_PCM,
141 .end = S5P64X0_PA_PCM + 0x100 - 1,
142 .flags = IORESOURCE_MEM,
143 },
144 [1] = {
145 .start = DMACH_PCM0_TX,
146 .end = DMACH_PCM0_TX,
147 .flags = IORESOURCE_DMA,
148 },
149 [2] = {
150 .start = DMACH_PCM0_RX,
151 .end = DMACH_PCM0_RX,
152 .flags = IORESOURCE_DMA,
153 },
154};
155
156struct platform_device s5p6440_device_pcm = {
157 .name = "samsung-pcm",
158 .id = 0,
159 .num_resources = ARRAY_SIZE(s5p6440_pcm0_resource),
160 .resource = s5p6440_pcm0_resource,
161 .dev = {
162 .platform_data = &s5p6440_pcm_pdata,
163 },
164};
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
new file mode 100644
index 000000000000..5b69ec4c8af3
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -0,0 +1,232 @@
1/* linux/arch/arm/mach-s5p64x0/dev-spi.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17
18#include <mach/dma.h>
19#include <mach/map.h>
20#include <mach/irqs.h>
21#include <mach/regs-clock.h>
22#include <mach/spi-clocks.h>
23
24#include <plat/s3c64xx-spi.h>
25#include <plat/gpio-cfg.h>
26
27static char *s5p64x0_spi_src_clks[] = {
28 [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
29 [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
30};
31
32/* SPI Controller platform_devices */
33
34/* Since we emulate multi-cs capability, we do not touch the CS.
35 * The emulated CS is toggled by board specific mechanism, as it can
36 * be either some immediate GPIO or some signal out of some other
37 * chip in between ... or some yet another way.
38 * We simply do not assume anything about CS.
39 */
40static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
41{
42 switch (pdev->id) {
43 case 0:
44 s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
45 s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
46 s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
47 s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
48 s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
49 s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
50 break;
51
52 case 1:
53 s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
54 s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
55 s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
56 s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
57 s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
58 s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
59 break;
60
61 default:
62 dev_err(&pdev->dev, "Invalid SPI Controller number!");
63 return -EINVAL;
64 }
65
66 return 0;
67}
68
69static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
70{
71 switch (pdev->id) {
72 case 0:
73 s3c_gpio_cfgpin(S5P6450_GPC(0), S3C_GPIO_SFN(2));
74 s3c_gpio_cfgpin(S5P6450_GPC(1), S3C_GPIO_SFN(2));
75 s3c_gpio_cfgpin(S5P6450_GPC(2), S3C_GPIO_SFN(2));
76 s3c_gpio_setpull(S5P6450_GPC(0), S3C_GPIO_PULL_UP);
77 s3c_gpio_setpull(S5P6450_GPC(1), S3C_GPIO_PULL_UP);
78 s3c_gpio_setpull(S5P6450_GPC(2), S3C_GPIO_PULL_UP);
79 break;
80
81 case 1:
82 s3c_gpio_cfgpin(S5P6450_GPC(4), S3C_GPIO_SFN(2));
83 s3c_gpio_cfgpin(S5P6450_GPC(5), S3C_GPIO_SFN(2));
84 s3c_gpio_cfgpin(S5P6450_GPC(6), S3C_GPIO_SFN(2));
85 s3c_gpio_setpull(S5P6450_GPC(4), S3C_GPIO_PULL_UP);
86 s3c_gpio_setpull(S5P6450_GPC(5), S3C_GPIO_PULL_UP);
87 s3c_gpio_setpull(S5P6450_GPC(6), S3C_GPIO_PULL_UP);
88 break;
89
90 default:
91 dev_err(&pdev->dev, "Invalid SPI Controller number!");
92 return -EINVAL;
93 }
94
95 return 0;
96}
97
98static struct resource s5p64x0_spi0_resource[] = {
99 [0] = {
100 .start = S5P64X0_PA_SPI0,
101 .end = S5P64X0_PA_SPI0 + 0x100 - 1,
102 .flags = IORESOURCE_MEM,
103 },
104 [1] = {
105 .start = DMACH_SPI0_TX,
106 .end = DMACH_SPI0_TX,
107 .flags = IORESOURCE_DMA,
108 },
109 [2] = {
110 .start = DMACH_SPI0_RX,
111 .end = DMACH_SPI0_RX,
112 .flags = IORESOURCE_DMA,
113 },
114 [3] = {
115 .start = IRQ_SPI0,
116 .end = IRQ_SPI0,
117 .flags = IORESOURCE_IRQ,
118 },
119};
120
121static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
122 .cfg_gpio = s5p6440_spi_cfg_gpio,
123 .fifo_lvl_mask = 0x1ff,
124 .rx_lvl_offset = 15,
125};
126
127static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
128 .cfg_gpio = s5p6450_spi_cfg_gpio,
129 .fifo_lvl_mask = 0x1ff,
130 .rx_lvl_offset = 15,
131};
132
133static u64 spi_dmamask = DMA_BIT_MASK(32);
134
135struct platform_device s5p64x0_device_spi0 = {
136 .name = "s3c64xx-spi",
137 .id = 0,
138 .num_resources = ARRAY_SIZE(s5p64x0_spi0_resource),
139 .resource = s5p64x0_spi0_resource,
140 .dev = {
141 .dma_mask = &spi_dmamask,
142 .coherent_dma_mask = DMA_BIT_MASK(32),
143 },
144};
145
146static struct resource s5p64x0_spi1_resource[] = {
147 [0] = {
148 .start = S5P64X0_PA_SPI1,
149 .end = S5P64X0_PA_SPI1 + 0x100 - 1,
150 .flags = IORESOURCE_MEM,
151 },
152 [1] = {
153 .start = DMACH_SPI1_TX,
154 .end = DMACH_SPI1_TX,
155 .flags = IORESOURCE_DMA,
156 },
157 [2] = {
158 .start = DMACH_SPI1_RX,
159 .end = DMACH_SPI1_RX,
160 .flags = IORESOURCE_DMA,
161 },
162 [3] = {
163 .start = IRQ_SPI1,
164 .end = IRQ_SPI1,
165 .flags = IORESOURCE_IRQ,
166 },
167};
168
169static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
170 .cfg_gpio = s5p6440_spi_cfg_gpio,
171 .fifo_lvl_mask = 0x7f,
172 .rx_lvl_offset = 15,
173};
174
175static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
176 .cfg_gpio = s5p6450_spi_cfg_gpio,
177 .fifo_lvl_mask = 0x7f,
178 .rx_lvl_offset = 15,
179};
180
181struct platform_device s5p64x0_device_spi1 = {
182 .name = "s3c64xx-spi",
183 .id = 1,
184 .num_resources = ARRAY_SIZE(s5p64x0_spi1_resource),
185 .resource = s5p64x0_spi1_resource,
186 .dev = {
187 .dma_mask = &spi_dmamask,
188 .coherent_dma_mask = DMA_BIT_MASK(32),
189 },
190};
191
192void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
193{
194 unsigned int id;
195 struct s3c64xx_spi_info *pd;
196
197 id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
198
199 /* Reject invalid configuration */
200 if (!num_cs || src_clk_nr < 0
201 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
202 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
203 return;
204 }
205
206 switch (cntrlr) {
207 case 0:
208 if (id == 0x50000)
209 pd = &s5p6450_spi0_pdata;
210 else
211 pd = &s5p6440_spi0_pdata;
212
213 s5p64x0_device_spi0.dev.platform_data = pd;
214 break;
215 case 1:
216 if (id == 0x50000)
217 pd = &s5p6450_spi1_pdata;
218 else
219 pd = &s5p6440_spi1_pdata;
220
221 s5p64x0_device_spi1.dev.platform_data = pd;
222 break;
223 default:
224 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
225 __func__, cntrlr);
226 return;
227 }
228
229 pd->num_cs = num_cs;
230 pd->src_clk_nr = src_clk_nr;
231 pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
232}
diff --git a/arch/arm/mach-s5p6440/dma.c b/arch/arm/mach-s5p64x0/dma.c
index 07606ad57519..29a8c2410049 100644
--- a/arch/arm/mach-s5p6440/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -1,4 +1,8 @@
1/* 1/* linux/arch/arm/mach-s5p64x0/dma.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd. 6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com> 7 * Jaswinder Singh <jassi.brar@samsung.com>
4 * 8 *
@@ -15,26 +19,25 @@
15 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */ 22*/
19 23
20#include <linux/platform_device.h> 24#include <linux/platform_device.h>
21#include <linux/dma-mapping.h> 25#include <linux/dma-mapping.h>
22 26
23#include <plat/devs.h>
24#include <plat/irqs.h>
25
26#include <mach/map.h> 27#include <mach/map.h>
27#include <mach/irqs.h> 28#include <mach/irqs.h>
29#include <mach/regs-clock.h>
28 30
31#include <plat/devs.h>
29#include <plat/s3c-pl330-pdata.h> 32#include <plat/s3c-pl330-pdata.h>
30 33
31static u64 dma_dmamask = DMA_BIT_MASK(32); 34static u64 dma_dmamask = DMA_BIT_MASK(32);
32 35
33static struct resource s5p6440_pdma_resource[] = { 36static struct resource s5p64x0_pdma_resource[] = {
34 [0] = { 37 [0] = {
35 .start = S5P6440_PA_PDMA, 38 .start = S5P64X0_PA_PDMA,
36 .end = S5P6440_PA_PDMA + SZ_4K, 39 .end = S5P64X0_PA_PDMA + SZ_4K,
37 .flags = IORESOURCE_MEM, 40 .flags = IORESOURCE_MEM,
38 }, 41 },
39 [1] = { 42 [1] = {
40 .start = IRQ_DMA0, 43 .start = IRQ_DMA0,
@@ -80,26 +83,67 @@ static struct s3c_pl330_platdata s5p6440_pdma_pdata = {
80 }, 83 },
81}; 84};
82 85
83static struct platform_device s5p6440_device_pdma = { 86static struct s3c_pl330_platdata s5p6450_pdma_pdata = {
87 .peri = {
88 [0] = DMACH_UART0_RX,
89 [1] = DMACH_UART0_TX,
90 [2] = DMACH_UART1_RX,
91 [3] = DMACH_UART1_TX,
92 [4] = DMACH_UART2_RX,
93 [5] = DMACH_UART2_TX,
94 [6] = DMACH_UART3_RX,
95 [7] = DMACH_UART3_TX,
96 [8] = DMACH_UART4_RX,
97 [9] = DMACH_UART4_TX,
98 [10] = DMACH_PCM0_TX,
99 [11] = DMACH_PCM0_RX,
100 [12] = DMACH_I2S0_TX,
101 [13] = DMACH_I2S0_RX,
102 [14] = DMACH_SPI0_TX,
103 [15] = DMACH_SPI0_RX,
104 [16] = DMACH_PCM1_TX,
105 [17] = DMACH_PCM1_RX,
106 [18] = DMACH_PCM2_TX,
107 [19] = DMACH_PCM2_RX,
108 [20] = DMACH_SPI1_TX,
109 [21] = DMACH_SPI1_RX,
110 [22] = DMACH_USI_TX,
111 [23] = DMACH_USI_RX,
112 [24] = DMACH_MAX,
113 [25] = DMACH_I2S1_TX,
114 [26] = DMACH_I2S1_RX,
115 [27] = DMACH_I2S2_TX,
116 [28] = DMACH_I2S2_RX,
117 [29] = DMACH_PWM,
118 [30] = DMACH_UART5_RX,
119 [31] = DMACH_UART5_TX,
120 },
121};
122
123static struct platform_device s5p64x0_device_pdma = {
84 .name = "s3c-pl330", 124 .name = "s3c-pl330",
85 .id = 1, 125 .id = 0,
86 .num_resources = ARRAY_SIZE(s5p6440_pdma_resource), 126 .num_resources = ARRAY_SIZE(s5p64x0_pdma_resource),
87 .resource = s5p6440_pdma_resource, 127 .resource = s5p64x0_pdma_resource,
88 .dev = { 128 .dev = {
89 .dma_mask = &dma_dmamask, 129 .dma_mask = &dma_dmamask,
90 .coherent_dma_mask = DMA_BIT_MASK(32), 130 .coherent_dma_mask = DMA_BIT_MASK(32),
91 .platform_data = &s5p6440_pdma_pdata,
92 }, 131 },
93}; 132};
94 133
95static struct platform_device *s5p6440_dmacs[] __initdata = { 134static int __init s5p64x0_dma_init(void)
96 &s5p6440_device_pdma,
97};
98
99static int __init s5p6440_dma_init(void)
100{ 135{
101 platform_add_devices(s5p6440_dmacs, ARRAY_SIZE(s5p6440_dmacs)); 136 unsigned int id;
137
138 id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
139
140 if (id == 0x50000)
141 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
142 else
143 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
144
145 platform_device_register(&s5p64x0_device_pdma);
102 146
103 return 0; 147 return 0;
104} 148}
105arch_initcall(s5p6440_dma_init); 149arch_initcall(s5p64x0_dma_init);
diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p64x0/gpio.c
index 8bf6e0ce51c9..39159dd5a29a 100644
--- a/arch/arm/mach-s5p6440/gpio.c
+++ b/arch/arm/mach-s5p64x0/gpio.c
@@ -1,14 +1,14 @@
1/* arch/arm/mach-s5p6440/gpio.c 1/* linux/arch/arm/mach-s5p64x0/gpio.c
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - GPIOlib support 6 * S5P64X0 - GPIOlib support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11*/
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/irq.h> 14#include <linux/irq.h>
@@ -22,26 +22,29 @@
22#include <plat/gpio-cfg.h> 22#include <plat/gpio-cfg.h>
23#include <plat/gpio-cfg-helpers.h> 23#include <plat/gpio-cfg-helpers.h>
24 24
25/* GPIO bank summary: 25/* To be implemented S5P6450 GPIO */
26* 26
27* Bank GPIOs Style SlpCon ExtInt Group 27/*
28* A 6 4Bit Yes 1 28 * S5P6440 GPIO bank summary:
29* B 7 4Bit Yes 1 29 *
30* C 8 4Bit Yes 2 30 * Bank GPIOs Style SlpCon ExtInt Group
31* F 2 2Bit Yes 4 [1] 31 * A 6 4Bit Yes 1
32* G 7 4Bit Yes 5 32 * B 7 4Bit Yes 1
33* H 10 4Bit[2] Yes 6 33 * C 8 4Bit Yes 2
34* I 16 2Bit Yes None 34 * F 2 2Bit Yes 4 [1]
35* J 12 2Bit Yes None 35 * G 7 4Bit Yes 5
36* N 16 2Bit No IRQ_EINT 36 * H 10 4Bit[2] Yes 6
37* P 8 2Bit Yes 8 37 * I 16 2Bit Yes None
38* R 15 4Bit[2] Yes 8 38 * J 12 2Bit Yes None
39* 39 * N 16 2Bit No IRQ_EINT
40* [1] BANKF pins 14,15 do not form part of the external interrupt sources 40 * P 8 2Bit Yes 8
41* [2] BANK has two control registers, GPxCON0 and GPxCON1 41 * R 15 4Bit[2] Yes 8
42*/ 42 *
43 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
44 * [2] BANK has two control registers, GPxCON0 and GPxCON1
45 */
43 46
44static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip, 47static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
45 unsigned int offset) 48 unsigned int offset)
46{ 49{
47 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); 50 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
@@ -77,7 +80,7 @@ static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
77 return 0; 80 return 0;
78} 81}
79 82
80static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, 83static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
81 unsigned int offset, int value) 84 unsigned int offset, int value)
82{ 85{
83 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); 86 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
@@ -124,12 +127,11 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
124 return 0; 127 return 0;
125} 128}
126 129
127int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip, 130int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
128 unsigned int off, unsigned int cfg) 131 unsigned int off, unsigned int cfg)
129{ 132{
130 void __iomem *reg = chip->base; 133 void __iomem *reg = chip->base;
131 unsigned int shift; 134 unsigned int shift;
132 unsigned long flags;
133 u32 con; 135 u32 con;
134 136
135 switch (off) { 137 switch (off) {
@@ -155,26 +157,22 @@ int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
155 cfg <<= shift; 157 cfg <<= shift;
156 } 158 }
157 159
158 s3c_gpio_lock(chip, flags);
159
160 con = __raw_readl(reg); 160 con = __raw_readl(reg);
161 con &= ~(0xf << shift); 161 con &= ~(0xf << shift);
162 con |= cfg; 162 con |= cfg;
163 __raw_writel(con, reg); 163 __raw_writel(con, reg);
164 164
165 s3c_gpio_unlock(chip, flags);
166
167 return 0; 165 return 0;
168} 166}
169 167
170static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = { 168static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
171 { 169 {
172 .cfg_eint = 0, 170 .cfg_eint = 0,
173 }, { 171 }, {
174 .cfg_eint = 7, 172 .cfg_eint = 7,
175 }, { 173 }, {
176 .cfg_eint = 3, 174 .cfg_eint = 3,
177 .set_config = s5p6440_gpio_setcfg_4bit_rbank, 175 .set_config = s5p64x0_gpio_setcfg_4bit_rbank,
178 }, { 176 }, {
179 .cfg_eint = 0, 177 .cfg_eint = 0,
180 .set_config = s3c_gpio_setcfg_s3c24xx, 178 .set_config = s3c_gpio_setcfg_s3c24xx,
@@ -193,7 +191,7 @@ static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
193static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { 191static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
194 { 192 {
195 .base = S5P6440_GPA_BASE, 193 .base = S5P6440_GPA_BASE,
196 .config = &s5p6440_gpio_cfgs[1], 194 .config = &s5p64x0_gpio_cfgs[1],
197 .chip = { 195 .chip = {
198 .base = S5P6440_GPA(0), 196 .base = S5P6440_GPA(0),
199 .ngpio = S5P6440_GPIO_A_NR, 197 .ngpio = S5P6440_GPIO_A_NR,
@@ -201,7 +199,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
201 }, 199 },
202 }, { 200 }, {
203 .base = S5P6440_GPB_BASE, 201 .base = S5P6440_GPB_BASE,
204 .config = &s5p6440_gpio_cfgs[1], 202 .config = &s5p64x0_gpio_cfgs[1],
205 .chip = { 203 .chip = {
206 .base = S5P6440_GPB(0), 204 .base = S5P6440_GPB(0),
207 .ngpio = S5P6440_GPIO_B_NR, 205 .ngpio = S5P6440_GPIO_B_NR,
@@ -209,7 +207,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
209 }, 207 },
210 }, { 208 }, {
211 .base = S5P6440_GPC_BASE, 209 .base = S5P6440_GPC_BASE,
212 .config = &s5p6440_gpio_cfgs[1], 210 .config = &s5p64x0_gpio_cfgs[1],
213 .chip = { 211 .chip = {
214 .base = S5P6440_GPC(0), 212 .base = S5P6440_GPC(0),
215 .ngpio = S5P6440_GPIO_C_NR, 213 .ngpio = S5P6440_GPIO_C_NR,
@@ -217,7 +215,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
217 }, 215 },
218 }, { 216 }, {
219 .base = S5P6440_GPG_BASE, 217 .base = S5P6440_GPG_BASE,
220 .config = &s5p6440_gpio_cfgs[1], 218 .config = &s5p64x0_gpio_cfgs[1],
221 .chip = { 219 .chip = {
222 .base = S5P6440_GPG(0), 220 .base = S5P6440_GPG(0),
223 .ngpio = S5P6440_GPIO_G_NR, 221 .ngpio = S5P6440_GPIO_G_NR,
@@ -229,7 +227,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
229static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { 227static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
230 { 228 {
231 .base = S5P6440_GPH_BASE + 0x4, 229 .base = S5P6440_GPH_BASE + 0x4,
232 .config = &s5p6440_gpio_cfgs[1], 230 .config = &s5p64x0_gpio_cfgs[1],
233 .chip = { 231 .chip = {
234 .base = S5P6440_GPH(0), 232 .base = S5P6440_GPH(0),
235 .ngpio = S5P6440_GPIO_H_NR, 233 .ngpio = S5P6440_GPIO_H_NR,
@@ -238,10 +236,10 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
238 }, 236 },
239}; 237};
240 238
241static struct s3c_gpio_chip gpio_rbank_4bit2[] = { 239static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
242 { 240 {
243 .base = S5P6440_GPR_BASE + 0x4, 241 .base = S5P6440_GPR_BASE + 0x4,
244 .config = &s5p6440_gpio_cfgs[2], 242 .config = &s5p64x0_gpio_cfgs[2],
245 .chip = { 243 .chip = {
246 .base = S5P6440_GPR(0), 244 .base = S5P6440_GPR(0),
247 .ngpio = S5P6440_GPIO_R_NR, 245 .ngpio = S5P6440_GPIO_R_NR,
@@ -253,7 +251,7 @@ static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
253static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { 251static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
254 { 252 {
255 .base = S5P6440_GPF_BASE, 253 .base = S5P6440_GPF_BASE,
256 .config = &s5p6440_gpio_cfgs[5], 254 .config = &s5p64x0_gpio_cfgs[5],
257 .chip = { 255 .chip = {
258 .base = S5P6440_GPF(0), 256 .base = S5P6440_GPF(0),
259 .ngpio = S5P6440_GPIO_F_NR, 257 .ngpio = S5P6440_GPIO_F_NR,
@@ -261,7 +259,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
261 }, 259 },
262 }, { 260 }, {
263 .base = S5P6440_GPI_BASE, 261 .base = S5P6440_GPI_BASE,
264 .config = &s5p6440_gpio_cfgs[3], 262 .config = &s5p64x0_gpio_cfgs[3],
265 .chip = { 263 .chip = {
266 .base = S5P6440_GPI(0), 264 .base = S5P6440_GPI(0),
267 .ngpio = S5P6440_GPIO_I_NR, 265 .ngpio = S5P6440_GPIO_I_NR,
@@ -269,7 +267,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
269 }, 267 },
270 }, { 268 }, {
271 .base = S5P6440_GPJ_BASE, 269 .base = S5P6440_GPJ_BASE,
272 .config = &s5p6440_gpio_cfgs[3], 270 .config = &s5p64x0_gpio_cfgs[3],
273 .chip = { 271 .chip = {
274 .base = S5P6440_GPJ(0), 272 .base = S5P6440_GPJ(0),
275 .ngpio = S5P6440_GPIO_J_NR, 273 .ngpio = S5P6440_GPIO_J_NR,
@@ -277,7 +275,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
277 }, 275 },
278 }, { 276 }, {
279 .base = S5P6440_GPN_BASE, 277 .base = S5P6440_GPN_BASE,
280 .config = &s5p6440_gpio_cfgs[4], 278 .config = &s5p64x0_gpio_cfgs[4],
281 .chip = { 279 .chip = {
282 .base = S5P6440_GPN(0), 280 .base = S5P6440_GPN(0),
283 .ngpio = S5P6440_GPIO_N_NR, 281 .ngpio = S5P6440_GPIO_N_NR,
@@ -285,7 +283,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
285 }, 283 },
286 }, { 284 }, {
287 .base = S5P6440_GPP_BASE, 285 .base = S5P6440_GPP_BASE,
288 .config = &s5p6440_gpio_cfgs[5], 286 .config = &s5p64x0_gpio_cfgs[5],
289 .chip = { 287 .chip = {
290 .base = S5P6440_GPP(0), 288 .base = S5P6440_GPP(0),
291 .ngpio = S5P6440_GPIO_P_NR, 289 .ngpio = S5P6440_GPIO_P_NR,
@@ -294,7 +292,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
294 }, 292 },
295}; 293};
296 294
297void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips) 295void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
298{ 296{
299 for (; nr_chips > 0; nr_chips--, chipcfg++) { 297 for (; nr_chips > 0; nr_chips--, chipcfg++) {
300 if (!chipcfg->set_config) 298 if (!chipcfg->set_config)
@@ -308,13 +306,13 @@ void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
308 } 306 }
309} 307}
310 308
311static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip, 309static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
312 int nr_chips) 310 int nr_chips)
313{ 311{
314 for (; nr_chips > 0; nr_chips--, chip++) { 312 for (; nr_chips > 0; nr_chips--, chip++) {
315 chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input; 313 chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
316 chip->chip.direction_output = 314 chip->chip.direction_output =
317 s5p6440_gpiolib_rbank_4bit2_output; 315 s5p64x0_gpiolib_rbank_4bit2_output;
318 s3c_gpiolib_add(chip); 316 s3c_gpiolib_add(chip);
319 } 317 }
320} 318}
@@ -324,8 +322,8 @@ static int __init s5p6440_gpiolib_init(void)
324 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit; 322 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
325 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit); 323 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
326 324
327 s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs, 325 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
328 ARRAY_SIZE(s5p6440_gpio_cfgs)); 326 ARRAY_SIZE(s5p64x0_gpio_cfgs));
329 327
330 for (; nr_chips > 0; nr_chips--, chips++) 328 for (; nr_chips > 0; nr_chips--, chips++)
331 s3c_gpiolib_add(chips); 329 s3c_gpiolib_add(chips);
@@ -336,8 +334,8 @@ static int __init s5p6440_gpiolib_init(void)
336 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, 334 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
337 ARRAY_SIZE(s5p6440_gpio_4bit2)); 335 ARRAY_SIZE(s5p6440_gpio_4bit2));
338 336
339 s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2, 337 s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
340 ARRAY_SIZE(gpio_rbank_4bit2)); 338 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
341 339
342 return 0; 340 return 0;
343} 341}
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
new file mode 100644
index 000000000000..79b04e6a6f8e
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
@@ -0,0 +1,33 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/* pull in the relevant register and map files. */
12
13#include <plat/map-base.h>
14#include <plat/map-s5p.h>
15
16#include <plat/regs-serial.h>
17
18 .macro addruart, rp, rv
19 mov \rp, #0xE0000000
20 orr \rp, \rp, #0x00100000
21 ldr \rp, [\rp, #0x118 ]
22 and \rp, \rp, #0xff000
23 teq \rp, #0x50000 @@ S5P6450
24 ldreq \rp, =0xEC800000
25 movne \rp, #0xEC000000 @@ S5P6440
26 ldrne \rv, = S3C_VA_UART
27#if CONFIG_DEBUG_S3C_UART != 0
28 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
29 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
30#endif
31 .endm
32
33#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5p6440/include/mach/dma.h b/arch/arm/mach-s5p64x0/include/mach/dma.h
index 81209eb1409b..81209eb1409b 100644
--- a/arch/arm/mach-s5p6440/include/mach/dma.h
+++ b/arch/arm/mach-s5p64x0/include/mach/dma.h
diff --git a/arch/arm/mach-s5p6440/include/mach/entry-macro.S b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
index e65f1b967262..10b62b4f8211 100644
--- a/arch/arm/mach-s5p6440/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/entry-macro.S 1/* linux/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Low-level IRQ helper macros for the Samsung S5P6440 6 * Low-level IRQ helper macros for the Samsung S5P64X0
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h
new file mode 100644
index 000000000000..5486c8f01f1d
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/gpio.h
@@ -0,0 +1,139 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* GPIO bank sizes */
22
23#define S5P6440_GPIO_A_NR (6)
24#define S5P6440_GPIO_B_NR (7)
25#define S5P6440_GPIO_C_NR (8)
26#define S5P6440_GPIO_F_NR (2)
27#define S5P6440_GPIO_G_NR (7)
28#define S5P6440_GPIO_H_NR (10)
29#define S5P6440_GPIO_I_NR (16)
30#define S5P6440_GPIO_J_NR (12)
31#define S5P6440_GPIO_N_NR (16)
32#define S5P6440_GPIO_P_NR (8)
33#define S5P6440_GPIO_R_NR (15)
34
35#define S5P6450_GPIO_A_NR (6)
36#define S5P6450_GPIO_B_NR (7)
37#define S5P6450_GPIO_C_NR (8)
38#define S5P6450_GPIO_D_NR (8)
39#define S5P6450_GPIO_F_NR (2)
40#define S5P6450_GPIO_G_NR (14)
41#define S5P6450_GPIO_H_NR (10)
42#define S5P6450_GPIO_I_NR (16)
43#define S5P6450_GPIO_J_NR (12)
44#define S5P6450_GPIO_K_NR (5)
45#define S5P6450_GPIO_N_NR (16)
46#define S5P6450_GPIO_P_NR (11)
47#define S5P6450_GPIO_Q_NR (14)
48#define S5P6450_GPIO_R_NR (15)
49#define S5P6450_GPIO_S_NR (8)
50
51/* GPIO bank numbers */
52
53/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
54 * space for debugging purposes so that any accidental
55 * change from one gpio bank to another can be caught.
56*/
57
58#define S5P64X0_GPIO_NEXT(__gpio) \
59 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
60
61enum s5p6440_gpio_number {
62 S5P6440_GPIO_A_START = 0,
63 S5P6440_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A),
64 S5P6440_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B),
65 S5P6440_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C),
66 S5P6440_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F),
67 S5P6440_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G),
68 S5P6440_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H),
69 S5P6440_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I),
70 S5P6440_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J),
71 S5P6440_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N),
72 S5P6440_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P),
73};
74
75enum s5p6450_gpio_number {
76 S5P6450_GPIO_A_START = 0,
77 S5P6450_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A),
78 S5P6450_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B),
79 S5P6450_GPIO_D_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C),
80 S5P6450_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D),
81 S5P6450_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F),
82 S5P6450_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G),
83 S5P6450_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H),
84 S5P6450_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I),
85 S5P6450_GPIO_K_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J),
86 S5P6450_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K),
87 S5P6450_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N),
88 S5P6450_GPIO_Q_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P),
89 S5P6450_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q),
90 S5P6450_GPIO_S_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R),
91};
92
93/* GPIO number definitions */
94
95#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
96#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
97#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
98#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
99#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
100#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
101#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
102#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
103#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
104#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
105#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
106
107#define S5P6450_GPA(_nr) (S5P6450_GPIO_A_START + (_nr))
108#define S5P6450_GPB(_nr) (S5P6450_GPIO_B_START + (_nr))
109#define S5P6450_GPC(_nr) (S5P6450_GPIO_C_START + (_nr))
110#define S5P6450_GPD(_nr) (S5P6450_GPIO_D_START + (_nr))
111#define S5P6450_GPF(_nr) (S5P6450_GPIO_F_START + (_nr))
112#define S5P6450_GPG(_nr) (S5P6450_GPIO_G_START + (_nr))
113#define S5P6450_GPH(_nr) (S5P6450_GPIO_H_START + (_nr))
114#define S5P6450_GPI(_nr) (S5P6450_GPIO_I_START + (_nr))
115#define S5P6450_GPJ(_nr) (S5P6450_GPIO_J_START + (_nr))
116#define S5P6450_GPK(_nr) (S5P6450_GPIO_K_START + (_nr))
117#define S5P6450_GPN(_nr) (S5P6450_GPIO_N_START + (_nr))
118#define S5P6450_GPP(_nr) (S5P6450_GPIO_P_START + (_nr))
119#define S5P6450_GPQ(_nr) (S5P6450_GPIO_Q_START + (_nr))
120#define S5P6450_GPR(_nr) (S5P6450_GPIO_R_START + (_nr))
121#define S5P6450_GPS(_nr) (S5P6450_GPIO_S_START + (_nr))
122
123/* the end of the S5P64X0 specific gpios */
124
125#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
126#define S5P6450_GPIO_END (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1)
127
128#define S5P64X0_GPIO_END (S5P6440_GPIO_END > S5P6450_GPIO_END ? \
129 S5P6440_GPIO_END : S5P6450_GPIO_END)
130
131#define S3C_GPIO_END S5P64X0_GPIO_END
132
133/* define the number of gpios we need to the one after the last GPIO range */
134
135#define ARCH_NR_GPIOS (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA)
136
137#include <asm-generic/gpio.h>
138
139#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/hardware.h b/arch/arm/mach-s5p64x0/include/mach/hardware.h
index be8b26e875db..d3e87996dd9a 100644
--- a/arch/arm/mach-s5p6440/include/mach/hardware.h
+++ b/arch/arm/mach-s5p64x0/include/mach/hardware.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/hardware.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/hardware.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - Hardware support 6 * S5P64X0 - Hardware support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/i2c.h b/arch/arm/mach-s5p64x0/include/mach/i2c.h
new file mode 100644
index 000000000000..887d25209e8e
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/i2c.h
@@ -0,0 +1,17 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/i2c.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 I2C configuration
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13extern void s5p6440_i2c0_cfg_gpio(struct platform_device *dev);
14extern void s5p6440_i2c1_cfg_gpio(struct platform_device *dev);
15
16extern void s5p6450_i2c0_cfg_gpio(struct platform_device *dev);
17extern void s5p6450_i2c1_cfg_gpio(struct platform_device *dev);
diff --git a/arch/arm/mach-s5p64x0/include/mach/io.h b/arch/arm/mach-s5p64x0/include/mach/io.h
new file mode 100644
index 000000000000..a3e095c02fb5
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/io.h
@@ -0,0 +1,25 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/io.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben-linux@fluff.org>
8 *
9 * Default IO routines for S5P64X0 based
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#ifndef __ASM_ARM_ARCH_IO_H
17#define __ASM_ARM_ARCH_IO_H
18
19/* No current ISA/PCI bus support. */
20#define __io(a) __typesafe_io(a)
21#define __mem_pci(a) (a)
22
23#define IO_SPACE_LIMIT (0xFFFFFFFF)
24
25#endif
diff --git a/arch/arm/mach-s5p6440/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 16a761270de1..513abffc7604 100644
--- a/arch/arm/mach-s5p6440/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -1,17 +1,17 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/irqs.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h
2 * 2 *
3 * Copyright 2009 Samsung Electronics Co., Ltd. 3 * Copyright 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - IRQ definitions 6 * S5P64X0 - IRQ definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13#ifndef __ASM_ARCH_S5P_IRQS_H 13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_S5P_IRQS_H __FILE__ 14#define __ASM_ARCH_IRQS_H __FILE__
15 15
16#include <plat/irqs.h> 16#include <plat/irqs.h>
17 17
@@ -20,10 +20,12 @@
20#define IRQ_EINT0_3 S5P_IRQ_VIC0(0) 20#define IRQ_EINT0_3 S5P_IRQ_VIC0(0)
21#define IRQ_EINT4_11 S5P_IRQ_VIC0(1) 21#define IRQ_EINT4_11 S5P_IRQ_VIC0(1)
22#define IRQ_RTC_TIC S5P_IRQ_VIC0(2) 22#define IRQ_RTC_TIC S5P_IRQ_VIC0(2)
23#define IRQ_IIS1 S5P_IRQ_VIC0(3) /* for only S5P6450 */
24#define IRQ_IIS2 S5P_IRQ_VIC0(4) /* for only S5P6450 */
23#define IRQ_IIC1 S5P_IRQ_VIC0(5) 25#define IRQ_IIC1 S5P_IRQ_VIC0(5)
24#define IRQ_I2SV40 S5P_IRQ_VIC0(6) 26#define IRQ_I2SV40 S5P_IRQ_VIC0(6)
25#define IRQ_GPS S5P_IRQ_VIC0(7) 27#define IRQ_GPS S5P_IRQ_VIC0(7) /* for only S5P6450 */
26#define IRQ_POST0 S5P_IRQ_VIC0(9) 28
27#define IRQ_2D S5P_IRQ_VIC0(11) 29#define IRQ_2D S5P_IRQ_VIC0(11)
28#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23) 30#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23)
29#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24) 31#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24)
@@ -39,22 +41,26 @@
39 41
40#define IRQ_EINT12_15 S5P_IRQ_VIC1(0) 42#define IRQ_EINT12_15 S5P_IRQ_VIC1(0)
41#define IRQ_PCM0 S5P_IRQ_VIC1(2) 43#define IRQ_PCM0 S5P_IRQ_VIC1(2)
44#define IRQ_PCM1 S5P_IRQ_VIC1(3) /* for only S5P6450 */
45#define IRQ_PCM2 S5P_IRQ_VIC1(4) /* for only S5P6450 */
42#define IRQ_UART0 S5P_IRQ_VIC1(5) 46#define IRQ_UART0 S5P_IRQ_VIC1(5)
43#define IRQ_UART1 S5P_IRQ_VIC1(6) 47#define IRQ_UART1 S5P_IRQ_VIC1(6)
44#define IRQ_UART2 S5P_IRQ_VIC1(7) 48#define IRQ_UART2 S5P_IRQ_VIC1(7)
45#define IRQ_UART3 S5P_IRQ_VIC1(8) 49#define IRQ_UART3 S5P_IRQ_VIC1(8)
46#define IRQ_DMA0 S5P_IRQ_VIC1(9) 50#define IRQ_DMA0 S5P_IRQ_VIC1(9)
51#define IRQ_UART4 S5P_IRQ_VIC1(10) /* S5P6450 */
52#define IRQ_UART5 S5P_IRQ_VIC1(11) /* S5P6450 */
47#define IRQ_NFC S5P_IRQ_VIC1(13) 53#define IRQ_NFC S5P_IRQ_VIC1(13)
54#define IRQ_USI S5P_IRQ_VIC1(15) /* S5P6450 */
48#define IRQ_SPI0 S5P_IRQ_VIC1(16) 55#define IRQ_SPI0 S5P_IRQ_VIC1(16)
49#define IRQ_SPI1 S5P_IRQ_VIC1(17) 56#define IRQ_SPI1 S5P_IRQ_VIC1(17)
57#define IRQ_HSMMC2 S5P_IRQ_VIC1(17) /* Shared */
50#define IRQ_IIC S5P_IRQ_VIC1(18) 58#define IRQ_IIC S5P_IRQ_VIC1(18)
51#define IRQ_DISPCON3 S5P_IRQ_VIC1(19) 59#define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
52#define IRQ_FIMGVG S5P_IRQ_VIC1(20)
53#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21) 60#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
54#define IRQ_PMU S5P_IRQ_VIC1(23) 61#define IRQ_PMU S5P_IRQ_VIC1(23) /* S5P6440 */
55#define IRQ_HSMMC0 S5P_IRQ_VIC1(24) 62#define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
56#define IRQ_HSMMC1 S5P_IRQ_VIC1(25) 63#define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
57#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
58#define IRQ_OTG S5P_IRQ_VIC1(26) 64#define IRQ_OTG S5P_IRQ_VIC1(26)
59#define IRQ_DSI S5P_IRQ_VIC1(27) 65#define IRQ_DSI S5P_IRQ_VIC1(27)
60#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28) 66#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28)
@@ -63,6 +69,24 @@
63#define IRQ_TC IRQ_PENDN 69#define IRQ_TC IRQ_PENDN
64#define IRQ_ADC S5P_IRQ_VIC1(31) 70#define IRQ_ADC S5P_IRQ_VIC1(31)
65 71
72/* UART interrupts, S5P6450 has 5 UARTs */
73#define IRQ_S5P_UART_BASE4 (96)
74#define IRQ_S5P_UART_BASE5 (100)
75
76#define IRQ_S5P_UART_RX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD)
77#define IRQ_S5P_UART_TX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD)
78#define IRQ_S5P_UART_ERR4 (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR)
79
80#define IRQ_S5P_UART_RX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD)
81#define IRQ_S5P_UART_TX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD)
82#define IRQ_S5P_UART_ERR5 (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR)
83
84/* S3C compatibilty defines */
85#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4
86#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5
87
88/* S5P6450 EINT feature will be added */
89
66/* 90/*
67 * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined 91 * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
68 * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place 92 * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
@@ -115,4 +139,4 @@
115 139
116#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) 140#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
117 141
118#endif /* __ASM_ARCH_S5P_IRQS_H */ 142#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
new file mode 100644
index 000000000000..31e534156e06
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -0,0 +1,83 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
18
19#define S5P64X0_PA_SDRAM (0x20000000)
20
21#define S5P64X0_PA_CHIPID (0xE0000000)
22#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
23
24#define S5P64X0_PA_SYSCON (0xE0100000)
25#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
26
27#define S5P64X0_PA_GPIO (0xE0308000)
28
29#define S5P64X0_PA_VIC0 (0xE4000000)
30#define S5P64X0_PA_VIC1 (0xE4100000)
31
32#define S5P64X0_PA_PDMA (0xE9000000)
33
34#define S5P64X0_PA_TIMER (0xEA000000)
35#define S5P_PA_TIMER S5P64X0_PA_TIMER
36
37#define S5P64X0_PA_RTC (0xEA100000)
38
39#define S5P64X0_PA_WDT (0xEA200000)
40
41#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET))
42#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
43
44#define S5P_PA_UART0 S5P6450_PA_UART(0)
45#define S5P_PA_UART1 S5P6450_PA_UART(1)
46#define S5P_PA_UART2 S5P6450_PA_UART(2)
47#define S5P_PA_UART3 S5P6450_PA_UART(3)
48#define S5P_PA_UART4 S5P6450_PA_UART(4)
49#define S5P_PA_UART5 S5P6450_PA_UART(5)
50
51#define S5P_SZ_UART SZ_256
52
53#define S5P6440_PA_IIC0 (0xEC104000)
54#define S5P6440_PA_IIC1 (0xEC20F000)
55#define S5P6450_PA_IIC0 (0xEC100000)
56#define S5P6450_PA_IIC1 (0xEC200000)
57
58#define S5P64X0_PA_SPI0 (0xEC400000)
59#define S5P64X0_PA_SPI1 (0xEC500000)
60
61#define S5P64X0_PA_HSOTG (0xED100000)
62
63#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
64
65#define S5P64X0_PA_I2S (0xF2000000)
66
67#define S5P64X0_PA_PCM (0xF2100000)
68
69#define S5P64X0_PA_ADC (0xF3000000)
70
71/* compatibiltiy defines. */
72
73#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
74#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
75#define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2)
76#define S3C_PA_IIC S5P6440_PA_IIC0
77#define S3C_PA_IIC1 S5P6440_PA_IIC1
78#define S3C_PA_RTC S5P64X0_PA_RTC
79#define S3C_PA_WDT S5P64X0_PA_WDT
80
81#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
82
83#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/memory.h b/arch/arm/mach-s5p64x0/include/mach/memory.h
index d62910c71b56..1b036b0a24ce 100644
--- a/arch/arm/mach-s5p6440/include/mach/memory.h
+++ b/arch/arm/mach-s5p64x0/include/mach/memory.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/memory.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/memory.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - Memory definitions 6 * S5P64X0 - Memory definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -11,9 +11,9 @@
11*/ 11*/
12 12
13#ifndef __ASM_ARCH_MEMORY_H 13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H 14#define __ASM_ARCH_MEMORY_H __FILE__
15 15
16#define PHYS_OFFSET UL(0x20000000) 16#define PHYS_OFFSET UL(0x20000000)
17#define CONSISTENT_DMA_SIZE SZ_8M 17#define CONSISTENT_DMA_SIZE SZ_8M
18 18
19#endif /* __ASM_ARCH_MEMORY_H */ 19#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
index 6a2a02fdf12a..19fff8b701c0 100644
--- a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
@@ -1,16 +1,14 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Copyright 2008 Openmoko, Inc. 6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics 7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk> 8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/ 9 * http://armlinux.simtec.co.uk/
10 * 10 *
11 * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h 11 * S5P64X0 - pwm clock and timer support
12 *
13 * S5P6440 - pwm clock and timer support
14 * 12 *
15 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as 14 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
new file mode 100644
index 000000000000..58e1bc813804
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
@@ -0,0 +1,63 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S5P64X0_APLL_CON S5P_CLKREG(0x0C)
21#define S5P64X0_MPLL_CON S5P_CLKREG(0x10)
22#define S5P64X0_EPLL_CON S5P_CLKREG(0x14)
23#define S5P64X0_EPLL_CON_K S5P_CLKREG(0x18)
24
25#define S5P64X0_CLK_SRC0 S5P_CLKREG(0x1C)
26
27#define S5P64X0_CLK_DIV0 S5P_CLKREG(0x20)
28#define S5P64X0_CLK_DIV1 S5P_CLKREG(0x24)
29#define S5P64X0_CLK_DIV2 S5P_CLKREG(0x28)
30
31#define S5P64X0_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
32#define S5P64X0_CLK_GATE_PCLK S5P_CLKREG(0x34)
33#define S5P64X0_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
34#define S5P64X0_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
35
36#define S5P64X0_CLK_DIV3 S5P_CLKREG(0x40)
37
38#define S5P64X0_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
39#define S5P64X0_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
40
41#define S5P6450_DPLL_CON S5P_CLKREG(0x50)
42#define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
43
44#define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
45
46#define S5P64X0_SYS_ID S5P_CLKREG(0x118)
47#define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
48
49#define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
50#define S5P64X0_OTHERS S5P_CLKREG(0x900)
51
52#define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
53#define S5P64X0_CLKDIV0_HCLK_MASK (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
54
55#define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
56
57/* Compatibility defines */
58
59#define ARM_CLK_DIV S5P64X0_CLK_DIV0
60#define ARM_DIV_RATIO_SHIFT 0
61#define ARM_DIV_MASK (0xF << ARM_DIV_RATIO_SHIFT)
62
63#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 82ff753913da..85f448e20a8b 100644
--- a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -1,21 +1,24 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/regs-gpio.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - GPIO register definitions 6 * S5P64X0 - GPIO register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11*/
12 12
13#ifndef __ASM_ARCH_REGS_GPIO_H 13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__ 14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15 15
16#include <mach/map.h> 16#include <mach/map.h>
17 17
18/* Will be implemented S5P6442 GPIOlib */
19
18/* Base addresses for each of the banks */ 20/* Base addresses for each of the banks */
21
19#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000) 22#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000)
20#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020) 23#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020)
21#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040) 24#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040)
@@ -27,6 +30,7 @@
27#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830) 30#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830)
28#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160) 31#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160)
29#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290) 32#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290)
33
30#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900) 34#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900)
31#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910) 35#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910)
32#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914) 36#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914)
@@ -34,19 +38,23 @@
34#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924) 38#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924)
35 39
36/* for LCD */ 40/* for LCD */
41
37#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0) 42#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0)
38#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0) 43#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0)
39 44
40/* These set of macros are not really useful for the 45/*
41 * GPF/GPI/GPJ/GPN/GPP, 46 * These set of macros are not really useful for the
42 * useful for others set of GPIO's (4 bit) 47 * GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit)
43 */ 48 */
49
44#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4)) 50#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4))
45#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4)) 51#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4))
46#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) 52#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
47 53
48/* Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit) 54/*
49 * */ 55 * Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
56 */
57
50#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) 58#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
51#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2)) 59#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2))
52#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) 60#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
index a961f4beeb0c..4aaebdace55f 100644
--- a/arch/arm/mach-s5p6440/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/regs-irq.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - IRQ register definitions 6 * S5P64X0 - IRQ register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
new file mode 100644
index 000000000000..ff85b4b6e8d9
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
@@ -0,0 +1,46 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for s5p64x0 clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_CLOCK_H
14#define __ASM_ARCH_CLOCK_H __FILE__
15
16#include <linux/clk.h>
17
18extern struct clksrc_clk clk_mout_apll;
19extern struct clksrc_clk clk_mout_mpll;
20extern struct clksrc_clk clk_mout_epll;
21
22extern int s5p64x0_epll_enable(struct clk *clk, int enable);
23extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
24
25extern unsigned long s5p64x0_armclk_get_rate(struct clk *clk);
26extern unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate);
27extern int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate);
28
29extern struct clk_ops s5p64x0_clkarm_ops;
30
31extern struct clksrc_clk clk_armclk;
32extern struct clksrc_clk clk_dout_mpll;
33
34extern struct clk *clkset_hclk_low_list[];
35extern struct clksrc_sources clkset_hclk_low;
36
37extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
38extern int s5p64x0_hclk0_ctrl(struct clk *clk, int enable);
39extern int s5p64x0_hclk1_ctrl(struct clk *clk, int enable);
40extern int s5p64x0_sclk_ctrl(struct clk *clk, int enable);
41extern int s5p64x0_sclk1_ctrl(struct clk *clk, int enable);
42extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
43
44extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
45
46#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..170a20a9643a
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
@@ -0,0 +1,20 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_SPI_CLKS_H
15#define __ASM_ARCH_SPI_CLKS_H __FILE__
16
17#define S5P64X0_SPI_SRCCLK_PCLK 0
18#define S5P64X0_SPI_SRCCLK_SCLK 1
19
20#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/system.h b/arch/arm/mach-s5p64x0/include/mach/system.h
index a359ee3fa510..60f57532c970 100644
--- a/arch/arm/mach-s5p6440/include/mach/system.h
+++ b/arch/arm/mach-s5p64x0/include/mach/system.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/system.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/system.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - system support header 6 * S5P64X0 - system support header
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p6440/include/mach/tick.h b/arch/arm/mach-s5p64x0/include/mach/tick.h
index 2f25c7f07970..00aa7f1d8e51 100644
--- a/arch/arm/mach-s5p6440/include/mach/tick.h
+++ b/arch/arm/mach-s5p64x0/include/mach/tick.h
@@ -1,9 +1,14 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/tick.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/tick.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - Timer tick support definitions 6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * http://armlinux.simtec.co.uk/
9 * Ben Dooks <ben@simtec.co.uk>
10 *
11 * S5P64X0 - Timer tick support definitions
7 * 12 *
8 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 14 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p6440/include/mach/timex.h b/arch/arm/mach-s5p64x0/include/mach/timex.h
index fb2e8cd40829..4b91faa195a8 100644
--- a/arch/arm/mach-s5p6440/include/mach/timex.h
+++ b/arch/arm/mach-s5p64x0/include/mach/timex.h
@@ -1,9 +1,12 @@
1/* arch/arm/mach-s3c64xx/include/mach/timex.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/timex.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
2 * 5 *
3 * Copyright (c) 2003-2005 Simtec Electronics 6 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 7 * Ben Dooks <ben@simtec.co.uk>
5 * 8 *
6 * S3C6400 - time parameters 9 * S5P64X0 - time parameters
7 * 10 *
8 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
new file mode 100644
index 000000000000..c65b229aab23
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -0,0 +1,212 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/uncompress.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - uncompress code
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H
15
16#include <mach/map.h>
17
18/*
19 * cannot use commonly <plat/uncompress.h>
20 * because uart base of S5P6440 and S5P6450 is different
21 */
22
23typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
24
25/* uart setup */
26
27static unsigned int fifo_mask;
28static unsigned int fifo_max;
29
30/* forward declerations */
31
32static void arch_detect_cpu(void);
33
34/* defines for UART registers */
35
36#include <plat/regs-serial.h>
37#include <plat/regs-watchdog.h>
38
39/* working in physical space... */
40#undef S3C2410_WDOGREG
41#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
42
43/* how many bytes we allow into the FIFO at a time in FIFO mode */
44#define FIFO_MAX (14)
45
46static unsigned long uart_base;
47
48static __inline__ void get_uart_base(void)
49{
50 unsigned int chipid;
51
52 chipid = *(const volatile unsigned int __force *) 0xE0100118;
53
54 uart_base = S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT;
55
56 if ((chipid & 0xff000) == 0x50000)
57 uart_base += 0xEC800000;
58 else
59 uart_base += 0xEC000000;
60}
61
62static __inline__ void uart_wr(unsigned int reg, unsigned int val)
63{
64 volatile unsigned int *ptr;
65
66 get_uart_base();
67 ptr = (volatile unsigned int *)(reg + uart_base);
68 *ptr = val;
69}
70
71static __inline__ unsigned int uart_rd(unsigned int reg)
72{
73 volatile unsigned int *ptr;
74
75 get_uart_base();
76 ptr = (volatile unsigned int *)(reg + uart_base);
77 return *ptr;
78}
79
80/*
81 * we can deal with the case the UARTs are being run
82 * in FIFO mode, so that we don't hold up our execution
83 * waiting for tx to happen...
84 */
85
86static void putc(int ch)
87{
88 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
89 int level;
90
91 while (1) {
92 level = uart_rd(S3C2410_UFSTAT);
93 level &= fifo_mask;
94
95 if (level < fifo_max)
96 break;
97 }
98
99 } else {
100 /* not using fifos */
101
102 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
103 barrier();
104 }
105
106 /* write byte to transmission register */
107 uart_wr(S3C2410_UTXH, ch);
108}
109
110static inline void flush(void)
111{
112}
113
114#define __raw_writel(d, ad) \
115 do { \
116 *((volatile unsigned int __force *)(ad)) = (d); \
117 } while (0)
118
119/*
120 * CONFIG_S3C_BOOT_WATCHDOG
121 *
122 * Simple boot-time watchdog setup, to reboot the system if there is
123 * any problem with the boot process
124 */
125
126#ifdef CONFIG_S3C_BOOT_WATCHDOG
127
128#define WDOG_COUNT (0xff00)
129
130static inline void arch_decomp_wdog(void)
131{
132 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
133}
134
135static void arch_decomp_wdog_start(void)
136{
137 __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
138 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
139 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
140}
141
142#else
143#define arch_decomp_wdog_start()
144#define arch_decomp_wdog()
145#endif
146
147#ifdef CONFIG_S3C_BOOT_ERROR_RESET
148
149static void arch_decomp_error(const char *x)
150{
151 putstr("\n\n");
152 putstr(x);
153 putstr("\n\n -- System resetting\n");
154
155 __raw_writel(0x4000, S3C2410_WTDAT);
156 __raw_writel(0x4000, S3C2410_WTCNT);
157 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
158
159 while(1);
160}
161
162#define arch_error arch_decomp_error
163#endif
164
165#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
166static inline void arch_enable_uart_fifo(void)
167{
168 u32 fifocon = uart_rd(S3C2410_UFCON);
169
170 if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
171 fifocon |= S3C2410_UFCON_RESETBOTH;
172 uart_wr(S3C2410_UFCON, fifocon);
173
174 /* wait for fifo reset to complete */
175 while (1) {
176 fifocon = uart_rd(S3C2410_UFCON);
177 if (!(fifocon & S3C2410_UFCON_RESETBOTH))
178 break;
179 }
180 }
181}
182#else
183#define arch_enable_uart_fifo() do { } while(0)
184#endif
185
186static void arch_decomp_setup(void)
187{
188 /*
189 * we may need to setup the uart(s) here if we are not running
190 * on an BAST... the BAST will have left the uarts configured
191 * after calling linux.
192 */
193
194 arch_detect_cpu();
195 arch_decomp_wdog_start();
196
197 /*
198 * Enable the UART FIFOs if they where not enabled and our
199 * configuration says we should turn them on.
200 */
201
202 arch_enable_uart_fifo();
203}
204
205
206
207static void arch_detect_cpu(void)
208{
209 /* we do not need to do any cpu detection here at the moment. */
210}
211
212#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/vmalloc.h b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
index e3f0eebf5205..97a9df38f1cf 100644
--- a/arch/arm/mach-s5p6440/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
@@ -1,4 +1,7 @@
1/* arch/arm/mach-s5p6440/include/mach/vmalloc.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
2 * 5 *
3 * Copyright 2010 Ben Dooks <ben-linux@fluff.org> 6 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
4 * 7 *
diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
new file mode 100644
index 000000000000..79833caf8165
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/init.c
@@ -0,0 +1,73 @@
1/* linux/arch/arm/mach-s5p64x0/init.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Init support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/serial_core.h>
17
18#include <mach/map.h>
19
20#include <plat/cpu.h>
21#include <plat/devs.h>
22#include <plat/s5p6440.h>
23#include <plat/s5p6450.h>
24#include <plat/regs-serial.h>
25
26static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
27 [0] = {
28 .name = "pclk_low",
29 .divisor = 1,
30 .min_baud = 0,
31 .max_baud = 0,
32 },
33 [1] = {
34 .name = "uclk1",
35 .divisor = 1,
36 .min_baud = 0,
37 .max_baud = 0,
38 },
39};
40
41/* uart registration process */
42
43void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
44{
45 struct s3c2410_uartcfg *tcfg = cfg;
46 u32 ucnt;
47
48 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
49 if (!tcfg->clocks) {
50 tcfg->clocks = s5p64x0_serial_clocks;
51 tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
52 }
53 }
54}
55
56void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
57{
58 int uart;
59
60 for (uart = 0; uart < no; uart++) {
61 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
62 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
63 }
64
65 s5p64x0_common_init_uarts(cfg, no);
66 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
67}
68
69void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
70{
71 s5p64x0_common_init_uarts(cfg, no);
72 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
73}
diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 9202aaac3b56..28de0a57208c 100644
--- a/arch/arm/mach-s5p6440/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5p6440/mach-smdk6440.c 1/* linux/arch/arm/mach-s5p64x0/mach-smdk6440.c
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -21,21 +21,22 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/module.h> 22#include <linux/module.h>
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/gpio.h>
24 25
25#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
26#include <asm/mach/map.h> 27#include <asm/mach/map.h>
28#include <asm/irq.h>
29#include <asm/mach-types.h>
27 30
28#include <mach/hardware.h> 31#include <mach/hardware.h>
29#include <mach/map.h> 32#include <mach/map.h>
30 33#include <mach/regs-clock.h>
31#include <asm/irq.h> 34#include <mach/i2c.h>
32#include <asm/mach-types.h>
33 35
34#include <plat/regs-serial.h> 36#include <plat/regs-serial.h>
35 37#include <plat/gpio-cfg.h>
36#include <plat/s5p6440.h> 38#include <plat/s5p6440.h>
37#include <plat/clock.h> 39#include <plat/clock.h>
38#include <mach/regs-clock.h>
39#include <plat/devs.h> 40#include <plat/devs.h>
40#include <plat/cpu.h> 41#include <plat/cpu.h>
41#include <plat/iic.h> 42#include <plat/iic.h>
@@ -58,43 +59,60 @@
58 59
59static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { 60static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
60 [0] = { 61 [0] = {
61 .hwport = 0, 62 .hwport = 0,
62 .flags = 0, 63 .flags = 0,
63 .ucon = SMDK6440_UCON_DEFAULT, 64 .ucon = SMDK6440_UCON_DEFAULT,
64 .ulcon = SMDK6440_ULCON_DEFAULT, 65 .ulcon = SMDK6440_ULCON_DEFAULT,
65 .ufcon = SMDK6440_UFCON_DEFAULT, 66 .ufcon = SMDK6440_UFCON_DEFAULT,
66 }, 67 },
67 [1] = { 68 [1] = {
68 .hwport = 1, 69 .hwport = 1,
69 .flags = 0, 70 .flags = 0,
70 .ucon = SMDK6440_UCON_DEFAULT, 71 .ucon = SMDK6440_UCON_DEFAULT,
71 .ulcon = SMDK6440_ULCON_DEFAULT, 72 .ulcon = SMDK6440_ULCON_DEFAULT,
72 .ufcon = SMDK6440_UFCON_DEFAULT, 73 .ufcon = SMDK6440_UFCON_DEFAULT,
73 }, 74 },
74 [2] = { 75 [2] = {
75 .hwport = 2, 76 .hwport = 2,
76 .flags = 0, 77 .flags = 0,
77 .ucon = SMDK6440_UCON_DEFAULT, 78 .ucon = SMDK6440_UCON_DEFAULT,
78 .ulcon = SMDK6440_ULCON_DEFAULT, 79 .ulcon = SMDK6440_ULCON_DEFAULT,
79 .ufcon = SMDK6440_UFCON_DEFAULT, 80 .ufcon = SMDK6440_UFCON_DEFAULT,
80 }, 81 },
81 [3] = { 82 [3] = {
82 .hwport = 3, 83 .hwport = 3,
83 .flags = 0, 84 .flags = 0,
84 .ucon = SMDK6440_UCON_DEFAULT, 85 .ucon = SMDK6440_UCON_DEFAULT,
85 .ulcon = SMDK6440_ULCON_DEFAULT, 86 .ulcon = SMDK6440_ULCON_DEFAULT,
86 .ufcon = SMDK6440_UFCON_DEFAULT, 87 .ufcon = SMDK6440_UFCON_DEFAULT,
87 }, 88 },
88}; 89};
89 90
90static struct platform_device *smdk6440_devices[] __initdata = { 91static struct platform_device *smdk6440_devices[] __initdata = {
91 &s5p6440_device_iis,
92 &s3c_device_adc, 92 &s3c_device_adc,
93 &s3c_device_rtc, 93 &s3c_device_rtc,
94 &s3c_device_i2c0, 94 &s3c_device_i2c0,
95 &s3c_device_i2c1, 95 &s3c_device_i2c1,
96 &s3c_device_ts, 96 &s3c_device_ts,
97 &s3c_device_wdt, 97 &s3c_device_wdt,
98 &s5p6440_device_iis,
99};
100
101static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
102 .flags = 0,
103 .slave_addr = 0x10,
104 .frequency = 100*1000,
105 .sda_delay = 100,
106 .cfg_gpio = s5p6440_i2c0_cfg_gpio,
107};
108
109static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = {
110 .flags = 0,
111 .bus_num = 1,
112 .slave_addr = 0x10,
113 .frequency = 100*1000,
114 .sda_delay = 100,
115 .cfg_gpio = s5p6440_i2c1_cfg_gpio,
98}; 116};
99 117
100static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = { 118static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = {
@@ -113,7 +131,7 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
113 131
114static void __init smdk6440_map_io(void) 132static void __init smdk6440_map_io(void)
115{ 133{
116 s5p_init_io(NULL, 0, S5P_SYS_ID); 134 s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
117 s3c24xx_init_clocks(12000000); 135 s3c24xx_init_clocks(12000000);
118 s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs)); 136 s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
119} 137}
@@ -122,9 +140,8 @@ static void __init smdk6440_machine_init(void)
122{ 140{
123 s3c24xx_ts_set_platdata(&s3c_ts_platform); 141 s3c24xx_ts_set_platdata(&s3c_ts_platform);
124 142
125 /* I2C */ 143 s3c_i2c0_set_platdata(&s5p6440_i2c0_data);
126 s3c_i2c0_set_platdata(NULL); 144 s3c_i2c1_set_platdata(&s5p6440_i2c1_data);
127 s3c_i2c1_set_platdata(NULL);
128 i2c_register_board_info(0, smdk6440_i2c_devs0, 145 i2c_register_board_info(0, smdk6440_i2c_devs0,
129 ARRAY_SIZE(smdk6440_i2c_devs0)); 146 ARRAY_SIZE(smdk6440_i2c_devs0));
130 i2c_register_board_info(1, smdk6440_i2c_devs1, 147 i2c_register_board_info(1, smdk6440_i2c_devs1,
@@ -135,9 +152,9 @@ static void __init smdk6440_machine_init(void)
135 152
136MACHINE_START(SMDK6440, "SMDK6440") 153MACHINE_START(SMDK6440, "SMDK6440")
137 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 154 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
138 .phys_io = S3C_PA_UART & 0xfff00000, 155 .phys_io = S5P6440_PA_UART(0) & 0xfff00000,
139 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, 156 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
140 .boot_params = S5P_PA_SDRAM + 0x100, 157 .boot_params = S5P64X0_PA_SDRAM + 0x100,
141 158
142 .init_irq = s5p6440_init_irq, 159 .init_irq = s5p6440_init_irq,
143 .map_io = smdk6440_map_io, 160 .map_io = smdk6440_map_io,
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
new file mode 100644
index 000000000000..8e982171418b
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -0,0 +1,182 @@
1/* linux/arch/arm/mach-s5p64x0/mach-smdk6450.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/i2c.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/clk.h>
24#include <linux/gpio.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/irq.h>
29#include <asm/mach-types.h>
30
31#include <mach/hardware.h>
32#include <mach/map.h>
33#include <mach/regs-clock.h>
34#include <mach/i2c.h>
35
36#include <plat/regs-serial.h>
37#include <plat/gpio-cfg.h>
38#include <plat/s5p6450.h>
39#include <plat/clock.h>
40#include <plat/devs.h>
41#include <plat/cpu.h>
42#include <plat/iic.h>
43#include <plat/pll.h>
44#include <plat/adc.h>
45#include <plat/ts.h>
46
47#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
48 S3C2410_UCON_RXILEVEL | \
49 S3C2410_UCON_TXIRQMODE | \
50 S3C2410_UCON_RXIRQMODE | \
51 S3C2410_UCON_RXFIFO_TOI | \
52 S3C2443_UCON_RXERR_IRQEN)
53
54#define SMDK6450_ULCON_DEFAULT S3C2410_LCON_CS8
55
56#define SMDK6450_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
57 S3C2440_UFCON_TXTRIG16 | \
58 S3C2410_UFCON_RXTRIG8)
59
60static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
61 [0] = {
62 .hwport = 0,
63 .flags = 0,
64 .ucon = SMDK6450_UCON_DEFAULT,
65 .ulcon = SMDK6450_ULCON_DEFAULT,
66 .ufcon = SMDK6450_UFCON_DEFAULT,
67 },
68 [1] = {
69 .hwport = 1,
70 .flags = 0,
71 .ucon = SMDK6450_UCON_DEFAULT,
72 .ulcon = SMDK6450_ULCON_DEFAULT,
73 .ufcon = SMDK6450_UFCON_DEFAULT,
74 },
75 [2] = {
76 .hwport = 2,
77 .flags = 0,
78 .ucon = SMDK6450_UCON_DEFAULT,
79 .ulcon = SMDK6450_ULCON_DEFAULT,
80 .ufcon = SMDK6450_UFCON_DEFAULT,
81 },
82 [3] = {
83 .hwport = 3,
84 .flags = 0,
85 .ucon = SMDK6450_UCON_DEFAULT,
86 .ulcon = SMDK6450_ULCON_DEFAULT,
87 .ufcon = SMDK6450_UFCON_DEFAULT,
88 },
89#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
90 [4] = {
91 .hwport = 4,
92 .flags = 0,
93 .ucon = SMDK6450_UCON_DEFAULT,
94 .ulcon = SMDK6450_ULCON_DEFAULT,
95 .ufcon = SMDK6450_UFCON_DEFAULT,
96 },
97#endif
98#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
99 [5] = {
100 .hwport = 5,
101 .flags = 0,
102 .ucon = SMDK6450_UCON_DEFAULT,
103 .ulcon = SMDK6450_ULCON_DEFAULT,
104 .ufcon = SMDK6450_UFCON_DEFAULT,
105 },
106#endif
107};
108
109static struct platform_device *smdk6450_devices[] __initdata = {
110 &s3c_device_adc,
111 &s3c_device_rtc,
112 &s3c_device_i2c0,
113 &s3c_device_i2c1,
114 &s3c_device_ts,
115 &s3c_device_wdt,
116 &s5p6450_device_iis0,
117 /* s5p6450_device_spi0 will be added */
118};
119
120static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
121 .flags = 0,
122 .slave_addr = 0x10,
123 .frequency = 100*1000,
124 .sda_delay = 100,
125 .cfg_gpio = s5p6450_i2c0_cfg_gpio,
126};
127
128static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = {
129 .flags = 0,
130 .bus_num = 1,
131 .slave_addr = 0x10,
132 .frequency = 100*1000,
133 .sda_delay = 100,
134 .cfg_gpio = s5p6450_i2c1_cfg_gpio,
135};
136
137static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = {
138 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung KS24C080C EEPROM */
139};
140
141static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = {
142 { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */
143};
144
145static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
146 .delay = 10000,
147 .presc = 49,
148 .oversampling_shift = 2,
149};
150
151static void __init smdk6450_map_io(void)
152{
153 s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
154 s3c24xx_init_clocks(19200000);
155 s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
156}
157
158static void __init smdk6450_machine_init(void)
159{
160 s3c24xx_ts_set_platdata(&s3c_ts_platform);
161
162 s3c_i2c0_set_platdata(&s5p6450_i2c0_data);
163 s3c_i2c1_set_platdata(&s5p6450_i2c1_data);
164 i2c_register_board_info(0, smdk6450_i2c_devs0,
165 ARRAY_SIZE(smdk6450_i2c_devs0));
166 i2c_register_board_info(1, smdk6450_i2c_devs1,
167 ARRAY_SIZE(smdk6450_i2c_devs1));
168
169 platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
170}
171
172MACHINE_START(SMDK6450, "SMDK6450")
173 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
174 .phys_io = S5P6450_PA_UART(0) & 0xfff00000,
175 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
176 .boot_params = S5P64X0_PA_SDRAM + 0x100,
177
178 .init_irq = s5p6450_init_irq,
179 .map_io = smdk6450_map_io,
180 .init_machine = smdk6450_machine_init,
181 .timer = &s3c24xx_timer,
182MACHINE_END
diff --git a/arch/arm/mach-s5p6440/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
index 2c99d14f7ac7..dc4cc65a5019 100644
--- a/arch/arm/mach-s5p6440/setup-i2c0.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c0.c
@@ -1,11 +1,11 @@
1/* linux/arch/arm/mach-s5p6440/setup-i2c0.c 1/* linux/arch/arm/mach-s5p64x0/setup-i2c0.c
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * I2C0 GPIO configuration. 6 * I2C0 GPIO configuration.
7 * 7 *
8 * Based on plat-s3c64xx/setup-i2c0.c 8 * Based on plat-s3c64x0/setup-i2c0.c
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
@@ -14,17 +14,29 @@
14 14
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/types.h> 16#include <linux/types.h>
17#include <linux/gpio.h>
17 18
18struct platform_device; /* don't need the contents */ 19struct platform_device; /* don't need the contents */
19 20
20#include <linux/gpio.h>
21#include <plat/gpio-cfg.h> 21#include <plat/gpio-cfg.h>
22#include <plat/iic.h> 22#include <plat/iic.h>
23 23
24void s3c_i2c0_cfg_gpio(struct platform_device *dev) 24#include <mach/i2c.h>
25
26void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
25{ 27{
26 s3c_gpio_cfgpin(S5P6440_GPB(5), S3C_GPIO_SFN(2)); 28 s3c_gpio_cfgpin(S5P6440_GPB(5), S3C_GPIO_SFN(2));
27 s3c_gpio_setpull(S5P6440_GPB(5), S3C_GPIO_PULL_UP); 29 s3c_gpio_setpull(S5P6440_GPB(5), S3C_GPIO_PULL_UP);
28 s3c_gpio_cfgpin(S5P6440_GPB(6), S3C_GPIO_SFN(2)); 30 s3c_gpio_cfgpin(S5P6440_GPB(6), S3C_GPIO_SFN(2));
29 s3c_gpio_setpull(S5P6440_GPB(6), S3C_GPIO_PULL_UP); 31 s3c_gpio_setpull(S5P6440_GPB(6), S3C_GPIO_PULL_UP);
30} 32}
33
34void s5p6450_i2c0_cfg_gpio(struct platform_device *dev)
35{
36 s3c_gpio_cfgpin(S5P6450_GPB(5), S3C_GPIO_SFN(2));
37 s3c_gpio_setpull(S5P6450_GPB(5), S3C_GPIO_PULL_UP);
38 s3c_gpio_cfgpin(S5P6450_GPB(6), S3C_GPIO_SFN(2));
39 s3c_gpio_setpull(S5P6450_GPB(6), S3C_GPIO_PULL_UP);
40}
41
42void s3c_i2c0_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5p6440/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
index 9a1537f786e0..2edd7912f8e4 100644
--- a/arch/arm/mach-s5p6440/setup-i2c1.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c1.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5p6440/setup-i2c1.c 1/* linux/arch/arm/mach-s5p64xx/setup-i2c1.c
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * I2C1 GPIO configuration. 6 * I2C1 GPIO configuration.
7 * 7 *
@@ -21,10 +21,22 @@ struct platform_device; /* don't need the contents */
21#include <plat/gpio-cfg.h> 21#include <plat/gpio-cfg.h>
22#include <plat/iic.h> 22#include <plat/iic.h>
23 23
24void s3c_i2c1_cfg_gpio(struct platform_device *dev) 24#include <mach/i2c.h>
25
26void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
25{ 27{
26 s3c_gpio_cfgpin(S5P6440_GPR(9), S3C_GPIO_SFN(6)); 28 s3c_gpio_cfgpin(S5P6440_GPR(9), S3C_GPIO_SFN(6));
27 s3c_gpio_setpull(S5P6440_GPR(9), S3C_GPIO_PULL_UP); 29 s3c_gpio_setpull(S5P6440_GPR(9), S3C_GPIO_PULL_UP);
28 s3c_gpio_cfgpin(S5P6440_GPR(10), S3C_GPIO_SFN(6)); 30 s3c_gpio_cfgpin(S5P6440_GPR(10), S3C_GPIO_SFN(6));
29 s3c_gpio_setpull(S5P6440_GPR(10), S3C_GPIO_PULL_UP); 31 s3c_gpio_setpull(S5P6440_GPR(10), S3C_GPIO_PULL_UP);
30} 32}
33
34void s5p6450_i2c1_cfg_gpio(struct platform_device *dev)
35{
36 s3c_gpio_cfgpin(S5P6450_GPR(9), S3C_GPIO_SFN(6));
37 s3c_gpio_setpull(S5P6450_GPR(9), S3C_GPIO_PULL_UP);
38 s3c_gpio_cfgpin(S5P6450_GPR(10), S3C_GPIO_SFN(6));
39 s3c_gpio_setpull(S5P6450_GPR(10), S3C_GPIO_PULL_UP);
40}
41
42void s3c_i2c1_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index 251c92ac5b22..fd2708e7d8a9 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -1,5 +1,8 @@
1/* linux/arch/arm/mach-s5pc100/cpu.c 1/* linux/arch/arm/mach-s5pc100/cpu.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
3 * Copyright 2009 Samsung Electronics Co. 6 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 7 * Byungho Min <bhmin@samsung.com>
5 * 8 *
@@ -21,6 +24,7 @@
21#include <linux/sysdev.h> 24#include <linux/sysdev.h>
22#include <linux/serial_core.h> 25#include <linux/serial_core.h>
23#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/sched.h>
24 28
25#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
26#include <asm/mach/map.h> 30#include <asm/mach/map.h>
@@ -56,11 +60,31 @@ static struct map_desc s5pc100_iodesc[] __initdata = {
56 .length = SZ_16K, 60 .length = SZ_16K,
57 .type = MT_DEVICE, 61 .type = MT_DEVICE,
58 }, { 62 }, {
63 .virtual = (unsigned long)S5P_VA_GPIO,
64 .pfn = __phys_to_pfn(S5PC100_PA_GPIO),
65 .length = SZ_4K,
66 .type = MT_DEVICE,
67 }, {
68 .virtual = (unsigned long)VA_VIC0,
69 .pfn = __phys_to_pfn(S5PC100_PA_VIC0),
70 .length = SZ_16K,
71 .type = MT_DEVICE,
72 }, {
73 .virtual = (unsigned long)VA_VIC1,
74 .pfn = __phys_to_pfn(S5PC100_PA_VIC1),
75 .length = SZ_16K,
76 .type = MT_DEVICE,
77 }, {
59 .virtual = (unsigned long)VA_VIC2, 78 .virtual = (unsigned long)VA_VIC2,
60 .pfn = __phys_to_pfn(S5P_PA_VIC2), 79 .pfn = __phys_to_pfn(S5PC100_PA_VIC2),
61 .length = SZ_16K, 80 .length = SZ_16K,
62 .type = MT_DEVICE, 81 .type = MT_DEVICE,
63 }, { 82 }, {
83 .virtual = (unsigned long)S3C_VA_UART,
84 .pfn = __phys_to_pfn(S3C_PA_UART),
85 .length = SZ_512K,
86 .type = MT_DEVICE,
87 }, {
64 .virtual = (unsigned long)S5PC100_VA_OTHERS, 88 .virtual = (unsigned long)S5PC100_VA_OTHERS,
65 .pfn = __phys_to_pfn(S5PC100_PA_OTHERS), 89 .pfn = __phys_to_pfn(S5PC100_PA_OTHERS),
66 .length = SZ_4K, 90 .length = SZ_4K,
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 01b9134feff0..8751ef4a6804 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -44,19 +44,16 @@
44#define S5PC100_PA_OTHERS (0xE0200000) 44#define S5PC100_PA_OTHERS (0xE0200000)
45#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) 45#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
46 46
47#define S5P_PA_GPIO (0xE0300000) 47#define S5PC100_PA_GPIO (0xE0300000)
48#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) 48#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
49 49
50/* Interrupt */ 50/* Interrupt */
51#define S5PC100_PA_VIC (0xE4000000) 51#define S5PC100_PA_VIC0 (0xE4000000)
52#define S5PC100_PA_VIC1 (0xE4100000)
53#define S5PC100_PA_VIC2 (0xE4200000)
52#define S5PC100_VA_VIC S3C_VA_IRQ 54#define S5PC100_VA_VIC S3C_VA_IRQ
53#define S5PC100_PA_VIC_OFFSET 0x100000
54#define S5PC100_VA_VIC_OFFSET 0x10000 55#define S5PC100_VA_VIC_OFFSET 0x10000
55#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
56#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) 56#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
57#define S5P_PA_VIC0 S5PC1XX_PA_VIC(0)
58#define S5P_PA_VIC1 S5PC1XX_PA_VIC(1)
59#define S5P_PA_VIC2 S5PC1XX_PA_VIC(2)
60 57
61 58
62#define S5PC100_PA_ONENAND (0xE7100000) 59#define S5PC100_PA_ONENAND (0xE7100000)
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index d3a38955c741..5315fec3db86 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -53,11 +53,6 @@ config S5PV210_SETUP_SDHCI_GPIO
53 help 53 help
54 Common setup code for SDHCI gpio. 54 Common setup code for SDHCI gpio.
55 55
56config S5PC110_DEV_ONENAND
57 bool
58 help
59 Compile in platform device definition for OneNAND1 controller
60
61menu "S5PC110 Machines" 56menu "S5PC110 Machines"
62 57
63config MACH_AQUILA 58config MACH_AQUILA
@@ -71,7 +66,7 @@ config MACH_AQUILA
71 select S3C_DEV_HSMMC 66 select S3C_DEV_HSMMC
72 select S3C_DEV_HSMMC1 67 select S3C_DEV_HSMMC1
73 select S3C_DEV_HSMMC2 68 select S3C_DEV_HSMMC2
74 select S5PC110_DEV_ONENAND 69 select S5P_DEV_ONENAND
75 select S5PV210_SETUP_FB_24BPP 70 select S5PV210_SETUP_FB_24BPP
76 select S5PV210_SETUP_SDHCI 71 select S5PV210_SETUP_SDHCI
77 help 72 help
@@ -88,7 +83,7 @@ config MACH_GONI
88 select S3C_DEV_HSMMC 83 select S3C_DEV_HSMMC
89 select S3C_DEV_HSMMC1 84 select S3C_DEV_HSMMC1
90 select S3C_DEV_HSMMC2 85 select S3C_DEV_HSMMC2
91 select S5PC110_DEV_ONENAND 86 select S5P_DEV_ONENAND
92 select S5PV210_SETUP_FB_24BPP 87 select S5PV210_SETUP_FB_24BPP
93 select S5PV210_SETUP_SDHCI 88 select S5PV210_SETUP_SDHCI
94 help 89 help
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 05048c5aa4c6..704548912408 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_MACH_GONI) += mach-goni.o
26 26
27obj-y += dev-audio.o 27obj-y += dev-audio.o
28obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o 28obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
29obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o
30 29
31obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o 30obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o
32obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o 31obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index cfecd70657cb..d562670e1b0b 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -173,11 +173,6 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
173 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); 173 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
174} 174}
175 175
176static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable)
177{
178 return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable);
179}
180
181static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) 176static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
182{ 177{
183 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); 178 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 77f456c91ad3..2f16bfc0a116 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv210/cpu.c 1/* linux/arch/arm/mach-s5pv210/cpu.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -19,6 +19,7 @@
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/sysdev.h> 20#include <linux/sysdev.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/sched.h>
22 23
23#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
24#include <asm/mach/map.h> 25#include <asm/mach/map.h>
@@ -50,6 +51,21 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
50 .length = SZ_4K, 51 .length = SZ_4K,
51 .type = MT_DEVICE, 52 .type = MT_DEVICE,
52 }, { 53 }, {
54 .virtual = (unsigned long)S5P_VA_GPIO,
55 .pfn = __phys_to_pfn(S5PV210_PA_GPIO),
56 .length = SZ_4K,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = (unsigned long)VA_VIC0,
60 .pfn = __phys_to_pfn(S5PV210_PA_VIC0),
61 .length = SZ_16K,
62 .type = MT_DEVICE,
63 }, {
64 .virtual = (unsigned long)VA_VIC1,
65 .pfn = __phys_to_pfn(S5PV210_PA_VIC1),
66 .length = SZ_16K,
67 .type = MT_DEVICE,
68 }, {
53 .virtual = (unsigned long)VA_VIC2, 69 .virtual = (unsigned long)VA_VIC2,
54 .pfn = __phys_to_pfn(S5PV210_PA_VIC2), 70 .pfn = __phys_to_pfn(S5PV210_PA_VIC2),
55 .length = SZ_16K, 71 .length = SZ_16K,
@@ -60,6 +76,11 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
60 .length = SZ_16K, 76 .length = SZ_16K,
61 .type = MT_DEVICE, 77 .type = MT_DEVICE,
62 }, { 78 }, {
79 .virtual = (unsigned long)S3C_VA_UART,
80 .pfn = __phys_to_pfn(S3C_PA_UART),
81 .length = SZ_512K,
82 .type = MT_DEVICE,
83 }, {
63 .virtual = (unsigned long)S5P_VA_SROMC, 84 .virtual = (unsigned long)S5P_VA_SROMC,
64 .pfn = __phys_to_pfn(S5PV210_PA_SROMC), 85 .pfn = __phys_to_pfn(S5PV210_PA_SROMC),
65 .length = SZ_4K, 86 .length = SZ_4K,
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index dd4fb6bf14b5..bd9afd52466a 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -17,7 +17,10 @@
17#include <plat/map-s5p.h> 17#include <plat/map-s5p.h>
18 18
19#define S5PC110_PA_ONENAND (0xB0000000) 19#define S5PC110_PA_ONENAND (0xB0000000)
20#define S5P_PA_ONENAND S5PC110_PA_ONENAND
21
20#define S5PC110_PA_ONENAND_DMA (0xB0600000) 22#define S5PC110_PA_ONENAND_DMA (0xB0600000)
23#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
21 24
22#define S5PV210_PA_CHIPID (0xE0000000) 25#define S5PV210_PA_CHIPID (0xE0000000)
23#define S5P_PA_CHIPID S5PV210_PA_CHIPID 26#define S5P_PA_CHIPID S5PV210_PA_CHIPID
@@ -26,7 +29,6 @@
26#define S5P_PA_SYSCON S5PV210_PA_SYSCON 29#define S5P_PA_SYSCON S5PV210_PA_SYSCON
27 30
28#define S5PV210_PA_GPIO (0xE0200000) 31#define S5PV210_PA_GPIO (0xE0200000)
29#define S5P_PA_GPIO S5PV210_PA_GPIO
30 32
31/* SPI */ 33/* SPI */
32#define S5PV210_PA_SPI0 0xE1300000 34#define S5PV210_PA_SPI0 0xE1300000
@@ -72,16 +74,9 @@
72#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) 74#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
73 75
74#define S5PV210_PA_VIC0 (0xF2000000) 76#define S5PV210_PA_VIC0 (0xF2000000)
75#define S5P_PA_VIC0 S5PV210_PA_VIC0
76
77#define S5PV210_PA_VIC1 (0xF2100000) 77#define S5PV210_PA_VIC1 (0xF2100000)
78#define S5P_PA_VIC1 S5PV210_PA_VIC1
79
80#define S5PV210_PA_VIC2 (0xF2200000) 78#define S5PV210_PA_VIC2 (0xF2200000)
81#define S5P_PA_VIC2 S5PV210_PA_VIC2
82
83#define S5PV210_PA_VIC3 (0xF2300000) 79#define S5PV210_PA_VIC3 (0xF2300000)
84#define S5P_PA_VIC3 S5PV210_PA_VIC3
85 80
86#define S5PV210_PA_SDRAM (0x20000000) 81#define S5PV210_PA_SDRAM (0x20000000)
87#define S5P_PA_SDRAM S5PV210_PA_SDRAM 82#define S5P_PA_SDRAM S5PV210_PA_SDRAM
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 0dda8012d6b2..bf772de6b0c3 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -477,7 +477,7 @@ static struct platform_device *aquila_devices[] __initdata = {
477 &aquila_i2c_gpio_pmic, 477 &aquila_i2c_gpio_pmic,
478 &aquila_device_gpiokeys, 478 &aquila_device_gpiokeys,
479 &s3c_device_fb, 479 &s3c_device_fb,
480 &s5pc110_device_onenand, 480 &s5p_device_onenand,
481 &s3c_device_hsmmc0, 481 &s3c_device_hsmmc0,
482 &s3c_device_hsmmc1, 482 &s3c_device_hsmmc1,
483 &s3c_device_hsmmc2, 483 &s3c_device_hsmmc2,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 53754d7d364e..fdc5cca4eb41 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -456,7 +456,7 @@ static void goni_setup_sdhci(void)
456 456
457static struct platform_device *goni_devices[] __initdata = { 457static struct platform_device *goni_devices[] __initdata = {
458 &s3c_device_fb, 458 &s3c_device_fb,
459 &s5pc110_device_onenand, 459 &s5p_device_onenand,
460 &goni_i2c_gpio_pmic, 460 &goni_i2c_gpio_pmic,
461 &goni_device_gpiokeys, 461 &goni_device_gpiokeys,
462 &s5p_device_fimc0, 462 &s5p_device_fimc0,
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index e5b261a99ab2..4add39853ff9 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -31,9 +31,14 @@ extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
31/* Initial IO mappings */ 31/* Initial IO mappings */
32static struct map_desc s5pv310_iodesc[] __initdata = { 32static struct map_desc s5pv310_iodesc[] __initdata = {
33 { 33 {
34 .virtual = (unsigned long)S5P_VA_COREPERI_BASE, 34 .virtual = (unsigned long)S5P_VA_SYSRAM,
35 .pfn = __phys_to_pfn(S5PV310_PA_COREPERI), 35 .pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
36 .length = SZ_8K, 36 .length = SZ_4K,
37 .type = MT_DEVICE,
38 }, {
39 .virtual = (unsigned long)S5P_VA_CMU,
40 .pfn = __phys_to_pfn(S5PV310_PA_CMU),
41 .length = SZ_128K,
37 .type = MT_DEVICE, 42 .type = MT_DEVICE,
38 }, { 43 }, {
39 .virtual = (unsigned long)S5P_VA_COMBINER_BASE, 44 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
@@ -41,19 +46,24 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
41 .length = SZ_4K, 46 .length = SZ_4K,
42 .type = MT_DEVICE, 47 .type = MT_DEVICE,
43 }, { 48 }, {
49 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
50 .pfn = __phys_to_pfn(S5PV310_PA_COREPERI),
51 .length = SZ_8K,
52 .type = MT_DEVICE,
53 }, {
44 .virtual = (unsigned long)S5P_VA_L2CC, 54 .virtual = (unsigned long)S5P_VA_L2CC,
45 .pfn = __phys_to_pfn(S5PV310_PA_L2CC), 55 .pfn = __phys_to_pfn(S5PV310_PA_L2CC),
46 .length = SZ_4K, 56 .length = SZ_4K,
47 .type = MT_DEVICE, 57 .type = MT_DEVICE,
48 }, { 58 }, {
49 .virtual = (unsigned long)S5P_VA_SYSRAM, 59 .virtual = (unsigned long)S5P_VA_GPIO,
50 .pfn = __phys_to_pfn(S5PV310_PA_SYSRAM), 60 .pfn = __phys_to_pfn(S5PV310_PA_GPIO1),
51 .length = SZ_4K, 61 .length = SZ_4K,
52 .type = MT_DEVICE, 62 .type = MT_DEVICE,
53 }, { 63 }, {
54 .virtual = (unsigned long)S5P_VA_CMU, 64 .virtual = (unsigned long)S3C_VA_UART,
55 .pfn = __phys_to_pfn(S5PV310_PA_CMU), 65 .pfn = __phys_to_pfn(S3C_PA_UART),
56 .length = SZ_128K, 66 .length = SZ_512K,
57 .type = MT_DEVICE, 67 .type = MT_DEVICE,
58 }, 68 },
59}; 69};
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
index 4cdedda6e652..471fc3bb199a 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -68,6 +68,8 @@
68 68
69#define IRQ_IIC COMBINER_IRQ(27, 0) 69#define IRQ_IIC COMBINER_IRQ(27, 0)
70 70
71#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
72
71/* Set the default NR_IRQS */ 73/* Set the default NR_IRQS */
72 74
73#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0) 75#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0)
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 213e1101a3b3..aff6d23624bb 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -25,6 +25,12 @@
25 25
26#define S5PV310_PA_SYSRAM (0x02025000) 26#define S5PV310_PA_SYSRAM (0x02025000)
27 27
28#define S5PC210_PA_ONENAND (0x0C000000)
29#define S5P_PA_ONENAND S5PC210_PA_ONENAND
30
31#define S5PC210_PA_ONENAND_DMA (0x0C600000)
32#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
33
28#define S5PV310_PA_CHIPID (0x10000000) 34#define S5PV310_PA_CHIPID (0x10000000)
29#define S5P_PA_CHIPID S5PV310_PA_CHIPID 35#define S5P_PA_CHIPID S5PV310_PA_CHIPID
30 36
@@ -46,7 +52,6 @@
46#define S5PV310_PA_GPIO1 (0x11400000) 52#define S5PV310_PA_GPIO1 (0x11400000)
47#define S5PV310_PA_GPIO2 (0x11000000) 53#define S5PV310_PA_GPIO2 (0x11000000)
48#define S5PV310_PA_GPIO3 (0x03860000) 54#define S5PV310_PA_GPIO3 (0x03860000)
49#define S5P_PA_GPIO S5PV310_PA_GPIO1
50 55
51#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 56#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
52 57
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index efb127022d42..71fb17349520 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -68,7 +68,7 @@ static void __init ct_ca9x4_init_irq(void)
68} 68}
69 69
70#if 0 70#if 0
71static void ct_ca9x4_timer_init(void) 71static void __init ct_ca9x4_timer_init(void)
72{ 72{
73 writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL); 73 writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
74 writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL); 74 writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
@@ -222,7 +222,7 @@ static struct platform_device pmu_device = {
222 .resource = pmu_resources, 222 .resource = pmu_resources,
223}; 223};
224 224
225static void ct_ca9x4_init(void) 225static void __init ct_ca9x4_init(void)
226{ 226{
227 int i; 227 int i;
228 228
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 817f0ad38a0b..7eaa232180a5 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -48,7 +48,7 @@ void __init v2m_map_io(struct map_desc *tile, size_t num)
48} 48}
49 49
50 50
51static void v2m_timer_init(void) 51static void __init v2m_timer_init(void)
52{ 52{
53 writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL); 53 writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
54 writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL); 54 writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index ab506272b2d3..17e7b0b57e49 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -204,8 +204,12 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
204 /* 204 /*
205 * Don't allow RAM to be mapped - this causes problems with ARMv6+ 205 * Don't allow RAM to be mapped - this causes problems with ARMv6+
206 */ 206 */
207 if (WARN_ON(pfn_valid(pfn))) 207 if (pfn_valid(pfn)) {
208 return NULL; 208 printk(KERN_WARNING "BUG: Your driver calls ioremap() on system memory. This leads\n"
209 KERN_WARNING "to architecturally unpredictable behaviour on ARMv6+, and ioremap()\n"
210 KERN_WARNING "will fail in the next kernel release. Please fix your driver.\n");
211 WARN_ON(1);
212 }
209 213
210 type = get_mem_type(mtype); 214 type = get_mem_type(mtype);
211 if (!type) 215 if (!type)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6a3a2d0cd6db..e8ed9dc461fe 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -248,7 +248,7 @@ static struct mem_type mem_types[] = {
248 }, 248 },
249 [MT_MEMORY] = { 249 [MT_MEMORY] = {
250 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 250 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
251 L_PTE_USER | L_PTE_EXEC, 251 L_PTE_WRITE | L_PTE_EXEC,
252 .prot_l1 = PMD_TYPE_TABLE, 252 .prot_l1 = PMD_TYPE_TABLE,
253 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 253 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
254 .domain = DOMAIN_KERNEL, 254 .domain = DOMAIN_KERNEL,
@@ -259,7 +259,7 @@ static struct mem_type mem_types[] = {
259 }, 259 },
260 [MT_MEMORY_NONCACHED] = { 260 [MT_MEMORY_NONCACHED] = {
261 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 261 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
262 L_PTE_USER | L_PTE_EXEC | L_PTE_MT_BUFFERABLE, 262 L_PTE_WRITE | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
263 .prot_l1 = PMD_TYPE_TABLE, 263 .prot_l1 = PMD_TYPE_TABLE,
264 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 264 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
265 .domain = DOMAIN_KERNEL, 265 .domain = DOMAIN_KERNEL,
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7563ff0141bd..197f21bed5e9 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -253,6 +253,14 @@ __v7_setup:
253 orreq r10, r10, #1 << 22 @ set bit #22 253 orreq r10, r10, #1 << 22 @ set bit #22
254 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 254 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
255#endif 255#endif
256#ifdef CONFIG_ARM_ERRATA_743622
257 teq r6, #0x20 @ present in r2p0
258 teqne r6, #0x21 @ present in r2p1
259 teqne r6, #0x22 @ present in r2p2
260 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
261 orreq r10, r10, #1 << 6 @ set bit #6
262 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
263#endif
256 264
2573: mov r10, #0 2653: mov r10, #0
258#ifdef HARVARD_CACHE 266#ifdef HARVARD_CACHE
@@ -365,7 +373,7 @@ __v7_ca9mp_proc_info:
365 b __v7_ca9mp_setup 373 b __v7_ca9mp_setup
366 .long cpu_arch_name 374 .long cpu_arch_name
367 .long cpu_elf_name 375 .long cpu_elf_name
368 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 376 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
369 .long cpu_v7_name 377 .long cpu_v7_name
370 .long v7_processor_functions 378 .long v7_processor_functions
371 .long v7wbi_tlb_fns 379 .long v7wbi_tlb_fns
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index a202a2ce6e3d..6cd151b31bc5 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -320,6 +320,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
320 if ((start <= da) && (da < start + bytes)) { 320 if ((start <= da) && (da < start + bytes)) {
321 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", 321 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
322 __func__, start, da, bytes); 322 __func__, start, da, bytes);
323 iotlb_load_cr(obj, &cr);
323 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); 324 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
324 } 325 }
325 } 326 }
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index c6a855db2fb6..25960966af7c 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -7,7 +7,7 @@
7 7
8config PLAT_S5P 8config PLAT_S5P
9 bool 9 bool
10 depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310) 10 depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310)
11 default y 11 default y
12 select ARM_VIC if !ARCH_S5PV310 12 select ARM_VIC if !ARCH_S5PV310
13 select ARM_GIC if ARCH_S5PV310 13 select ARM_GIC if ARCH_S5PV310
@@ -30,7 +30,7 @@ config S5P_EXT_INT
30 bool 30 bool
31 help 31 help
32 Use the external interrupts (other than GPIO interrupts.) 32 Use the external interrupts (other than GPIO interrupts.)
33 Note: Do not choose this for S5P6440. 33 Note: Do not choose this for S5P6440 and S5P6450.
34 34
35config S5P_DEV_FIMC0 35config S5P_DEV_FIMC0
36 bool 36 bool
@@ -46,3 +46,8 @@ config S5P_DEV_FIMC2
46 bool 46 bool
47 help 47 help
48 Compile in platform device definitions for FIMC controller 2 48 Compile in platform device definitions for FIMC controller 2
49
50config S5P_DEV_ONENAND
51 bool
52 help
53 Compile in platform device definition for OneNAND controller
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index b2e029673950..f3e917e27da8 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
24obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o 24obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o
25obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o 25obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o
26obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o 26obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o
27obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index b5e255265f20..8aaf4e6b60c3 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -74,6 +74,13 @@ struct clk clk_fout_epll = {
74 .ctrlbit = (1 << 31), 74 .ctrlbit = (1 << 31),
75}; 75};
76 76
77/* DPLL clock output */
78struct clk clk_fout_dpll = {
79 .name = "fout_dpll",
80 .id = -1,
81 .ctrlbit = (1 << 31),
82};
83
77/* VPLL clock output */ 84/* VPLL clock output */
78struct clk clk_fout_vpll = { 85struct clk clk_fout_vpll = {
79 .name = "fout_vpll", 86 .name = "fout_vpll",
@@ -122,6 +129,17 @@ struct clksrc_sources clk_src_epll = {
122 .nr_sources = ARRAY_SIZE(clk_src_epll_list), 129 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
123}; 130};
124 131
132/* Possible clock sources for DPLL Mux */
133static struct clk *clk_src_dpll_list[] = {
134 [0] = &clk_fin_dpll,
135 [1] = &clk_fout_dpll,
136};
137
138struct clksrc_sources clk_src_dpll = {
139 .sources = clk_src_dpll_list,
140 .nr_sources = ARRAY_SIZE(clk_src_dpll_list),
141};
142
125struct clk clk_vpll = { 143struct clk clk_vpll = {
126 .name = "vpll", 144 .name = "vpll",
127 .id = -1, 145 .id = -1,
@@ -145,6 +163,7 @@ static struct clk *s5p_clks[] __initdata = {
145 &clk_fout_apll, 163 &clk_fout_apll,
146 &clk_fout_mpll, 164 &clk_fout_mpll,
147 &clk_fout_epll, 165 &clk_fout_epll,
166 &clk_fout_dpll,
148 &clk_fout_vpll, 167 &clk_fout_vpll,
149 &clk_arm, 168 &clk_arm,
150 &clk_vpll, 169 &clk_vpll,
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index b07a078fd284..74f7f5a5446c 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -19,6 +19,7 @@
19#include <plat/cpu.h> 19#include <plat/cpu.h>
20#include <plat/s5p6440.h> 20#include <plat/s5p6440.h>
21#include <plat/s5p6442.h> 21#include <plat/s5p6442.h>
22#include <plat/s5p6450.h>
22#include <plat/s5pc100.h> 23#include <plat/s5pc100.h>
23#include <plat/s5pv210.h> 24#include <plat/s5pv210.h>
24#include <plat/s5pv310.h> 25#include <plat/s5pv310.h>
@@ -27,6 +28,7 @@
27 28
28static const char name_s5p6440[] = "S5P6440"; 29static const char name_s5p6440[] = "S5P6440";
29static const char name_s5p6442[] = "S5P6442"; 30static const char name_s5p6442[] = "S5P6442";
31static const char name_s5p6450[] = "S5P6450";
30static const char name_s5pc100[] = "S5PC100"; 32static const char name_s5pc100[] = "S5PC100";
31static const char name_s5pv210[] = "S5PV210/S5PC110"; 33static const char name_s5pv210[] = "S5PV210/S5PC110";
32static const char name_s5pv310[] = "S5PV310"; 34static const char name_s5pv310[] = "S5PV310";
@@ -38,7 +40,7 @@ static struct cpu_table cpu_ids[] __initdata = {
38 .map_io = s5p6440_map_io, 40 .map_io = s5p6440_map_io,
39 .init_clocks = s5p6440_init_clocks, 41 .init_clocks = s5p6440_init_clocks,
40 .init_uarts = s5p6440_init_uarts, 42 .init_uarts = s5p6440_init_uarts,
41 .init = s5p6440_init, 43 .init = s5p64x0_init,
42 .name = name_s5p6440, 44 .name = name_s5p6440,
43 }, { 45 }, {
44 .idcode = 0x36442000, 46 .idcode = 0x36442000,
@@ -49,6 +51,14 @@ static struct cpu_table cpu_ids[] __initdata = {
49 .init = s5p6442_init, 51 .init = s5p6442_init,
50 .name = name_s5p6442, 52 .name = name_s5p6442,
51 }, { 53 }, {
54 .idcode = 0x36450000,
55 .idmask = 0xffffff00,
56 .map_io = s5p6450_map_io,
57 .init_clocks = s5p6450_init_clocks,
58 .init_uarts = s5p6450_init_uarts,
59 .init = s5p64x0_init,
60 .name = name_s5p6450,
61 }, {
52 .idcode = 0x43100000, 62 .idcode = 0x43100000,
53 .idmask = 0xfffff000, 63 .idmask = 0xfffff000,
54 .map_io = s5pc100_map_io, 64 .map_io = s5pc100_map_io,
@@ -89,33 +99,11 @@ static struct map_desc s5p_iodesc[] __initdata = {
89 .length = SZ_64K, 99 .length = SZ_64K,
90 .type = MT_DEVICE, 100 .type = MT_DEVICE,
91 }, { 101 }, {
92 .virtual = (unsigned long)S3C_VA_UART,
93 .pfn = __phys_to_pfn(S3C_PA_UART),
94 .length = SZ_512K,
95 .type = MT_DEVICE,
96#ifdef CONFIG_ARM_VIC
97 }, {
98 .virtual = (unsigned long)VA_VIC0,
99 .pfn = __phys_to_pfn(S5P_PA_VIC0),
100 .length = SZ_16K,
101 .type = MT_DEVICE,
102 }, {
103 .virtual = (unsigned long)VA_VIC1,
104 .pfn = __phys_to_pfn(S5P_PA_VIC1),
105 .length = SZ_16K,
106 .type = MT_DEVICE,
107#endif
108 }, {
109 .virtual = (unsigned long)S3C_VA_TIMER, 102 .virtual = (unsigned long)S3C_VA_TIMER,
110 .pfn = __phys_to_pfn(S5P_PA_TIMER), 103 .pfn = __phys_to_pfn(S5P_PA_TIMER),
111 .length = SZ_16K, 104 .length = SZ_16K,
112 .type = MT_DEVICE, 105 .type = MT_DEVICE,
113 }, { 106 }, {
114 .virtual = (unsigned long)S5P_VA_GPIO,
115 .pfn = __phys_to_pfn(S5P_PA_GPIO),
116 .length = SZ_4K,
117 .type = MT_DEVICE,
118 }, {
119 .virtual = (unsigned long)S3C_VA_WATCHDOG, 107 .virtual = (unsigned long)S3C_VA_WATCHDOG,
120 .pfn = __phys_to_pfn(S3C_PA_WDT), 108 .pfn = __phys_to_pfn(S3C_PA_WDT),
121 .length = SZ_4K, 109 .length = SZ_4K,
diff --git a/arch/arm/mach-s5pv210/dev-onenand.c b/arch/arm/plat-s5p/dev-onenand.c
index f8ede33ee82b..6db926202caa 100644
--- a/arch/arm/mach-s5pv210/dev-onenand.c
+++ b/arch/arm/plat-s5p/dev-onenand.c
@@ -1,10 +1,12 @@
1/* 1/* linux/arch/arm/plat-s5p/dev-onenand.c
2 * linux/arch/arm/mach-s5pv210/dev-onenand.c 2 *
3 * Copyright 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
3 * 5 *
4 * Copyright (c) 2008-2010 Samsung Electronics 6 * Copyright (c) 2008-2010 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com> 7 * Kyungmin Park <kyungmin.park@samsung.com>
6 * 8 *
7 * S5PC110 series device definition for OneNAND devices 9 * S5P series device definition for OneNAND devices
8 * 10 *
9 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
@@ -19,15 +21,15 @@
19#include <mach/irqs.h> 21#include <mach/irqs.h>
20#include <mach/map.h> 22#include <mach/map.h>
21 23
22static struct resource s5pc110_onenand_resources[] = { 24static struct resource s5p_onenand_resources[] = {
23 [0] = { 25 [0] = {
24 .start = S5PC110_PA_ONENAND, 26 .start = S5P_PA_ONENAND,
25 .end = S5PC110_PA_ONENAND + SZ_128K - 1, 27 .end = S5P_PA_ONENAND + SZ_128K - 1,
26 .flags = IORESOURCE_MEM, 28 .flags = IORESOURCE_MEM,
27 }, 29 },
28 [1] = { 30 [1] = {
29 .start = S5PC110_PA_ONENAND_DMA, 31 .start = S5P_PA_ONENAND_DMA,
30 .end = S5PC110_PA_ONENAND_DMA + SZ_8K - 1, 32 .end = S5P_PA_ONENAND_DMA + SZ_8K - 1,
31 .flags = IORESOURCE_MEM, 33 .flags = IORESOURCE_MEM,
32 }, 34 },
33 [2] = { 35 [2] = {
@@ -37,19 +39,19 @@ static struct resource s5pc110_onenand_resources[] = {
37 }, 39 },
38}; 40};
39 41
40struct platform_device s5pc110_device_onenand = { 42struct platform_device s5p_device_onenand = {
41 .name = "s5pc110-onenand", 43 .name = "s5pc110-onenand",
42 .id = -1, 44 .id = -1,
43 .num_resources = ARRAY_SIZE(s5pc110_onenand_resources), 45 .num_resources = ARRAY_SIZE(s5p_onenand_resources),
44 .resource = s5pc110_onenand_resources, 46 .resource = s5p_onenand_resources,
45}; 47};
46 48
47void s5pc110_onenand_set_platdata(struct onenand_platform_data *pdata) 49void s5p_onenand_set_platdata(struct onenand_platform_data *pdata)
48{ 50{
49 struct onenand_platform_data *pd; 51 struct onenand_platform_data *pd;
50 52
51 pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL); 53 pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL);
52 if (!pd) 54 if (!pd)
53 printk(KERN_ERR "%s: no memory for platform data\n", __func__); 55 printk(KERN_ERR "%s: no memory for platform data\n", __func__);
54 s5pc110_device_onenand.dev.platform_data = pd; 56 s5p_device_onenand.dev.platform_data = pd;
55} 57}
diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c
index a89331ef4ae1..6a7342886171 100644
--- a/arch/arm/plat-s5p/dev-uart.c
+++ b/arch/arm/plat-s5p/dev-uart.c
@@ -119,6 +119,56 @@ static struct resource s5p_uart3_resource[] = {
119#endif 119#endif
120}; 120};
121 121
122static struct resource s5p_uart4_resource[] = {
123#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
124 [0] = {
125 .start = S5P_PA_UART4,
126 .end = S5P_PA_UART4 + S5P_SZ_UART,
127 .flags = IORESOURCE_MEM,
128 },
129 [1] = {
130 .start = IRQ_S5P_UART_RX4,
131 .end = IRQ_S5P_UART_RX4,
132 .flags = IORESOURCE_IRQ,
133 },
134 [2] = {
135 .start = IRQ_S5P_UART_TX4,
136 .end = IRQ_S5P_UART_TX4,
137 .flags = IORESOURCE_IRQ,
138 },
139 [3] = {
140 .start = IRQ_S5P_UART_ERR4,
141 .end = IRQ_S5P_UART_ERR4,
142 .flags = IORESOURCE_IRQ,
143 },
144#endif
145};
146
147static struct resource s5p_uart5_resource[] = {
148#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
149 [0] = {
150 .start = S5P_PA_UART5,
151 .end = S5P_PA_UART5 + S5P_SZ_UART,
152 .flags = IORESOURCE_MEM,
153 },
154 [1] = {
155 .start = IRQ_S5P_UART_RX5,
156 .end = IRQ_S5P_UART_RX5,
157 .flags = IORESOURCE_IRQ,
158 },
159 [2] = {
160 .start = IRQ_S5P_UART_TX5,
161 .end = IRQ_S5P_UART_TX5,
162 .flags = IORESOURCE_IRQ,
163 },
164 [3] = {
165 .start = IRQ_S5P_UART_ERR5,
166 .end = IRQ_S5P_UART_ERR5,
167 .flags = IORESOURCE_IRQ,
168 },
169#endif
170};
171
122struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = { 172struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
123 [0] = { 173 [0] = {
124 .resources = s5p_uart0_resource, 174 .resources = s5p_uart0_resource,
@@ -136,4 +186,12 @@ struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
136 .resources = s5p_uart3_resource, 186 .resources = s5p_uart3_resource,
137 .nr_resources = ARRAY_SIZE(s5p_uart3_resource), 187 .nr_resources = ARRAY_SIZE(s5p_uart3_resource),
138 }, 188 },
189 [4] = {
190 .resources = s5p_uart4_resource,
191 .nr_resources = ARRAY_SIZE(s5p_uart4_resource),
192 },
193 [5] = {
194 .resources = s5p_uart5_resource,
195 .nr_resources = ARRAY_SIZE(s5p_uart5_resource),
196 },
139}; 197};
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
index 4e8fe08cb70d..bf28fadee7ae 100644
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -47,6 +47,7 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
47} 47}
48 48
49#define PLL46XX_KDIV_MASK (0xFFFF) 49#define PLL46XX_KDIV_MASK (0xFFFF)
50#define PLL4650C_KDIV_MASK (0xFFF)
50#define PLL46XX_MDIV_MASK (0x1FF) 51#define PLL46XX_MDIV_MASK (0x1FF)
51#define PLL46XX_PDIV_MASK (0x3F) 52#define PLL46XX_PDIV_MASK (0x3F)
52#define PLL46XX_SDIV_MASK (0x7) 53#define PLL46XX_SDIV_MASK (0x7)
@@ -57,6 +58,7 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
57enum pll46xx_type_t { 58enum pll46xx_type_t {
58 pll_4600, 59 pll_4600,
59 pll_4650, 60 pll_4650,
61 pll_4650c,
60}; 62};
61 63
62static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, 64static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
@@ -72,6 +74,11 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
72 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; 74 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
73 kdiv = pll_con1 & PLL46XX_KDIV_MASK; 75 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
74 76
77 if (pll_type == pll_4650c)
78 kdiv = pll_con1 & PLL4650C_KDIV_MASK;
79 else
80 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
81
75 tmp = baseclk; 82 tmp = baseclk;
76 83
77 if (pll_type == pll_4600) { 84 if (pll_type == pll_4600) {
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h
index 09418b1101fe..17036c898409 100644
--- a/arch/arm/plat-s5p/include/plat/s5p-clock.h
+++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h
@@ -1,7 +1,7 @@
1/* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h 1/* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h
2 * 2 *
3 * Copyright 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Header file for s5p clock support 6 * Header file for s5p clock support
7 * 7 *
@@ -20,6 +20,7 @@
20#define clk_fin_apll clk_ext_xtal_mux 20#define clk_fin_apll clk_ext_xtal_mux
21#define clk_fin_mpll clk_ext_xtal_mux 21#define clk_fin_mpll clk_ext_xtal_mux
22#define clk_fin_epll clk_ext_xtal_mux 22#define clk_fin_epll clk_ext_xtal_mux
23#define clk_fin_dpll clk_ext_xtal_mux
23#define clk_fin_vpll clk_ext_xtal_mux 24#define clk_fin_vpll clk_ext_xtal_mux
24#define clk_fin_hpll clk_ext_xtal_mux 25#define clk_fin_hpll clk_ext_xtal_mux
25 26
@@ -30,6 +31,7 @@ extern struct clk s5p_clk_27m;
30extern struct clk clk_fout_apll; 31extern struct clk clk_fout_apll;
31extern struct clk clk_fout_mpll; 32extern struct clk clk_fout_mpll;
32extern struct clk clk_fout_epll; 33extern struct clk clk_fout_epll;
34extern struct clk clk_fout_dpll;
33extern struct clk clk_fout_vpll; 35extern struct clk clk_fout_vpll;
34extern struct clk clk_arm; 36extern struct clk clk_arm;
35extern struct clk clk_vpll; 37extern struct clk clk_vpll;
@@ -37,8 +39,8 @@ extern struct clk clk_vpll;
37extern struct clksrc_sources clk_src_apll; 39extern struct clksrc_sources clk_src_apll;
38extern struct clksrc_sources clk_src_mpll; 40extern struct clksrc_sources clk_src_mpll;
39extern struct clksrc_sources clk_src_epll; 41extern struct clksrc_sources clk_src_epll;
42extern struct clksrc_sources clk_src_dpll;
40 43
41extern int s5p6440_clk48m_ctrl(struct clk *clk, int enable);
42extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable); 44extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
43 45
44#endif /* __ASM_PLAT_S5P_CLOCK_H */ 46#endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-s5p/include/plat/s5p6440.h b/arch/arm/plat-s5p/include/plat/s5p6440.h
index a4cd75afeb3b..528585d2cafc 100644
--- a/arch/arm/plat-s5p/include/plat/s5p6440.h
+++ b/arch/arm/plat-s5p/include/plat/s5p6440.h
@@ -12,24 +12,23 @@
12 12
13 /* Common init code for S5P6440 related SoCs */ 13 /* Common init code for S5P6440 related SoCs */
14 14
15extern void s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void s5p6440_register_clocks(void); 15extern void s5p6440_register_clocks(void);
17extern void s5p6440_setup_clocks(void); 16extern void s5p6440_setup_clocks(void);
18 17
19#ifdef CONFIG_CPU_S5P6440 18#ifdef CONFIG_CPU_S5P6440
20 19
21extern int s5p6440_init(void); 20extern int s5p64x0_init(void);
22extern void s5p6440_init_irq(void); 21extern void s5p6440_init_irq(void);
23extern void s5p6440_map_io(void); 22extern void s5p6440_map_io(void);
24extern void s5p6440_init_clocks(int xtal); 23extern void s5p6440_init_clocks(int xtal);
25 24
26#define s5p6440_init_uarts s5p6440_common_init_uarts 25extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
27 26
28#else 27#else
29#define s5p6440_init_clocks NULL 28#define s5p6440_init_clocks NULL
30#define s5p6440_init_uarts NULL 29#define s5p6440_init_uarts NULL
31#define s5p6440_map_io NULL 30#define s5p6440_map_io NULL
32#define s5p6440_init NULL 31#define s5p64x0_init NULL
33#endif 32#endif
34 33
35/* S5P6440 timer */ 34/* S5P6440 timer */
diff --git a/arch/arm/plat-s5p/include/plat/s5p6450.h b/arch/arm/plat-s5p/include/plat/s5p6450.h
new file mode 100644
index 000000000000..640a41c26be3
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5p6450.h
@@ -0,0 +1,36 @@
1/* arch/arm/plat-s5p/include/plat/s5p6450.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for s5p6450 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5P6450 related SoCs */
14
15extern void s5p6450_register_clocks(void);
16extern void s5p6450_setup_clocks(void);
17
18#ifdef CONFIG_CPU_S5P6450
19
20extern int s5p64x0_init(void);
21extern void s5p6450_init_irq(void);
22extern void s5p6450_map_io(void);
23extern void s5p6450_init_clocks(int xtal);
24
25extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
26
27#else
28#define s5p6450_init_clocks NULL
29#define s5p6450_init_uarts NULL
30#define s5p6450_map_io NULL
31#define s5p64x0_init NULL
32#endif
33
34/* S5P6450 timer */
35
36extern struct sys_timer s5p6450_timer;
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 04d9521ddc9f..e8f2be2d67f2 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -435,7 +435,6 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
435static int s3c_adc_resume(struct platform_device *pdev) 435static int s3c_adc_resume(struct platform_device *pdev)
436{ 436{
437 struct adc_device *adc = platform_get_drvdata(pdev); 437 struct adc_device *adc = platform_get_drvdata(pdev);
438 unsigned long flags;
439 438
440 clk_enable(adc->clk); 439 clk_enable(adc->clk);
441 enable_irq(adc->irq); 440 enable_irq(adc->irq);
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 90a20512d68d..e8d20b0bc50e 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -48,6 +48,9 @@
48#include <plat/clock.h> 48#include <plat/clock.h>
49#include <plat/cpu.h> 49#include <plat/cpu.h>
50 50
51#include <linux/serial_core.h>
52#include <plat/regs-serial.h> /* for s3c24xx_uart_devs */
53
51/* clock information */ 54/* clock information */
52 55
53static LIST_HEAD(clocks); 56static LIST_HEAD(clocks);
@@ -65,6 +68,28 @@ static int clk_null_enable(struct clk *clk, int enable)
65 return 0; 68 return 0;
66} 69}
67 70
71static int dev_is_s3c_uart(struct device *dev)
72{
73 struct platform_device **pdev = s3c24xx_uart_devs;
74 int i;
75 for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++)
76 if (*pdev && dev == &(*pdev)->dev)
77 return 1;
78 return 0;
79}
80
81/*
82 * Serial drivers call get_clock() very early, before platform bus
83 * has been set up, this requires a special check to let them get
84 * a proper clock
85 */
86
87static int dev_is_platform_device(struct device *dev)
88{
89 return dev->bus == &platform_bus_type ||
90 (dev->bus == NULL && dev_is_s3c_uart(dev));
91}
92
68/* Clock API calls */ 93/* Clock API calls */
69 94
70struct clk *clk_get(struct device *dev, const char *id) 95struct clk *clk_get(struct device *dev, const char *id)
@@ -73,7 +98,7 @@ struct clk *clk_get(struct device *dev, const char *id)
73 struct clk *clk = ERR_PTR(-ENOENT); 98 struct clk *clk = ERR_PTR(-ENOENT);
74 int idno; 99 int idno;
75 100
76 if (dev == NULL || dev->bus != &platform_bus_type) 101 if (dev == NULL || !dev_is_platform_device(dev))
77 idno = -1; 102 idno = -1;
78 else 103 else
79 idno = to_platform_device(dev)->id; 104 idno = to_platform_device(dev)->id;
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 6412933d6fbb..9addb3dfb4bc 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -79,7 +79,7 @@ extern struct sysdev_class s3c2442_sysclass;
79extern struct sysdev_class s3c2443_sysclass; 79extern struct sysdev_class s3c2443_sysclass;
80extern struct sysdev_class s3c6410_sysclass; 80extern struct sysdev_class s3c6410_sysclass;
81extern struct sysdev_class s3c64xx_sysclass; 81extern struct sysdev_class s3c64xx_sysclass;
82extern struct sysdev_class s5p6440_sysclass; 82extern struct sysdev_class s5p64x0_sysclass;
83extern struct sysdev_class s5p6442_sysclass; 83extern struct sysdev_class s5p6442_sysclass;
84extern struct sysdev_class s5pv210_sysclass; 84extern struct sysdev_class s5pv210_sysclass;
85 85
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 85f6f23a510f..7d448e138792 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -67,13 +67,15 @@ extern struct platform_device s5pv210_device_spi0;
67extern struct platform_device s5pv210_device_spi1; 67extern struct platform_device s5pv210_device_spi1;
68extern struct platform_device s5p6440_device_spi0; 68extern struct platform_device s5p6440_device_spi0;
69extern struct platform_device s5p6440_device_spi1; 69extern struct platform_device s5p6440_device_spi1;
70extern struct platform_device s5p6450_device_spi0;
71extern struct platform_device s5p6450_device_spi1;
70 72
71extern struct platform_device s3c_device_hwmon; 73extern struct platform_device s3c_device_hwmon;
72 74
73extern struct platform_device s3c_device_nand; 75extern struct platform_device s3c_device_nand;
74extern struct platform_device s3c_device_onenand; 76extern struct platform_device s3c_device_onenand;
75extern struct platform_device s3c64xx_device_onenand1; 77extern struct platform_device s3c64xx_device_onenand1;
76extern struct platform_device s5pc110_device_onenand; 78extern struct platform_device s5p_device_onenand;
77 79
78extern struct platform_device s3c_device_usbgadget; 80extern struct platform_device s3c_device_usbgadget;
79extern struct platform_device s3c_device_usb_hsotg; 81extern struct platform_device s3c_device_usb_hsotg;
@@ -95,6 +97,9 @@ extern struct platform_device s5p6442_device_spi;
95extern struct platform_device s5p6440_device_pcm; 97extern struct platform_device s5p6440_device_pcm;
96extern struct platform_device s5p6440_device_iis; 98extern struct platform_device s5p6440_device_iis;
97 99
100extern struct platform_device s5p6450_device_iis0;
101extern struct platform_device s5p6450_device_pcm0;
102
98extern struct platform_device s5pc100_device_ac97; 103extern struct platform_device s5pc100_device_ac97;
99extern struct platform_device s5pc100_device_pcm0; 104extern struct platform_device s5pc100_device_pcm0;
100extern struct platform_device s5pc100_device_pcm1; 105extern struct platform_device s5pc100_device_pcm1;
diff --git a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
index 5fe6721b57f7..810744213120 100644
--- a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
@@ -32,6 +32,12 @@ enum dma_ch {
32 DMACH_UART2_TX, 32 DMACH_UART2_TX,
33 DMACH_UART3_RX, 33 DMACH_UART3_RX,
34 DMACH_UART3_TX, 34 DMACH_UART3_TX,
35 DMACH_UART4_RX,
36 DMACH_UART4_TX,
37 DMACH_UART5_RX,
38 DMACH_UART5_TX,
39 DMACH_USI_RX,
40 DMACH_USI_TX,
35 DMACH_IRDA, 41 DMACH_IRDA,
36 DMACH_I2S0_RX, 42 DMACH_I2S0_RX,
37 DMACH_I2S0_TX, 43 DMACH_I2S0_TX,
@@ -64,6 +70,20 @@ enum dma_ch {
64 DMACH_MSM_REQ2, 70 DMACH_MSM_REQ2,
65 DMACH_MSM_REQ1, 71 DMACH_MSM_REQ1,
66 DMACH_MSM_REQ0, 72 DMACH_MSM_REQ0,
73 DMACH_SLIMBUS0_RX,
74 DMACH_SLIMBUS0_TX,
75 DMACH_SLIMBUS0AUX_RX,
76 DMACH_SLIMBUS0AUX_TX,
77 DMACH_SLIMBUS1_RX,
78 DMACH_SLIMBUS1_TX,
79 DMACH_SLIMBUS2_RX,
80 DMACH_SLIMBUS2_TX,
81 DMACH_SLIMBUS3_RX,
82 DMACH_SLIMBUS3_TX,
83 DMACH_SLIMBUS4_RX,
84 DMACH_SLIMBUS4_TX,
85 DMACH_SLIMBUS5_RX,
86 DMACH_SLIMBUS5_TX,
67 /* END Marker, also used to denote a reserved channel */ 87 /* END Marker, also used to denote a reserved channel */
68 DMACH_MAX, 88 DMACH_MAX,
69}; 89};
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index e5aba8f95b79..ae8e802bdca8 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -65,7 +65,7 @@ struct s3c64xx_spi_info {
65extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 65extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
66extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 66extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
67extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 67extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
68extern void s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 68extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
69extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 69extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
70 70
71#endif /* __S3C64XX_PLAT_SPI_H */ 71#endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/mips/include/asm/siginfo.h b/arch/mips/include/asm/siginfo.h
index 96e28f18dad1..1ca64b4d33d9 100644
--- a/arch/mips/include/asm/siginfo.h
+++ b/arch/mips/include/asm/siginfo.h
@@ -88,6 +88,7 @@ typedef struct siginfo {
88#ifdef __ARCH_SI_TRAPNO 88#ifdef __ARCH_SI_TRAPNO
89 int _trapno; /* TRAP # which caused the signal */ 89 int _trapno; /* TRAP # which caused the signal */
90#endif 90#endif
91 short _addr_lsb;
91 } _sigfault; 92 } _sigfault;
92 93
93 /* SIGPOLL, SIGXFSZ (To do ...) */ 94 /* SIGPOLL, SIGXFSZ (To do ...) */
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index 0350311906ae..2d93bdbc9ac0 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -34,7 +34,7 @@
34#include <asm/ia32.h> 34#include <asm/ia32.h>
35 35
36#undef WARN_OLD 36#undef WARN_OLD
37#undef CORE_DUMP /* probably broken */ 37#undef CORE_DUMP /* definitely broken */
38 38
39static int load_aout_binary(struct linux_binprm *, struct pt_regs *regs); 39static int load_aout_binary(struct linux_binprm *, struct pt_regs *regs);
40static int load_aout_library(struct file *); 40static int load_aout_library(struct file *);
@@ -131,21 +131,15 @@ static void set_brk(unsigned long start, unsigned long end)
131 * macros to write out all the necessary info. 131 * macros to write out all the necessary info.
132 */ 132 */
133 133
134static int dump_write(struct file *file, const void *addr, int nr) 134#include <linux/coredump.h>
135{
136 return file->f_op->write(file, addr, nr, &file->f_pos) == nr;
137}
138 135
139#define DUMP_WRITE(addr, nr) \ 136#define DUMP_WRITE(addr, nr) \
140 if (!dump_write(file, (void *)(addr), (nr))) \ 137 if (!dump_write(file, (void *)(addr), (nr))) \
141 goto end_coredump; 138 goto end_coredump;
142 139
143#define DUMP_SEEK(offset) \ 140#define DUMP_SEEK(offset) \
144 if (file->f_op->llseek) { \ 141 if (!dump_seek(file, offset)) \
145 if (file->f_op->llseek(file, (offset), 0) != (offset)) \ 142 goto end_coredump;
146 goto end_coredump; \
147 } else \
148 file->f_pos = (offset)
149 143
150#define START_DATA() (u.u_tsize << PAGE_SHIFT) 144#define START_DATA() (u.u_tsize << PAGE_SHIFT)
151#define START_STACK(u) (u.start_stack) 145#define START_STACK(u) (u.start_stack)
@@ -217,12 +211,6 @@ static int aout_core_dump(long signr, struct pt_regs *regs, struct file *file,
217 dump_size = dump.u_ssize << PAGE_SHIFT; 211 dump_size = dump.u_ssize << PAGE_SHIFT;
218 DUMP_WRITE(dump_start, dump_size); 212 DUMP_WRITE(dump_start, dump_size);
219 } 213 }
220 /*
221 * Finally dump the task struct. Not be used by gdb, but
222 * could be useful
223 */
224 set_fs(KERNEL_DS);
225 DUMP_WRITE(current, sizeof(*current));
226end_coredump: 214end_coredump:
227 set_fs(fs); 215 set_fs(fs);
228 return has_dumped; 216 return has_dumped;
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 5e975298fa81..39aaee5c1ab2 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -141,6 +141,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
141 address = (low & MASK_BLKPTR_LO) >> 21; 141 address = (low & MASK_BLKPTR_LO) >> 21;
142 if (!address) 142 if (!address)
143 break; 143 break;
144
144 address += MCG_XBLK_ADDR; 145 address += MCG_XBLK_ADDR;
145 } else 146 } else
146 ++address; 147 ++address;
@@ -148,12 +149,8 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
148 if (rdmsr_safe(address, &low, &high)) 149 if (rdmsr_safe(address, &low, &high))
149 break; 150 break;
150 151
151 if (!(high & MASK_VALID_HI)) { 152 if (!(high & MASK_VALID_HI))
152 if (block) 153 continue;
153 continue;
154 else
155 break;
156 }
157 154
158 if (!(high & MASK_CNTP_HI) || 155 if (!(high & MASK_CNTP_HI) ||
159 (high & MASK_LOCKED_HI)) 156 (high & MASK_LOCKED_HI))
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index d9368eeda309..169d8804a9f8 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -216,7 +216,7 @@ static __cpuinit int thermal_throttle_add_dev(struct sys_device *sys_dev,
216 err = sysfs_add_file_to_group(&sys_dev->kobj, 216 err = sysfs_add_file_to_group(&sys_dev->kobj,
217 &attr_core_power_limit_count.attr, 217 &attr_core_power_limit_count.attr,
218 thermal_attr_group.name); 218 thermal_attr_group.name);
219 if (cpu_has(c, X86_FEATURE_PTS)) 219 if (cpu_has(c, X86_FEATURE_PTS)) {
220 err = sysfs_add_file_to_group(&sys_dev->kobj, 220 err = sysfs_add_file_to_group(&sys_dev->kobj,
221 &attr_package_throttle_count.attr, 221 &attr_package_throttle_count.attr,
222 thermal_attr_group.name); 222 thermal_attr_group.name);
@@ -224,6 +224,7 @@ static __cpuinit int thermal_throttle_add_dev(struct sys_device *sys_dev,
224 err = sysfs_add_file_to_group(&sys_dev->kobj, 224 err = sysfs_add_file_to_group(&sys_dev->kobj,
225 &attr_package_power_limit_count.attr, 225 &attr_package_power_limit_count.attr,
226 thermal_attr_group.name); 226 thermal_attr_group.name);
227 }
227 228
228 return err; 229 return err;
229} 230}
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index bc5b9b8d4a33..81ed28cb36e6 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -766,7 +766,6 @@ static void init_vmcb(struct vcpu_svm *svm)
766 766
767 control->iopm_base_pa = iopm_base; 767 control->iopm_base_pa = iopm_base;
768 control->msrpm_base_pa = __pa(svm->msrpm); 768 control->msrpm_base_pa = __pa(svm->msrpm);
769 control->tsc_offset = 0;
770 control->int_ctl = V_INTR_MASKING_MASK; 769 control->int_ctl = V_INTR_MASKING_MASK;
771 770
772 init_seg(&save->es); 771 init_seg(&save->es);
@@ -902,6 +901,7 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
902 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; 901 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
903 svm->asid_generation = 0; 902 svm->asid_generation = 0;
904 init_vmcb(svm); 903 init_vmcb(svm);
904 svm->vmcb->control.tsc_offset = 0-native_read_tsc();
905 905
906 err = fx_init(&svm->vcpu); 906 err = fx_init(&svm->vcpu);
907 if (err) 907 if (err)
diff --git a/arch/x86/mm/srat_64.c b/arch/x86/mm/srat_64.c
index f9897f7a9ef1..9c0d0d399c30 100644
--- a/arch/x86/mm/srat_64.c
+++ b/arch/x86/mm/srat_64.c
@@ -420,9 +420,11 @@ int __init acpi_scan_nodes(unsigned long start, unsigned long end)
420 return -1; 420 return -1;
421 } 421 }
422 422
423 for_each_node_mask(i, nodes_parsed) 423 for (i = 0; i < num_node_memblks; i++)
424 e820_register_active_regions(i, nodes[i].start >> PAGE_SHIFT, 424 e820_register_active_regions(memblk_nodeid[i],
425 nodes[i].end >> PAGE_SHIFT); 425 node_memblk_range[i].start >> PAGE_SHIFT,
426 node_memblk_range[i].end >> PAGE_SHIFT);
427
426 /* for out of order entries in SRAT */ 428 /* for out of order entries in SRAT */
427 sort_node_map(); 429 sort_node_map();
428 if (!nodes_cover_memory(nodes)) { 430 if (!nodes_cover_memory(nodes)) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 16:09:08 -0500