Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull ARM64 fixes from Catalin Marinas:
 - Exception level check at boot time (for completeness, not triggering
   any bug before)
 - I/D-cache synchronisation logic for huge pages
 - Config symbol typo

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: fix el2_setup check of CurrentEL
  arm64: mm: Make icache synchronisation logic huge page aware
  arm64: mm: Fix horrendous config typo

5 files changed, 9 insertions, 6 deletions

diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 579702086488..e0ccceb317d9 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -292,7 +292,7 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 #define pmd_sect(pmd)           ((pmd_val(pmd) & PMD_TYPE_MASK) == \
                                  PMD_TYPE_SECT)
 
-#ifdef ARM64_64K_PAGES
+#ifdef CONFIG_ARM64_64K_PAGES
 #define pud_sect(pud)           (0)
 #else
 #define pud_sect(pud)           ((pud_val(pud) & PUD_TYPE_MASK) == \
diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
index a429b5940be2..501000fadb6f 100644
--- a/arch/arm64/include/asm/ptrace.h
+++ b/arch/arm64/include/asm/ptrace.h
@@ -21,6 +21,10 @@
 
 #include <uapi/asm/ptrace.h>
 
+/* Current Exception Level values, as contained in CurrentEL */
+#define CurrentEL_EL1           (1 << 2)
+#define CurrentEL_EL2           (2 << 2)
+
 /* AArch32-specific ptrace requests */
 #define COMPAT_PTRACE_GETREGS           12
 #define COMPAT_PTRACE_SETREGS           13
diff --git a/arch/arm64/kernel/efi-entry.S b/arch/arm64/kernel/efi-entry.S
index 66716c9b9e5f..619b1dd7bcde 100644
--- a/arch/arm64/kernel/efi-entry.S
+++ b/arch/arm64/kernel/efi-entry.S
@@ -78,8 +78,7 @@ ENTRY(efi_stub_entry)
 
         /* Turn off Dcache and MMU */
         mrs     x0, CurrentEL
-        cmp     x0, #PSR_MODE_EL2t
-        ccmp    x0, #PSR_MODE_EL2h, #0x4, ne
+        cmp     x0, #CurrentEL_EL2
         b.ne    1f
         mrs     x0, sctlr_el2
         bic     x0, x0, #1 << 0 // clear SCTLR.M
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index a96d3a6a63f6..a2c1195abb7f 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -270,8 +270,7 @@ ENDPROC(stext)
  */
 ENTRY(el2_setup)
         mrs     x0, CurrentEL
-        cmp     x0, #PSR_MODE_EL2t
-        ccmp    x0, #PSR_MODE_EL2h, #0x4, ne
+        cmp     x0, #CurrentEL_EL2
         b.ne    1f
         mrs     x0, sctlr_el2
 CPU_BE( orr     x0, x0, #(1 << 25)      )       // Set the EE bit for EL2
diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
index e4193e3adc7f..0d64089d28b5 100644
--- a/arch/arm64/mm/flush.c
+++ b/arch/arm64/mm/flush.c
@@ -79,7 +79,8 @@ void __sync_icache_dcache(pte_t pte, unsigned long addr)
                 return;
 
         if (!test_and_set_bit(PG_dcache_clean, &page->flags)) {
-                __flush_dcache_area(page_address(page), PAGE_SIZE);
+                __flush_dcache_area(page_address(page),
+                                PAGE_SIZE << compound_order(page));
                 __flush_icache_all();
         } else if (icache_is_aivivt()) {
                 __flush_icache_all();