powerpc/85xx: fix mpic configuration in CAMP mode

Change the string to check for CAMP mode boot on MPC85xx (eg. P2020) to match
the one in the corresponding dts files (p2020rdb_camp_core{0,1}.dts).

Without this fix the mpic is configured as in the SMP boot mode, which causes
the first core to report a protected source interrupt error for devices
of the other core and lock up.

Also add MPIC_SINGLE_DEST_CPU on both P2020 based architectures in CAMP
mode as suggested by Scott Wood. Thanks.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

2 files changed, 5 insertions, 3 deletions

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index c7b97f70312e..1b9a8cf1873a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -83,7 +83,8 @@ void __init mpc85xx_ds_pic_init(void)
         if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
                 mpic = mpic_alloc(np, r.start,
                         MPIC_PRIMARY |
-                        MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
+                        MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                        MPIC_SINGLE_DEST_CPU,
                         0, 256, " OpenPIC  ");
         } else {
                 mpic = mpic_alloc(np, r.start,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 088f30b0c088..f5ff9110c97e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -58,10 +58,11 @@ void __init mpc85xx_rdb_pic_init(void)
                 return;
         }
 
-        if (of_flat_dt_is_compatible(root, "fsl,85XXRDB-CAMP")) {
+        if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
                 mpic = mpic_alloc(np, r.start,
                         MPIC_PRIMARY |
-                        MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
+                        MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                        MPIC_SINGLE_DEST_CPU,
                         0, 256, " OpenPIC  ");
         } else {
                 mpic = mpic_alloc(np, r.start,