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authorKumar Gala <galak@kernel.crashing.org>2011-06-23 08:19:15 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-07-07 10:33:50 -0400
commit8dbb6bc13617379a6534700e51634a3f88c9a513 (patch)
tree829789a41369b6b97c32fefcb504e671b4a9a6d8 /arch
parente5aae727c0014107c647c4148fa21c4f11e97307 (diff)
powerpc/85xx: Add P5020 SoC device tree include stub
Split out common (non-board specific) parts of the SoC related device tree into a stub so multiple board dts files can include it and we can reduce duplication and maintenance effort. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/p5020ds.dts571
-rw-r--r--arch/powerpc/boot/dts/p5020si.dtsi652
2 files changed, 653 insertions, 570 deletions
diff --git a/arch/powerpc/boot/dts/p5020ds.dts b/arch/powerpc/boot/dts/p5020ds.dts
index 069cff7c2ea5..8366e2fd2fba 100644
--- a/arch/powerpc/boot/dts/p5020ds.dts
+++ b/arch/powerpc/boot/dts/p5020ds.dts
@@ -32,7 +32,7 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35/dts-v1/; 35/include/ "p5020si.dtsi"
36 36
37/ { 37/ {
38 model = "fsl,P5020DS"; 38 model = "fsl,P5020DS";
@@ -41,292 +41,12 @@
41 #size-cells = <2>; 41 #size-cells = <2>;
42 interrupt-parent = <&mpic>; 42 interrupt-parent = <&mpic>;
43 43
44 aliases {
45 ccsr = &soc;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 pci2 = &pci2;
54 pci3 = &pci3;
55 usb0 = &usb0;
56 usb1 = &usb1;
57 dma0 = &dma0;
58 dma1 = &dma1;
59 sdhc = &sdhc;
60 msi0 = &msi0;
61 msi1 = &msi1;
62 msi2 = &msi2;
63
64 crypto = &crypto;
65 sec_jr0 = &sec_jr0;
66 sec_jr1 = &sec_jr1;
67 sec_jr2 = &sec_jr2;
68 sec_jr3 = &sec_jr3;
69 rtic_a = &rtic_a;
70 rtic_b = &rtic_b;
71 rtic_c = &rtic_c;
72 rtic_d = &rtic_d;
73 sec_mon = &sec_mon;
74 };
75
76 cpus {
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 cpu0: PowerPC,e5500@0 {
81 device_type = "cpu";
82 reg = <0>;
83 next-level-cache = <&L2_0>;
84 L2_0: l2-cache {
85 next-level-cache = <&cpc>;
86 };
87 };
88 cpu1: PowerPC,e5500@1 {
89 device_type = "cpu";
90 reg = <1>;
91 next-level-cache = <&L2_1>;
92 L2_1: l2-cache {
93 next-level-cache = <&cpc>;
94 };
95 };
96 };
97
98 memory { 44 memory {
99 device_type = "memory"; 45 device_type = "memory";
100 }; 46 };
101 47
102 soc: soc@ffe000000 { 48 soc: soc@ffe000000 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 device_type = "soc";
106 compatible = "simple-bus";
107 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
108 reg = <0xf 0xfe000000 0 0x00001000>;
109
110 soc-sram-error {
111 compatible = "fsl,soc-sram-error";
112 interrupts = <16 2 1 29>;
113 };
114
115 corenet-law@0 {
116 compatible = "fsl,corenet-law";
117 reg = <0x0 0x1000>;
118 fsl,num-laws = <32>;
119 };
120
121 memory-controller@8000 {
122 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
123 reg = <0x8000 0x1000>;
124 interrupts = <16 2 1 23>;
125 };
126
127 memory-controller@9000 {
128 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
129 reg = <0x9000 0x1000>;
130 interrupts = <16 2 1 22>;
131 };
132
133 cpc: l3-cache-controller@10000 {
134 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
135 reg = <0x10000 0x1000
136 0x11000 0x1000>;
137 interrupts = <16 2 1 27
138 16 2 1 26>;
139 };
140
141 corenet-cf@18000 {
142 compatible = "fsl,corenet-cf";
143 reg = <0x18000 0x1000>;
144 interrupts = <16 2 1 31>;
145 fsl,ccf-num-csdids = <32>;
146 fsl,ccf-num-snoopids = <32>;
147 };
148
149 iommu@20000 {
150 compatible = "fsl,pamu-v1.0", "fsl,pamu";
151 reg = <0x20000 0x4000>;
152 interrupts = <
153 24 2 0 0
154 16 2 1 30>;
155 };
156
157 mpic: pic@40000 {
158 clock-frequency = <0>;
159 interrupt-controller;
160 #address-cells = <0>;
161 #interrupt-cells = <4>;
162 reg = <0x40000 0x40000>;
163 compatible = "fsl,mpic", "chrp,open-pic";
164 device_type = "open-pic";
165 };
166
167 msi0: msi@41600 {
168 compatible = "fsl,mpic-msi";
169 reg = <0x41600 0x200>;
170 msi-available-ranges = <0 0x100>;
171 interrupts = <
172 0xe0 0 0 0
173 0xe1 0 0 0
174 0xe2 0 0 0
175 0xe3 0 0 0
176 0xe4 0 0 0
177 0xe5 0 0 0
178 0xe6 0 0 0
179 0xe7 0 0 0>;
180 };
181
182 msi1: msi@41800 {
183 compatible = "fsl,mpic-msi";
184 reg = <0x41800 0x200>;
185 msi-available-ranges = <0 0x100>;
186 interrupts = <
187 0xe8 0 0 0
188 0xe9 0 0 0
189 0xea 0 0 0
190 0xeb 0 0 0
191 0xec 0 0 0
192 0xed 0 0 0
193 0xee 0 0 0
194 0xef 0 0 0>;
195 };
196
197 msi2: msi@41a00 {
198 compatible = "fsl,mpic-msi";
199 reg = <0x41a00 0x200>;
200 msi-available-ranges = <0 0x100>;
201 interrupts = <
202 0xf0 0 0 0
203 0xf1 0 0 0
204 0xf2 0 0 0
205 0xf3 0 0 0
206 0xf4 0 0 0
207 0xf5 0 0 0
208 0xf6 0 0 0
209 0xf7 0 0 0>;
210 };
211
212 guts: global-utilities@e0000 {
213 compatible = "fsl,qoriq-device-config-1.0";
214 reg = <0xe0000 0xe00>;
215 fsl,has-rstcr;
216 #sleep-cells = <1>;
217 fsl,liodn-bits = <12>;
218 };
219
220 pins: global-utilities@e0e00 {
221 compatible = "fsl,qoriq-pin-control-1.0";
222 reg = <0xe0e00 0x200>;
223 #sleep-cells = <2>;
224 };
225
226 clockgen: global-utilities@e1000 {
227 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
228 reg = <0xe1000 0x1000>;
229 clock-frequency = <0>;
230 };
231
232 rcpm: global-utilities@e2000 {
233 compatible = "fsl,qoriq-rcpm-1.0";
234 reg = <0xe2000 0x1000>;
235 #sleep-cells = <1>;
236 };
237
238 sfp: sfp@e8000 {
239 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
240 reg = <0xe8000 0x1000>;
241 };
242
243 serdes: serdes@ea000 {
244 compatible = "fsl,p5020-serdes";
245 reg = <0xea000 0x1000>;
246 };
247
248 dma0: dma@100300 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
252 reg = <0x100300 0x4>;
253 ranges = <0x0 0x100100 0x200>;
254 cell-index = <0>;
255 dma-channel@0 {
256 compatible = "fsl,p5020-dma-channel",
257 "fsl,eloplus-dma-channel";
258 reg = <0x0 0x80>;
259 cell-index = <0>;
260 interrupts = <28 2 0 0>;
261 };
262 dma-channel@80 {
263 compatible = "fsl,p5020-dma-channel",
264 "fsl,eloplus-dma-channel";
265 reg = <0x80 0x80>;
266 cell-index = <1>;
267 interrupts = <29 2 0 0>;
268 };
269 dma-channel@100 {
270 compatible = "fsl,p5020-dma-channel",
271 "fsl,eloplus-dma-channel";
272 reg = <0x100 0x80>;
273 cell-index = <2>;
274 interrupts = <30 2 0 0>;
275 };
276 dma-channel@180 {
277 compatible = "fsl,p5020-dma-channel",
278 "fsl,eloplus-dma-channel";
279 reg = <0x180 0x80>;
280 cell-index = <3>;
281 interrupts = <31 2 0 0>;
282 };
283 };
284
285 dma1: dma@101300 {
286 #address-cells = <1>;
287 #size-cells = <1>;
288 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
289 reg = <0x101300 0x4>;
290 ranges = <0x0 0x101100 0x200>;
291 cell-index = <1>;
292 dma-channel@0 {
293 compatible = "fsl,p5020-dma-channel",
294 "fsl,eloplus-dma-channel";
295 reg = <0x0 0x80>;
296 cell-index = <0>;
297 interrupts = <32 2 0 0>;
298 };
299 dma-channel@80 {
300 compatible = "fsl,p5020-dma-channel",
301 "fsl,eloplus-dma-channel";
302 reg = <0x80 0x80>;
303 cell-index = <1>;
304 interrupts = <33 2 0 0>;
305 };
306 dma-channel@100 {
307 compatible = "fsl,p5020-dma-channel",
308 "fsl,eloplus-dma-channel";
309 reg = <0x100 0x80>;
310 cell-index = <2>;
311 interrupts = <34 2 0 0>;
312 };
313 dma-channel@180 {
314 compatible = "fsl,p5020-dma-channel",
315 "fsl,eloplus-dma-channel";
316 reg = <0x180 0x80>;
317 cell-index = <3>;
318 interrupts = <35 2 0 0>;
319 };
320 };
321
322 spi@110000 { 49 spi@110000 {
323 #address-cells = <1>;
324 #size-cells = <0>;
325 compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
326 reg = <0x110000 0x1000>;
327 interrupts = <53 0x2 0 0>;
328 fsl,espi-num-chipselects = <4>;
329
330 flash@0 { 50 flash@0 {
331 #address-cells = <1>; 51 #address-cells = <1>;
332 #size-cells = <1>; 52 #size-cells = <1>;
@@ -355,32 +75,7 @@
355 }; 75 };
356 }; 76 };
357 77
358 sdhc: sdhc@114000 {
359 compatible = "fsl,p5020-esdhc", "fsl,esdhc";
360 reg = <0x114000 0x1000>;
361 interrupts = <48 2 0 0>;
362 sdhci,auto-cmd12;
363 clock-frequency = <0>;
364 };
365
366 i2c@118000 {
367 #address-cells = <1>;
368 #size-cells = <0>;
369 cell-index = <0>;
370 compatible = "fsl-i2c";
371 reg = <0x118000 0x100>;
372 interrupts = <38 2 0 0>;
373 dfsrr;
374 };
375
376 i2c@118100 { 78 i2c@118100 {
377 #address-cells = <1>;
378 #size-cells = <0>;
379 cell-index = <1>;
380 compatible = "fsl-i2c";
381 reg = <0x118100 0x100>;
382 interrupts = <38 2 0 0>;
383 dfsrr;
384 eeprom@51 { 79 eeprom@51 {
385 compatible = "at24,24c256"; 80 compatible = "at24,24c256";
386 reg = <0x51>; 81 reg = <0x51>;
@@ -391,193 +86,17 @@
391 }; 86 };
392 }; 87 };
393 88
394 i2c@119000 {
395 #address-cells = <1>;
396 #size-cells = <0>;
397 cell-index = <2>;
398 compatible = "fsl-i2c";
399 reg = <0x119000 0x100>;
400 interrupts = <39 2 0 0>;
401 dfsrr;
402 };
403
404 i2c@119100 { 89 i2c@119100 {
405 #address-cells = <1>;
406 #size-cells = <0>;
407 cell-index = <3>;
408 compatible = "fsl-i2c";
409 reg = <0x119100 0x100>;
410 interrupts = <39 2 0 0>;
411 dfsrr;
412 rtc@68 { 90 rtc@68 {
413 compatible = "dallas,ds3232"; 91 compatible = "dallas,ds3232";
414 reg = <0x68>; 92 reg = <0x68>;
415 interrupts = <0x1 0x1 0 0>; 93 interrupts = <0x1 0x1 0 0>;
416 }; 94 };
417 }; 95 };
418
419 serial0: serial@11c500 {
420 cell-index = <0>;
421 device_type = "serial";
422 compatible = "ns16550";
423 reg = <0x11c500 0x100>;
424 clock-frequency = <0>;
425 interrupts = <36 2 0 0>;
426 };
427
428 serial1: serial@11c600 {
429 cell-index = <1>;
430 device_type = "serial";
431 compatible = "ns16550";
432 reg = <0x11c600 0x100>;
433 clock-frequency = <0>;
434 interrupts = <36 2 0 0>;
435 };
436
437 serial2: serial@11d500 {
438 cell-index = <2>;
439 device_type = "serial";
440 compatible = "ns16550";
441 reg = <0x11d500 0x100>;
442 clock-frequency = <0>;
443 interrupts = <37 2 0 0>;
444 };
445
446 serial3: serial@11d600 {
447 cell-index = <3>;
448 device_type = "serial";
449 compatible = "ns16550";
450 reg = <0x11d600 0x100>;
451 clock-frequency = <0>;
452 interrupts = <37 2 0 0>;
453 };
454
455 gpio0: gpio@130000 {
456 compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
457 reg = <0x130000 0x1000>;
458 interrupts = <55 2 0 0>;
459 #gpio-cells = <2>;
460 gpio-controller;
461 };
462
463 usb0: usb@210000 {
464 compatible = "fsl,p5020-usb2-mph",
465 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
466 reg = <0x210000 0x1000>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 interrupts = <44 0x2 0 0>;
470 phy_type = "utmi";
471 port0;
472 };
473
474 usb1: usb@211000 {
475 compatible = "fsl,p5020-usb2-dr",
476 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
477 reg = <0x211000 0x1000>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480 interrupts = <45 0x2 0 0>;
481 dr_mode = "host";
482 phy_type = "utmi";
483 };
484
485 sata@220000 {
486 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
487 reg = <0x220000 0x1000>;
488 interrupts = <68 0x2 0 0>;
489 };
490
491 sata@221000 {
492 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
493 reg = <0x221000 0x1000>;
494 interrupts = <69 0x2 0 0>;
495 };
496
497 crypto: crypto@300000 {
498 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
499 #address-cells = <1>;
500 #size-cells = <1>;
501 reg = <0x300000 0x10000>;
502 ranges = <0 0x300000 0x10000>;
503 interrupts = <92 2 0 0>;
504
505 sec_jr0: jr@1000 {
506 compatible = "fsl,sec-v4.2-job-ring",
507 "fsl,sec-v4.0-job-ring";
508 reg = <0x1000 0x1000>;
509 interrupts = <88 2 0 0>;
510 };
511
512 sec_jr1: jr@2000 {
513 compatible = "fsl,sec-v4.2-job-ring",
514 "fsl,sec-v4.0-job-ring";
515 reg = <0x2000 0x1000>;
516 interrupts = <89 2 0 0>;
517 };
518
519 sec_jr2: jr@3000 {
520 compatible = "fsl,sec-v4.2-job-ring",
521 "fsl,sec-v4.0-job-ring";
522 reg = <0x3000 0x1000>;
523 interrupts = <90 2 0 0>;
524 };
525
526 sec_jr3: jr@4000 {
527 compatible = "fsl,sec-v4.2-job-ring",
528 "fsl,sec-v4.0-job-ring";
529 reg = <0x4000 0x1000>;
530 interrupts = <91 2 0 0>;
531 };
532
533 rtic@6000 {
534 compatible = "fsl,sec-v4.2-rtic",
535 "fsl,sec-v4.0-rtic";
536 #address-cells = <1>;
537 #size-cells = <1>;
538 reg = <0x6000 0x100>;
539 ranges = <0x0 0x6100 0xe00>;
540
541 rtic_a: rtic-a@0 {
542 compatible = "fsl,sec-v4.2-rtic-memory",
543 "fsl,sec-v4.0-rtic-memory";
544 reg = <0x00 0x20 0x100 0x80>;
545 };
546
547 rtic_b: rtic-b@20 {
548 compatible = "fsl,sec-v4.2-rtic-memory",
549 "fsl,sec-v4.0-rtic-memory";
550 reg = <0x20 0x20 0x200 0x80>;
551 };
552
553 rtic_c: rtic-c@40 {
554 compatible = "fsl,sec-v4.2-rtic-memory",
555 "fsl,sec-v4.0-rtic-memory";
556 reg = <0x40 0x20 0x300 0x80>;
557 };
558
559 rtic_d: rtic-d@60 {
560 compatible = "fsl,sec-v4.2-rtic-memory",
561 "fsl,sec-v4.0-rtic-memory";
562 reg = <0x60 0x20 0x500 0x80>;
563 };
564 };
565 };
566
567 sec_mon: sec_mon@314000 {
568 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
569 reg = <0x314000 0x1000>;
570 interrupts = <93 2 0 0>;
571 };
572 }; 96 };
573 97
574 localbus@ffe124000 { 98 localbus@ffe124000 {
575 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
576 reg = <0xf 0xfe124000 0 0x1000>; 99 reg = <0xf 0xfe124000 0 0x1000>;
577 interrupts = <25 2 0 0>;
578 #address-cells = <2>;
579 #size-cells = <1>;
580
581 ranges = <0 0 0xf 0xe8000000 0x08000000 100 ranges = <0 0 0xf 0xe8000000 0x08000000
582 2 0 0xf 0xffa00000 0x00040000 101 2 0 0xf 0xffa00000 0x00040000
583 3 0 0xf 0xffdf0000 0x00008000>; 102 3 0 0xf 0xffdf0000 0x00008000>;
@@ -634,33 +153,11 @@
634 }; 153 };
635 154
636 pci0: pcie@ffe200000 { 155 pci0: pcie@ffe200000 {
637 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
638 device_type = "pci";
639 #size-cells = <2>;
640 #address-cells = <3>;
641 reg = <0xf 0xfe200000 0 0x1000>; 156 reg = <0xf 0xfe200000 0 0x1000>;
642 bus-range = <0x0 0xff>;
643 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 157 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
644 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 158 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
645 clock-frequency = <0x1fca055>;
646 fsl,msi = <&msi0>;
647 interrupts = <16 2 1 15>;
648 159
649 pcie@0 { 160 pcie@0 {
650 reg = <0 0 0 0 0>;
651 #interrupt-cells = <1>;
652 #size-cells = <2>;
653 #address-cells = <3>;
654 device_type = "pci";
655 interrupts = <16 2 1 15>;
656 interrupt-map-mask = <0xf800 0 0 7>;
657 interrupt-map = <
658 /* IDSEL 0x0 */
659 0000 0 0 1 &mpic 40 1 0 0
660 0000 0 0 2 &mpic 1 1 0 0
661 0000 0 0 3 &mpic 2 1 0 0
662 0000 0 0 4 &mpic 3 1 0 0
663 >;
664 ranges = <0x02000000 0 0xe0000000 161 ranges = <0x02000000 0 0xe0000000
665 0x02000000 0 0xe0000000 162 0x02000000 0 0xe0000000
666 0 0x20000000 163 0 0x20000000
@@ -672,32 +169,10 @@
672 }; 169 };
673 170
674 pci1: pcie@ffe201000 { 171 pci1: pcie@ffe201000 {
675 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
676 device_type = "pci";
677 #size-cells = <2>;
678 #address-cells = <3>;
679 reg = <0xf 0xfe201000 0 0x1000>; 172 reg = <0xf 0xfe201000 0 0x1000>;
680 bus-range = <0 0xff>;
681 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 173 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
682 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 174 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
683 clock-frequency = <0x1fca055>;
684 fsl,msi = <&msi1>;
685 interrupts = <16 2 1 14>;
686 pcie@0 { 175 pcie@0 {
687 reg = <0 0 0 0 0>;
688 #interrupt-cells = <1>;
689 #size-cells = <2>;
690 #address-cells = <3>;
691 device_type = "pci";
692 interrupts = <16 2 1 14>;
693 interrupt-map-mask = <0xf800 0 0 7>;
694 interrupt-map = <
695 /* IDSEL 0x0 */
696 0000 0 0 1 &mpic 41 1 0 0
697 0000 0 0 2 &mpic 5 1 0 0
698 0000 0 0 3 &mpic 6 1 0 0
699 0000 0 0 4 &mpic 7 1 0 0
700 >;
701 ranges = <0x02000000 0 0xe0000000 176 ranges = <0x02000000 0 0xe0000000
702 0x02000000 0 0xe0000000 177 0x02000000 0 0xe0000000
703 0 0x20000000 178 0 0x20000000
@@ -709,32 +184,10 @@
709 }; 184 };
710 185
711 pci2: pcie@ffe202000 { 186 pci2: pcie@ffe202000 {
712 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
713 device_type = "pci";
714 #size-cells = <2>;
715 #address-cells = <3>;
716 reg = <0xf 0xfe202000 0 0x1000>; 187 reg = <0xf 0xfe202000 0 0x1000>;
717 bus-range = <0x0 0xff>;
718 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 188 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
719 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 189 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
720 clock-frequency = <0x1fca055>;
721 fsl,msi = <&msi2>;
722 interrupts = <16 2 1 13>;
723 pcie@0 { 190 pcie@0 {
724 reg = <0 0 0 0 0>;
725 #interrupt-cells = <1>;
726 #size-cells = <2>;
727 #address-cells = <3>;
728 device_type = "pci";
729 interrupts = <16 2 1 13>;
730 interrupt-map-mask = <0xf800 0 0 7>;
731 interrupt-map = <
732 /* IDSEL 0x0 */
733 0000 0 0 1 &mpic 42 1 0 0
734 0000 0 0 2 &mpic 9 1 0 0
735 0000 0 0 3 &mpic 10 1 0 0
736 0000 0 0 4 &mpic 11 1 0 0
737 >;
738 ranges = <0x02000000 0 0xe0000000 191 ranges = <0x02000000 0 0xe0000000
739 0x02000000 0 0xe0000000 192 0x02000000 0 0xe0000000
740 0 0x20000000 193 0 0x20000000
@@ -746,32 +199,10 @@
746 }; 199 };
747 200
748 pci3: pcie@ffe203000 { 201 pci3: pcie@ffe203000 {
749 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
750 device_type = "pci";
751 #size-cells = <2>;
752 #address-cells = <3>;
753 reg = <0xf 0xfe203000 0 0x1000>; 202 reg = <0xf 0xfe203000 0 0x1000>;
754 bus-range = <0x0 0xff>;
755 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 203 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
756 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 204 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
757 clock-frequency = <0x1fca055>;
758 fsl,msi = <&msi2>;
759 interrupts = <16 2 1 12>;
760 pcie@0 { 205 pcie@0 {
761 reg = <0 0 0 0 0>;
762 #interrupt-cells = <1>;
763 #size-cells = <2>;
764 #address-cells = <3>;
765 device_type = "pci";
766 interrupts = <16 2 1 12>;
767 interrupt-map-mask = <0xf800 0 0 7>;
768 interrupt-map = <
769 /* IDSEL 0x0 */
770 0000 0 0 1 &mpic 43 1 0 0
771 0000 0 0 2 &mpic 0 1 0 0
772 0000 0 0 3 &mpic 4 1 0 0
773 0000 0 0 4 &mpic 8 1 0 0
774 >;
775 ranges = <0x02000000 0 0xe0000000 206 ranges = <0x02000000 0 0xe0000000
776 0x02000000 0 0xe0000000 207 0x02000000 0 0xe0000000
777 0 0x20000000 208 0 0x20000000
diff --git a/arch/powerpc/boot/dts/p5020si.dtsi b/arch/powerpc/boot/dts/p5020si.dtsi
new file mode 100644
index 000000000000..5e6048ec55bb
--- /dev/null
+++ b/arch/powerpc/boot/dts/p5020si.dtsi
@@ -0,0 +1,652 @@
1/*
2 * P5020 Silicon Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P5020";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 pci3 = &pci3;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73
74/*
75 rio0 = &rapidio0;
76 */
77 };
78
79 cpus {
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 cpu0: PowerPC,e5500@0 {
84 device_type = "cpu";
85 reg = <0>;
86 next-level-cache = <&L2_0>;
87 L2_0: l2-cache {
88 next-level-cache = <&cpc>;
89 };
90 };
91 cpu1: PowerPC,e5500@1 {
92 device_type = "cpu";
93 reg = <1>;
94 next-level-cache = <&L2_1>;
95 L2_1: l2-cache {
96 next-level-cache = <&cpc>;
97 };
98 };
99 };
100
101 soc: soc@ffe000000 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 device_type = "soc";
105 compatible = "simple-bus";
106 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
107 reg = <0xf 0xfe000000 0 0x00001000>;
108
109 soc-sram-error {
110 compatible = "fsl,soc-sram-error";
111 interrupts = <16 2 1 29>;
112 };
113
114 corenet-law@0 {
115 compatible = "fsl,corenet-law";
116 reg = <0x0 0x1000>;
117 fsl,num-laws = <32>;
118 };
119
120 memory-controller@8000 {
121 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
122 reg = <0x8000 0x1000>;
123 interrupts = <16 2 1 23>;
124 };
125
126 memory-controller@9000 {
127 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
128 reg = <0x9000 0x1000>;
129 interrupts = <16 2 1 22>;
130 };
131
132 cpc: l3-cache-controller@10000 {
133 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
134 reg = <0x10000 0x1000
135 0x11000 0x1000>;
136 interrupts = <16 2 1 27
137 16 2 1 26>;
138 };
139
140 corenet-cf@18000 {
141 compatible = "fsl,corenet-cf";
142 reg = <0x18000 0x1000>;
143 interrupts = <16 2 1 31>;
144 fsl,ccf-num-csdids = <32>;
145 fsl,ccf-num-snoopids = <32>;
146 };
147
148 iommu@20000 {
149 compatible = "fsl,pamu-v1.0", "fsl,pamu";
150 reg = <0x20000 0x4000>;
151 interrupts = <
152 24 2 0 0
153 16 2 1 30>;
154 };
155
156 mpic: pic@40000 {
157 clock-frequency = <0>;
158 interrupt-controller;
159 #address-cells = <0>;
160 #interrupt-cells = <4>;
161 reg = <0x40000 0x40000>;
162 compatible = "fsl,mpic", "chrp,open-pic";
163 device_type = "open-pic";
164 };
165
166 msi0: msi@41600 {
167 compatible = "fsl,mpic-msi";
168 reg = <0x41600 0x200>;
169 msi-available-ranges = <0 0x100>;
170 interrupts = <
171 0xe0 0 0 0
172 0xe1 0 0 0
173 0xe2 0 0 0
174 0xe3 0 0 0
175 0xe4 0 0 0
176 0xe5 0 0 0
177 0xe6 0 0 0
178 0xe7 0 0 0>;
179 };
180
181 msi1: msi@41800 {
182 compatible = "fsl,mpic-msi";
183 reg = <0x41800 0x200>;
184 msi-available-ranges = <0 0x100>;
185 interrupts = <
186 0xe8 0 0 0
187 0xe9 0 0 0
188 0xea 0 0 0
189 0xeb 0 0 0
190 0xec 0 0 0
191 0xed 0 0 0
192 0xee 0 0 0
193 0xef 0 0 0>;
194 };
195
196 msi2: msi@41a00 {
197 compatible = "fsl,mpic-msi";
198 reg = <0x41a00 0x200>;
199 msi-available-ranges = <0 0x100>;
200 interrupts = <
201 0xf0 0 0 0
202 0xf1 0 0 0
203 0xf2 0 0 0
204 0xf3 0 0 0
205 0xf4 0 0 0
206 0xf5 0 0 0
207 0xf6 0 0 0
208 0xf7 0 0 0>;
209 };
210
211 guts: global-utilities@e0000 {
212 compatible = "fsl,qoriq-device-config-1.0";
213 reg = <0xe0000 0xe00>;
214 fsl,has-rstcr;
215 #sleep-cells = <1>;
216 fsl,liodn-bits = <12>;
217 };
218
219 pins: global-utilities@e0e00 {
220 compatible = "fsl,qoriq-pin-control-1.0";
221 reg = <0xe0e00 0x200>;
222 #sleep-cells = <2>;
223 };
224
225 clockgen: global-utilities@e1000 {
226 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
227 reg = <0xe1000 0x1000>;
228 clock-frequency = <0>;
229 };
230
231 rcpm: global-utilities@e2000 {
232 compatible = "fsl,qoriq-rcpm-1.0";
233 reg = <0xe2000 0x1000>;
234 #sleep-cells = <1>;
235 };
236
237 sfp: sfp@e8000 {
238 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
239 reg = <0xe8000 0x1000>;
240 };
241
242 serdes: serdes@ea000 {
243 compatible = "fsl,p5020-serdes";
244 reg = <0xea000 0x1000>;
245 };
246
247 dma0: dma@100300 {
248 #address-cells = <1>;
249 #size-cells = <1>;
250 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
251 reg = <0x100300 0x4>;
252 ranges = <0x0 0x100100 0x200>;
253 cell-index = <0>;
254 dma-channel@0 {
255 compatible = "fsl,p5020-dma-channel",
256 "fsl,eloplus-dma-channel";
257 reg = <0x0 0x80>;
258 cell-index = <0>;
259 interrupts = <28 2 0 0>;
260 };
261 dma-channel@80 {
262 compatible = "fsl,p5020-dma-channel",
263 "fsl,eloplus-dma-channel";
264 reg = <0x80 0x80>;
265 cell-index = <1>;
266 interrupts = <29 2 0 0>;
267 };
268 dma-channel@100 {
269 compatible = "fsl,p5020-dma-channel",
270 "fsl,eloplus-dma-channel";
271 reg = <0x100 0x80>;
272 cell-index = <2>;
273 interrupts = <30 2 0 0>;
274 };
275 dma-channel@180 {
276 compatible = "fsl,p5020-dma-channel",
277 "fsl,eloplus-dma-channel";
278 reg = <0x180 0x80>;
279 cell-index = <3>;
280 interrupts = <31 2 0 0>;
281 };
282 };
283
284 dma1: dma@101300 {
285 #address-cells = <1>;
286 #size-cells = <1>;
287 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
288 reg = <0x101300 0x4>;
289 ranges = <0x0 0x101100 0x200>;
290 cell-index = <1>;
291 dma-channel@0 {
292 compatible = "fsl,p5020-dma-channel",
293 "fsl,eloplus-dma-channel";
294 reg = <0x0 0x80>;
295 cell-index = <0>;
296 interrupts = <32 2 0 0>;
297 };
298 dma-channel@80 {
299 compatible = "fsl,p5020-dma-channel",
300 "fsl,eloplus-dma-channel";
301 reg = <0x80 0x80>;
302 cell-index = <1>;
303 interrupts = <33 2 0 0>;
304 };
305 dma-channel@100 {
306 compatible = "fsl,p5020-dma-channel",
307 "fsl,eloplus-dma-channel";
308 reg = <0x100 0x80>;
309 cell-index = <2>;
310 interrupts = <34 2 0 0>;
311 };
312 dma-channel@180 {
313 compatible = "fsl,p5020-dma-channel",
314 "fsl,eloplus-dma-channel";
315 reg = <0x180 0x80>;
316 cell-index = <3>;
317 interrupts = <35 2 0 0>;
318 };
319 };
320
321 spi@110000 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
325 reg = <0x110000 0x1000>;
326 interrupts = <53 0x2 0 0>;
327 fsl,espi-num-chipselects = <4>;
328 };
329
330 sdhc: sdhc@114000 {
331 compatible = "fsl,p5020-esdhc", "fsl,esdhc";
332 reg = <0x114000 0x1000>;
333 interrupts = <48 2 0 0>;
334 sdhci,auto-cmd12;
335 clock-frequency = <0>;
336 };
337
338 i2c@118000 {
339 #address-cells = <1>;
340 #size-cells = <0>;
341 cell-index = <0>;
342 compatible = "fsl-i2c";
343 reg = <0x118000 0x100>;
344 interrupts = <38 2 0 0>;
345 dfsrr;
346 };
347
348 i2c@118100 {
349 #address-cells = <1>;
350 #size-cells = <0>;
351 cell-index = <1>;
352 compatible = "fsl-i2c";
353 reg = <0x118100 0x100>;
354 interrupts = <38 2 0 0>;
355 dfsrr;
356 };
357
358 i2c@119000 {
359 #address-cells = <1>;
360 #size-cells = <0>;
361 cell-index = <2>;
362 compatible = "fsl-i2c";
363 reg = <0x119000 0x100>;
364 interrupts = <39 2 0 0>;
365 dfsrr;
366 };
367
368 i2c@119100 {
369 #address-cells = <1>;
370 #size-cells = <0>;
371 cell-index = <3>;
372 compatible = "fsl-i2c";
373 reg = <0x119100 0x100>;
374 interrupts = <39 2 0 0>;
375 dfsrr;
376 };
377
378 serial0: serial@11c500 {
379 cell-index = <0>;
380 device_type = "serial";
381 compatible = "ns16550";
382 reg = <0x11c500 0x100>;
383 clock-frequency = <0>;
384 interrupts = <36 2 0 0>;
385 };
386
387 serial1: serial@11c600 {
388 cell-index = <1>;
389 device_type = "serial";
390 compatible = "ns16550";
391 reg = <0x11c600 0x100>;
392 clock-frequency = <0>;
393 interrupts = <36 2 0 0>;
394 };
395
396 serial2: serial@11d500 {
397 cell-index = <2>;
398 device_type = "serial";
399 compatible = "ns16550";
400 reg = <0x11d500 0x100>;
401 clock-frequency = <0>;
402 interrupts = <37 2 0 0>;
403 };
404
405 serial3: serial@11d600 {
406 cell-index = <3>;
407 device_type = "serial";
408 compatible = "ns16550";
409 reg = <0x11d600 0x100>;
410 clock-frequency = <0>;
411 interrupts = <37 2 0 0>;
412 };
413
414 gpio0: gpio@130000 {
415 compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
416 reg = <0x130000 0x1000>;
417 interrupts = <55 2 0 0>;
418 #gpio-cells = <2>;
419 gpio-controller;
420 };
421
422 usb0: usb@210000 {
423 compatible = "fsl,p5020-usb2-mph",
424 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
425 reg = <0x210000 0x1000>;
426 #address-cells = <1>;
427 #size-cells = <0>;
428 interrupts = <44 0x2 0 0>;
429 phy_type = "utmi";
430 port0;
431 };
432
433 usb1: usb@211000 {
434 compatible = "fsl,p5020-usb2-dr",
435 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
436 reg = <0x211000 0x1000>;
437 #address-cells = <1>;
438 #size-cells = <0>;
439 interrupts = <45 0x2 0 0>;
440 dr_mode = "host";
441 phy_type = "utmi";
442 };
443
444 sata@220000 {
445 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
446 reg = <0x220000 0x1000>;
447 interrupts = <68 0x2 0 0>;
448 };
449
450 sata@221000 {
451 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
452 reg = <0x221000 0x1000>;
453 interrupts = <69 0x2 0 0>;
454 };
455
456 crypto: crypto@300000 {
457 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
458 #address-cells = <1>;
459 #size-cells = <1>;
460 reg = <0x300000 0x10000>;
461 ranges = <0 0x300000 0x10000>;
462 interrupts = <92 2 0 0>;
463
464 sec_jr0: jr@1000 {
465 compatible = "fsl,sec-v4.2-job-ring",
466 "fsl,sec-v4.0-job-ring";
467 reg = <0x1000 0x1000>;
468 interrupts = <88 2 0 0>;
469 };
470
471 sec_jr1: jr@2000 {
472 compatible = "fsl,sec-v4.2-job-ring",
473 "fsl,sec-v4.0-job-ring";
474 reg = <0x2000 0x1000>;
475 interrupts = <89 2 0 0>;
476 };
477
478 sec_jr2: jr@3000 {
479 compatible = "fsl,sec-v4.2-job-ring",
480 "fsl,sec-v4.0-job-ring";
481 reg = <0x3000 0x1000>;
482 interrupts = <90 2 0 0>;
483 };
484
485 sec_jr3: jr@4000 {
486 compatible = "fsl,sec-v4.2-job-ring",
487 "fsl,sec-v4.0-job-ring";
488 reg = <0x4000 0x1000>;
489 interrupts = <91 2 0 0>;
490 };
491
492 rtic@6000 {
493 compatible = "fsl,sec-v4.2-rtic",
494 "fsl,sec-v4.0-rtic";
495 #address-cells = <1>;
496 #size-cells = <1>;
497 reg = <0x6000 0x100>;
498 ranges = <0x0 0x6100 0xe00>;
499
500 rtic_a: rtic-a@0 {
501 compatible = "fsl,sec-v4.2-rtic-memory",
502 "fsl,sec-v4.0-rtic-memory";
503 reg = <0x00 0x20 0x100 0x80>;
504 };
505
506 rtic_b: rtic-b@20 {
507 compatible = "fsl,sec-v4.2-rtic-memory",
508 "fsl,sec-v4.0-rtic-memory";
509 reg = <0x20 0x20 0x200 0x80>;
510 };
511
512 rtic_c: rtic-c@40 {
513 compatible = "fsl,sec-v4.2-rtic-memory",
514 "fsl,sec-v4.0-rtic-memory";
515 reg = <0x40 0x20 0x300 0x80>;
516 };
517
518 rtic_d: rtic-d@60 {
519 compatible = "fsl,sec-v4.2-rtic-memory",
520 "fsl,sec-v4.0-rtic-memory";
521 reg = <0x60 0x20 0x500 0x80>;
522 };
523 };
524 };
525
526 sec_mon: sec_mon@314000 {
527 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
528 reg = <0x314000 0x1000>;
529 interrupts = <93 2 0 0>;
530 };
531 };
532
533/*
534 rapidio0: rapidio@ffe0c0000
535*/
536
537 localbus@ffe124000 {
538 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
539 interrupts = <25 2 0 0>;
540 #address-cells = <2>;
541 #size-cells = <1>;
542 };
543
544 pci0: pcie@ffe200000 {
545 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
546 device_type = "pci";
547 #size-cells = <2>;
548 #address-cells = <3>;
549 bus-range = <0x0 0xff>;
550 clock-frequency = <0x1fca055>;
551 fsl,msi = <&msi0>;
552 interrupts = <16 2 1 15>;
553
554 pcie@0 {
555 reg = <0 0 0 0 0>;
556 #interrupt-cells = <1>;
557 #size-cells = <2>;
558 #address-cells = <3>;
559 device_type = "pci";
560 interrupts = <16 2 1 15>;
561 interrupt-map-mask = <0xf800 0 0 7>;
562 interrupt-map = <
563 /* IDSEL 0x0 */
564 0000 0 0 1 &mpic 40 1 0 0
565 0000 0 0 2 &mpic 1 1 0 0
566 0000 0 0 3 &mpic 2 1 0 0
567 0000 0 0 4 &mpic 3 1 0 0
568 >;
569 };
570 };
571
572 pci1: pcie@ffe201000 {
573 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
574 device_type = "pci";
575 #size-cells = <2>;
576 #address-cells = <3>;
577 bus-range = <0 0xff>;
578 clock-frequency = <0x1fca055>;
579 fsl,msi = <&msi1>;
580 interrupts = <16 2 1 14>;
581 pcie@0 {
582 reg = <0 0 0 0 0>;
583 #interrupt-cells = <1>;
584 #size-cells = <2>;
585 #address-cells = <3>;
586 device_type = "pci";
587 interrupts = <16 2 1 14>;
588 interrupt-map-mask = <0xf800 0 0 7>;
589 interrupt-map = <
590 /* IDSEL 0x0 */
591 0000 0 0 1 &mpic 41 1 0 0
592 0000 0 0 2 &mpic 5 1 0 0
593 0000 0 0 3 &mpic 6 1 0 0
594 0000 0 0 4 &mpic 7 1 0 0
595 >;
596 };
597 };
598
599 pci2: pcie@ffe202000 {
600 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
601 device_type = "pci";
602 #size-cells = <2>;
603 #address-cells = <3>;
604 bus-range = <0x0 0xff>;
605 clock-frequency = <0x1fca055>;
606 fsl,msi = <&msi2>;
607 interrupts = <16 2 1 13>;
608 pcie@0 {
609 reg = <0 0 0 0 0>;
610 #interrupt-cells = <1>;
611 #size-cells = <2>;
612 #address-cells = <3>;
613 device_type = "pci";
614 interrupts = <16 2 1 13>;
615 interrupt-map-mask = <0xf800 0 0 7>;
616 interrupt-map = <
617 /* IDSEL 0x0 */
618 0000 0 0 1 &mpic 42 1 0 0
619 0000 0 0 2 &mpic 9 1 0 0
620 0000 0 0 3 &mpic 10 1 0 0
621 0000 0 0 4 &mpic 11 1 0 0
622 >;
623 };
624 };
625
626 pci3: pcie@ffe203000 {
627 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
628 device_type = "pci";
629 #size-cells = <2>;
630 #address-cells = <3>;
631 bus-range = <0x0 0xff>;
632 clock-frequency = <0x1fca055>;
633 fsl,msi = <&msi2>;
634 interrupts = <16 2 1 12>;
635 pcie@0 {
636 reg = <0 0 0 0 0>;
637 #interrupt-cells = <1>;
638 #size-cells = <2>;
639 #address-cells = <3>;
640 device_type = "pci";
641 interrupts = <16 2 1 12>;
642 interrupt-map-mask = <0xf800 0 0 7>;
643 interrupt-map = <
644 /* IDSEL 0x0 */
645 0000 0 0 1 &mpic 43 1 0 0
646 0000 0 0 2 &mpic 0 1 0 0
647 0000 0 0 3 &mpic 4 1 0 0
648 0000 0 0 4 &mpic 8 1 0 0
649 >;
650 };
651 };
652};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 09:14:51 -0500