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authorRalf Baechle <ralf@linux-mips.org>2012-01-11 09:42:10 -0500
committerRalf Baechle <ralf@linux-mips.org>2012-01-11 09:42:10 -0500
commit7a5c3b8c5c27211846efe7029a3d2ee7087425e3 (patch)
tree92530366912b64c2826a882a79ebcfbe6ec28d59 /arch
parent39b741431af7f6f46b2e0e7f7f13ea2351fb4a5f (diff)
parent2af99920d56debcf879ac71a1934e8fcccdc713e (diff)
Merge branch 'next/alchemy' into mips-for-linux-next
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/alchemy/Kconfig60
-rw-r--r--arch/mips/alchemy/Makefile3
-rw-r--r--arch/mips/alchemy/Platform58
-rw-r--r--arch/mips/alchemy/board-gpr.c (renamed from arch/mips/alchemy/gpr/platform.c)81
-rw-r--r--arch/mips/alchemy/board-mtx1.c (renamed from arch/mips/alchemy/mtx-1/platform.c)93
-rw-r--r--arch/mips/alchemy/board-xxs1500.c154
-rw-r--r--arch/mips/alchemy/common/Makefile4
-rw-r--r--arch/mips/alchemy/common/dbdma.c46
-rw-r--r--arch/mips/alchemy/common/gpiolib.c42
-rw-r--r--arch/mips/alchemy/common/irq.c875
-rw-r--r--arch/mips/alchemy/common/platform.c31
-rw-r--r--arch/mips/alchemy/common/power.c3
-rw-r--r--arch/mips/alchemy/common/sleeper.S73
-rw-r--r--arch/mips/alchemy/common/time.c1
-rw-r--r--arch/mips/alchemy/common/vss.c84
-rw-r--r--arch/mips/alchemy/devboards/Makefile19
-rw-r--r--arch/mips/alchemy/devboards/bcsr.c11
-rw-r--r--arch/mips/alchemy/devboards/db1000.c565
-rw-r--r--arch/mips/alchemy/devboards/db1200.c (renamed from arch/mips/alchemy/devboards/db1200/platform.c)397
-rw-r--r--arch/mips/alchemy/devboards/db1200/Makefile1
-rw-r--r--arch/mips/alchemy/devboards/db1200/setup.c81
-rw-r--r--arch/mips/alchemy/devboards/db1300.c785
-rw-r--r--arch/mips/alchemy/devboards/db1550.c498
-rw-r--r--arch/mips/alchemy/devboards/db1x00/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c229
-rw-r--r--arch/mips/alchemy/devboards/db1x00/platform.c316
-rw-r--r--arch/mips/alchemy/devboards/pb1000/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1000/board_setup.c209
-rw-r--r--arch/mips/alchemy/devboards/pb1100.c (renamed from arch/mips/alchemy/devboards/pb1100/board_setup.c)92
-rw-r--r--arch/mips/alchemy/devboards/pb1100/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1100/platform.c77
-rw-r--r--arch/mips/alchemy/devboards/pb1200/Makefile5
-rw-r--r--arch/mips/alchemy/devboards/pb1200/board_setup.c174
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c339
-rw-r--r--arch/mips/alchemy/devboards/pb1500.c (renamed from arch/mips/alchemy/devboards/pb1500/board_setup.c)113
-rw-r--r--arch/mips/alchemy/devboards/pb1500/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1500/platform.c94
-rw-r--r--arch/mips/alchemy/devboards/pb1550.c (renamed from arch/mips/alchemy/devboards/pb1550/platform.c)112
-rw-r--r--arch/mips/alchemy/devboards/pb1550/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1550/board_setup.c80
-rw-r--r--arch/mips/alchemy/devboards/platform.c13
-rw-r--r--arch/mips/alchemy/devboards/prom.c11
-rw-r--r--arch/mips/alchemy/gpr/Makefile8
-rw-r--r--arch/mips/alchemy/gpr/board_setup.c75
-rw-r--r--arch/mips/alchemy/gpr/init.c63
-rw-r--r--arch/mips/alchemy/mtx-1/Makefile9
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c94
-rw-r--r--arch/mips/alchemy/mtx-1/init.c66
-rw-r--r--arch/mips/alchemy/xxs1500/Makefile8
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c93
-rw-r--r--arch/mips/alchemy/xxs1500/init.c63
-rw-r--r--arch/mips/alchemy/xxs1500/platform.c63
-rw-r--r--arch/mips/boot/compressed/uart-alchemy.c5
-rw-r--r--arch/mips/configs/db1000_defconfig369
-rw-r--r--arch/mips/configs/db1100_defconfig122
-rw-r--r--arch/mips/configs/db1300_defconfig391
-rw-r--r--arch/mips/configs/db1500_defconfig128
-rw-r--r--arch/mips/configs/db1550_defconfig288
-rw-r--r--arch/mips/configs/pb1200_defconfig170
-rw-r--r--arch/mips/include/asm/cpu.h1
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h273
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1100_mmc.h2
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1200fb.h14
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1550nd.h16
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h31
-rw-r--r--arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h3
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1300.h241
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio.h3
-rw-r--r--arch/mips/include/asm/mach-db1x00/bcsr.h36
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1200.h11
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1300.h40
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1x00.h79
-rw-r--r--arch/mips/include/asm/mach-db1x00/irq.h23
-rw-r--r--arch/mips/include/asm/mach-pb1x00/mc146818rtc.h34
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1000.h87
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1200.h139
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1550.h73
-rw-r--r--arch/mips/kernel/cpu-probe.c7
78 files changed, 5259 insertions, 3738 deletions
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 2a68be6a1b97..0faaab24376e 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -2,6 +2,10 @@
2config ALCHEMY_GPIOINT_AU1000 2config ALCHEMY_GPIOINT_AU1000
3 bool 3 bool
4 4
5# au1300-style GPIO/INT controller
6config ALCHEMY_GPIOINT_AU1300
7 bool
8
5# select this in your board config if you don't want to use the gpio 9# select this in your board config if you don't want to use the gpio
6# namespace as documented in the manuals. In this case however you need 10# namespace as documented in the manuals. In this case however you need
7# to create the necessary gpio_* functions in your board code/headers! 11# to create the necessary gpio_* functions in your board code/headers!
@@ -22,43 +26,29 @@ config MIPS_MTX1
22 select SYS_SUPPORTS_LITTLE_ENDIAN 26 select SYS_SUPPORTS_LITTLE_ENDIAN
23 select SYS_HAS_EARLY_PRINTK 27 select SYS_HAS_EARLY_PRINTK
24 28
25config MIPS_BOSPORUS
26 bool "Alchemy Bosporus board"
27 select ALCHEMY_GPIOINT_AU1000
28 select DMA_NONCOHERENT
29 select SYS_SUPPORTS_LITTLE_ENDIAN
30 select SYS_HAS_EARLY_PRINTK
31
32config MIPS_DB1000 29config MIPS_DB1000
33 bool "Alchemy DB1000 board" 30 bool "Alchemy DB1000/DB1500/DB1100 boards"
34 select ALCHEMY_GPIOINT_AU1000 31 select ALCHEMY_GPIOINT_AU1000
35 select DMA_NONCOHERENT 32 select DMA_NONCOHERENT
36 select HW_HAS_PCI 33 select HW_HAS_PCI
37 select SYS_SUPPORTS_LITTLE_ENDIAN 34 select MIPS_DISABLE_OBSOLETE_IDE
38 select SYS_HAS_EARLY_PRINTK 35 select SYS_SUPPORTS_BIG_ENDIAN
39
40config MIPS_DB1100
41 bool "Alchemy DB1100 board"
42 select ALCHEMY_GPIOINT_AU1000
43 select DMA_NONCOHERENT
44 select SYS_SUPPORTS_LITTLE_ENDIAN 36 select SYS_SUPPORTS_LITTLE_ENDIAN
45 select SYS_HAS_EARLY_PRINTK 37 select SYS_HAS_EARLY_PRINTK
46 38
47config MIPS_DB1200 39config MIPS_DB1200
48 bool "Alchemy DB1200 board" 40 bool "Alchemy DB1200/PB1200 board"
49 select ALCHEMY_GPIOINT_AU1000 41 select ALCHEMY_GPIOINT_AU1000
50 select DMA_COHERENT 42 select DMA_COHERENT
51 select MIPS_DISABLE_OBSOLETE_IDE 43 select MIPS_DISABLE_OBSOLETE_IDE
52 select SYS_SUPPORTS_LITTLE_ENDIAN 44 select SYS_SUPPORTS_LITTLE_ENDIAN
53 select SYS_HAS_EARLY_PRINTK 45 select SYS_HAS_EARLY_PRINTK
54 46
55config MIPS_DB1500 47config MIPS_DB1300
56 bool "Alchemy DB1500 board" 48 bool "NetLogic DB1300 board"
57 select ALCHEMY_GPIOINT_AU1000 49 select ALCHEMY_GPIOINT_AU1300
58 select DMA_NONCOHERENT 50 select DMA_COHERENT
59 select HW_HAS_PCI
60 select MIPS_DISABLE_OBSOLETE_IDE 51 select MIPS_DISABLE_OBSOLETE_IDE
61 select SYS_SUPPORTS_BIG_ENDIAN
62 select SYS_SUPPORTS_LITTLE_ENDIAN 52 select SYS_SUPPORTS_LITTLE_ENDIAN
63 select SYS_HAS_EARLY_PRINTK 53 select SYS_HAS_EARLY_PRINTK
64 54
@@ -66,27 +56,11 @@ config MIPS_DB1550
66 bool "Alchemy DB1550 board" 56 bool "Alchemy DB1550 board"
67 select ALCHEMY_GPIOINT_AU1000 57 select ALCHEMY_GPIOINT_AU1000
68 select HW_HAS_PCI 58 select HW_HAS_PCI
69 select DMA_NONCOHERENT 59 select DMA_COHERENT
70 select MIPS_DISABLE_OBSOLETE_IDE 60 select MIPS_DISABLE_OBSOLETE_IDE
71 select SYS_SUPPORTS_LITTLE_ENDIAN 61 select SYS_SUPPORTS_LITTLE_ENDIAN
72 select SYS_HAS_EARLY_PRINTK 62 select SYS_HAS_EARLY_PRINTK
73 63
74config MIPS_MIRAGE
75 bool "Alchemy Mirage board"
76 select DMA_NONCOHERENT
77 select ALCHEMY_GPIOINT_AU1000
78 select SYS_SUPPORTS_LITTLE_ENDIAN
79 select SYS_HAS_EARLY_PRINTK
80
81config MIPS_PB1000
82 bool "Alchemy PB1000 board"
83 select ALCHEMY_GPIOINT_AU1000
84 select DMA_NONCOHERENT
85 select HW_HAS_PCI
86 select SWAP_IO_SPACE
87 select SYS_SUPPORTS_LITTLE_ENDIAN
88 select SYS_HAS_EARLY_PRINTK
89
90config MIPS_PB1100 64config MIPS_PB1100
91 bool "Alchemy PB1100 board" 65 bool "Alchemy PB1100 board"
92 select ALCHEMY_GPIOINT_AU1000 66 select ALCHEMY_GPIOINT_AU1000
@@ -96,14 +70,6 @@ config MIPS_PB1100
96 select SYS_SUPPORTS_LITTLE_ENDIAN 70 select SYS_SUPPORTS_LITTLE_ENDIAN
97 select SYS_HAS_EARLY_PRINTK 71 select SYS_HAS_EARLY_PRINTK
98 72
99config MIPS_PB1200
100 bool "Alchemy PB1200 board"
101 select ALCHEMY_GPIOINT_AU1000
102 select DMA_NONCOHERENT
103 select MIPS_DISABLE_OBSOLETE_IDE
104 select SYS_SUPPORTS_LITTLE_ENDIAN
105 select SYS_HAS_EARLY_PRINTK
106
107config MIPS_PB1500 73config MIPS_PB1500
108 bool "Alchemy PB1500 board" 74 bool "Alchemy PB1500 board"
109 select ALCHEMY_GPIOINT_AU1000 75 select ALCHEMY_GPIOINT_AU1000
diff --git a/arch/mips/alchemy/Makefile b/arch/mips/alchemy/Makefile
new file mode 100644
index 000000000000..aac3b179bbc0
--- /dev/null
+++ b/arch/mips/alchemy/Makefile
@@ -0,0 +1,3 @@
1obj-$(CONFIG_MIPS_GPR) += board-gpr.o
2obj-$(CONFIG_MIPS_MTX1) += board-mtx1.o
3obj-$(CONFIG_MIPS_XXS1500) += board-xxs1500.o
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
index 96e9e41f1b2a..7956274de15f 100644
--- a/arch/mips/alchemy/Platform
+++ b/arch/mips/alchemy/Platform
@@ -5,62 +5,31 @@ platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/
5 5
6 6
7# 7#
8# AMD Alchemy Pb1000 eval board
9#
10platform-$(CONFIG_MIPS_PB1000) += alchemy/devboards/
11cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
12load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000
13
14#
15# AMD Alchemy Pb1100 eval board 8# AMD Alchemy Pb1100 eval board
16# 9#
17platform-$(CONFIG_MIPS_PB1100) += alchemy/devboards/ 10platform-$(CONFIG_MIPS_PB1100) += alchemy/devboards/
18cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
19load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000 11load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000
20 12
21# 13#
22# AMD Alchemy Pb1500 eval board 14# AMD Alchemy Pb1500 eval board
23# 15#
24platform-$(CONFIG_MIPS_PB1500) += alchemy/devboards/ 16platform-$(CONFIG_MIPS_PB1500) += alchemy/devboards/
25cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
26load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000 17load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000
27 18
28# 19#
29# AMD Alchemy Pb1550 eval board 20# AMD Alchemy Pb1550 eval board
30# 21#
31platform-$(CONFIG_MIPS_PB1550) += alchemy/devboards/ 22platform-$(CONFIG_MIPS_PB1550) += alchemy/devboards/
32cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
33load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 23load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
34 24
35# 25#
36# AMD Alchemy Pb1200 eval board 26# AMD Alchemy Db1000/Db1500/Db1100 eval boards
37#
38platform-$(CONFIG_MIPS_PB1200) += alchemy/devboards/
39cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
40load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000
41
42#
43# AMD Alchemy Db1000 eval board
44# 27#
45platform-$(CONFIG_MIPS_DB1000) += alchemy/devboards/ 28platform-$(CONFIG_MIPS_DB1000) += alchemy/devboards/
46cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 29cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
47load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000 30load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000
48 31
49# 32#
50# AMD Alchemy Db1100 eval board
51#
52platform-$(CONFIG_MIPS_DB1100) += alchemy/devboards/
53cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
54load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000
55
56#
57# AMD Alchemy Db1500 eval board
58#
59platform-$(CONFIG_MIPS_DB1500) += alchemy/devboards/
60cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
61load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000
62
63#
64# AMD Alchemy Db1550 eval board 33# AMD Alchemy Db1550 eval board
65# 34#
66platform-$(CONFIG_MIPS_DB1550) += alchemy/devboards/ 35platform-$(CONFIG_MIPS_DB1550) += alchemy/devboards/
@@ -68,42 +37,35 @@ cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
68load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 37load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000
69 38
70# 39#
71# AMD Alchemy Db1200 eval board 40# AMD Alchemy Db1200/Pb1200 eval boards
72# 41#
73platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/ 42platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/
74cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 43cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
75load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 44load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000
76 45
77# 46#
78# AMD Alchemy Bosporus eval board 47# NetLogic DBAu1300 development platform
79#
80platform-$(CONFIG_MIPS_BOSPORUS) += alchemy/devboards/
81cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
82load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000
83
84#
85# AMD Alchemy Mirage eval board
86# 48#
87platform-$(CONFIG_MIPS_MIRAGE) += alchemy/devboards/ 49platform-$(CONFIG_MIPS_DB1300) += alchemy/devboards/
88cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 50cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
89load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000 51load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000
90 52
91# 53#
92# 4G-Systems eval board 54# 4G-Systems MTX-1 "MeshCube" wireless router
93# 55#
94platform-$(CONFIG_MIPS_MTX1) += alchemy/mtx-1/ 56platform-$(CONFIG_MIPS_MTX1) += alchemy/
95load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000 57load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000
96 58
97# 59#
98# MyCable eval board 60# MyCable eval board
99# 61#
100platform-$(CONFIG_MIPS_XXS1500) += alchemy/xxs1500/ 62platform-$(CONFIG_MIPS_XXS1500) += alchemy/
101load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 63load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
102 64
103# 65#
104# Trapeze ITS GRP board 66# Trapeze ITS GRP board
105# 67#
106platform-$(CONFIG_MIPS_GPR) += alchemy/gpr/ 68platform-$(CONFIG_MIPS_GPR) += alchemy/
107load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000 69load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000
108 70
109# boards can specify their own <gpio.h> in one of their include dirs. 71# boards can specify their own <gpio.h> in one of their include dirs.
diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/board-gpr.c
index 982ce85db60d..ba3259086b9d 100644
--- a/arch/mips/alchemy/gpr/platform.c
+++ b/arch/mips/alchemy/board-gpr.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * GPR board platform device registration 2 * GPR board platform device registration (Au1550)
3 * 3 *
4 * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de> 4 * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
5 * 5 *
@@ -18,16 +18,89 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/delay.h>
21#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/kernel.h>
22#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/pm.h>
23#include <linux/mtd/partitions.h> 27#include <linux/mtd/partitions.h>
24#include <linux/mtd/physmap.h> 28#include <linux/mtd/physmap.h>
25#include <linux/leds.h> 29#include <linux/leds.h>
26#include <linux/gpio.h> 30#include <linux/gpio.h>
27#include <linux/i2c.h> 31#include <linux/i2c.h>
28#include <linux/i2c-gpio.h> 32#include <linux/i2c-gpio.h>
29 33#include <asm/bootinfo.h>
34#include <asm/reboot.h>
30#include <asm/mach-au1x00/au1000.h> 35#include <asm/mach-au1x00/au1000.h>
36#include <prom.h>
37
38const char *get_system_type(void)
39{
40 return "GPR";
41}
42
43void __init prom_init(void)
44{
45 unsigned char *memsize_str;
46 unsigned long memsize;
47
48 prom_argc = fw_arg0;
49 prom_argv = (char **)fw_arg1;
50 prom_envp = (char **)fw_arg2;
51
52 prom_init_cmdline();
53
54 memsize_str = prom_getenv("memsize");
55 if (!memsize_str)
56 memsize = 0x04000000;
57 else
58 strict_strtoul(memsize_str, 0, &memsize);
59 add_memory_region(0, memsize, BOOT_MEM_RAM);
60}
61
62void prom_putchar(unsigned char c)
63{
64 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
65}
66
67static void gpr_reset(char *c)
68{
69 /* switch System-LED to orange (red# and green# on) */
70 alchemy_gpio_direction_output(4, 0);
71 alchemy_gpio_direction_output(5, 0);
72
73 /* trigger watchdog to reset board in 200ms */
74 printk(KERN_EMERG "Triggering watchdog soft reset...\n");
75 raw_local_irq_disable();
76 alchemy_gpio_direction_output(1, 0);
77 udelay(1);
78 alchemy_gpio_set_value(1, 1);
79 while (1)
80 cpu_wait();
81}
82
83static void gpr_power_off(void)
84{
85 while (1)
86 cpu_wait();
87}
88
89void __init board_setup(void)
90{
91 printk(KERN_INFO "Trapeze ITS GPR board\n");
92
93 pm_power_off = gpr_power_off;
94 _machine_halt = gpr_power_off;
95 _machine_restart = gpr_reset;
96
97 /* Enable UART1/3 */
98 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
99 alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
100
101 /* Take away Reset of UMTS-card */
102 alchemy_gpio_direction_output(215, 1);
103}
31 104
32/* 105/*
33 * Watchdog 106 * Watchdog
@@ -152,7 +225,7 @@ static struct i2c_gpio_platform_data gpr_i2c_data = {
152 .scl_is_open_drain = 1, 225 .scl_is_open_drain = 1,
153 .udelay = 2, /* ~100 kHz */ 226 .udelay = 2, /* ~100 kHz */
154 .timeout = HZ, 227 .timeout = HZ,
155 }; 228};
156 229
157static struct platform_device gpr_i2c_device = { 230static struct platform_device gpr_i2c_device = {
158 .name = "i2c-gpio", 231 .name = "i2c-gpio",
@@ -184,7 +257,7 @@ static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
184 else if ((slot == 0) && (pin == 2)) 257 else if ((slot == 0) && (pin == 2))
185 return AU1550_PCI_INTB; 258 return AU1550_PCI_INTB;
186 259
187 return -1; 260 return 0xff;
188} 261}
189 262
190static struct alchemy_pci_platdata gpr_pci_pd = { 263static struct alchemy_pci_platdata gpr_pci_pd = {
diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/board-mtx1.c
index cc47b6868ca3..295f1a95f745 100644
--- a/arch/mips/alchemy/mtx-1/platform.c
+++ b/arch/mips/alchemy/board-mtx1.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * MTX-1 platform devices registration 2 * MTX-1 platform devices registration (Au1500)
3 * 3 *
4 * Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org> 4 * Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org>
5 * 5 *
@@ -19,6 +19,8 @@
19 */ 19 */
20 20
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/kernel.h>
22#include <linux/platform_device.h> 24#include <linux/platform_device.h>
23#include <linux/leds.h> 25#include <linux/leds.h>
24#include <linux/gpio.h> 26#include <linux/gpio.h>
@@ -27,8 +29,85 @@
27#include <linux/mtd/partitions.h> 29#include <linux/mtd/partitions.h>
28#include <linux/mtd/physmap.h> 30#include <linux/mtd/physmap.h>
29#include <mtd/mtd-abi.h> 31#include <mtd/mtd-abi.h>
30 32#include <asm/bootinfo.h>
33#include <asm/reboot.h>
34#include <asm/mach-au1x00/au1000.h>
31#include <asm/mach-au1x00/au1xxx_eth.h> 35#include <asm/mach-au1x00/au1xxx_eth.h>
36#include <prom.h>
37
38const char *get_system_type(void)
39{
40 return "MTX-1";
41}
42
43void __init prom_init(void)
44{
45 unsigned char *memsize_str;
46 unsigned long memsize;
47
48 prom_argc = fw_arg0;
49 prom_argv = (char **)fw_arg1;
50 prom_envp = (char **)fw_arg2;
51
52 prom_init_cmdline();
53
54 memsize_str = prom_getenv("memsize");
55 if (!memsize_str)
56 memsize = 0x04000000;
57 else
58 strict_strtoul(memsize_str, 0, &memsize);
59 add_memory_region(0, memsize, BOOT_MEM_RAM);
60}
61
62void prom_putchar(unsigned char c)
63{
64 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
65}
66
67static void mtx1_reset(char *c)
68{
69 /* Jump to the reset vector */
70 __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000));
71}
72
73static void mtx1_power_off(void)
74{
75 while (1)
76 asm volatile (
77 " .set mips32 \n"
78 " wait \n"
79 " .set mips0 \n");
80}
81
82void __init board_setup(void)
83{
84#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
85 /* Enable USB power switch */
86 alchemy_gpio_direction_output(204, 0);
87#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
88
89 /* Initialize sys_pinfunc */
90 au_writel(SYS_PF_NI2, SYS_PINFUNC);
91
92 /* Initialize GPIO */
93 au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR);
94 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
95 alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
96 alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
97 alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */
98
99 /* Enable LED and set it to green */
100 alchemy_gpio_direction_output(211, 1); /* green on */
101 alchemy_gpio_direction_output(212, 0); /* red off */
102
103 pm_power_off = mtx1_power_off;
104 _machine_halt = mtx1_power_off;
105 _machine_restart = mtx1_reset;
106
107 printk(KERN_INFO "4G Systems MTX-1 Board\n");
108}
109
110/******************************************************************************/
32 111
33static struct gpio_keys_button mtx1_gpio_button[] = { 112static struct gpio_keys_button mtx1_gpio_button[] = {
34 { 113 {
@@ -195,7 +274,6 @@ static struct platform_device mtx1_pci_host = {
195 .resource = alchemy_pci_host_res, 274 .resource = alchemy_pci_host_res,
196}; 275};
197 276
198
199static struct __initdata platform_device * mtx1_devs[] = { 277static struct __initdata platform_device * mtx1_devs[] = {
200 &mtx1_pci_host, 278 &mtx1_pci_host,
201 &mtx1_gpio_leds, 279 &mtx1_gpio_leds,
@@ -206,13 +284,19 @@ static struct __initdata platform_device * mtx1_devs[] = {
206 284
207static struct au1000_eth_platform_data mtx1_au1000_eth0_pdata = { 285static struct au1000_eth_platform_data mtx1_au1000_eth0_pdata = {
208 .phy_search_highest_addr = 1, 286 .phy_search_highest_addr = 1,
209 .phy1_search_mac0 = 1, 287 .phy1_search_mac0 = 1,
210}; 288};
211 289
212static int __init mtx1_register_devices(void) 290static int __init mtx1_register_devices(void)
213{ 291{
214 int rc; 292 int rc;
215 293
294 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_HIGH);
295 irq_set_irq_type(AU1500_GPIO201_INT, IRQ_TYPE_LEVEL_LOW);
296 irq_set_irq_type(AU1500_GPIO202_INT, IRQ_TYPE_LEVEL_LOW);
297 irq_set_irq_type(AU1500_GPIO203_INT, IRQ_TYPE_LEVEL_LOW);
298 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
299
216 au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata); 300 au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata);
217 301
218 rc = gpio_request(mtx1_gpio_button[0].gpio, 302 rc = gpio_request(mtx1_gpio_button[0].gpio,
@@ -226,5 +310,4 @@ static int __init mtx1_register_devices(void)
226out: 310out:
227 return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs)); 311 return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs));
228} 312}
229
230arch_initcall(mtx1_register_devices); 313arch_initcall(mtx1_register_devices);
diff --git a/arch/mips/alchemy/board-xxs1500.c b/arch/mips/alchemy/board-xxs1500.c
new file mode 100644
index 000000000000..bd5513650293
--- /dev/null
+++ b/arch/mips/alchemy/board-xxs1500.c
@@ -0,0 +1,154 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * MyCable XXS1500 board support
4 *
5 * Copyright 2003, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/platform_device.h>
27#include <linux/gpio.h>
28#include <linux/delay.h>
29#include <linux/pm.h>
30#include <asm/bootinfo.h>
31#include <asm/reboot.h>
32#include <asm/mach-au1x00/au1000.h>
33#include <prom.h>
34
35const char *get_system_type(void)
36{
37 return "XXS1500";
38}
39
40void __init prom_init(void)
41{
42 unsigned char *memsize_str;
43 unsigned long memsize;
44
45 prom_argc = fw_arg0;
46 prom_argv = (char **)fw_arg1;
47 prom_envp = (char **)fw_arg2;
48
49 prom_init_cmdline();
50
51 memsize_str = prom_getenv("memsize");
52 if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
53 memsize = 0x04000000;
54
55 add_memory_region(0, memsize, BOOT_MEM_RAM);
56}
57
58void prom_putchar(unsigned char c)
59{
60 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
61}
62
63static void xxs1500_reset(char *c)
64{
65 /* Jump to the reset vector */
66 __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000));
67}
68
69static void xxs1500_power_off(void)
70{
71 while (1)
72 asm volatile (
73 " .set mips32 \n"
74 " wait \n"
75 " .set mips0 \n");
76}
77
78void __init board_setup(void)
79{
80 u32 pin_func;
81
82 pm_power_off = xxs1500_power_off;
83 _machine_halt = xxs1500_power_off;
84 _machine_restart = xxs1500_reset;
85
86 alchemy_gpio1_input_enable();
87 alchemy_gpio2_enable();
88
89 /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
90 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
91 pin_func |= SYS_PF_UR3;
92 au_writel(pin_func, SYS_PINFUNC);
93
94 /* Enable UART */
95 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
96 /* Enable DTR (MCR bit 0) = USB power up */
97 __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
98 wmb();
99}
100
101/******************************************************************************/
102
103static struct resource xxs1500_pcmcia_res[] = {
104 {
105 .name = "pcmcia-io",
106 .flags = IORESOURCE_MEM,
107 .start = AU1000_PCMCIA_IO_PHYS_ADDR,
108 .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
109 },
110 {
111 .name = "pcmcia-attr",
112 .flags = IORESOURCE_MEM,
113 .start = AU1000_PCMCIA_ATTR_PHYS_ADDR,
114 .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
115 },
116 {
117 .name = "pcmcia-mem",
118 .flags = IORESOURCE_MEM,
119 .start = AU1000_PCMCIA_MEM_PHYS_ADDR,
120 .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
121 },
122};
123
124static struct platform_device xxs1500_pcmcia_dev = {
125 .name = "xxs1500_pcmcia",
126 .id = -1,
127 .num_resources = ARRAY_SIZE(xxs1500_pcmcia_res),
128 .resource = xxs1500_pcmcia_res,
129};
130
131static struct platform_device *xxs1500_devs[] __initdata = {
132 &xxs1500_pcmcia_dev,
133};
134
135static int __init xxs1500_dev_init(void)
136{
137 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_HIGH);
138 irq_set_irq_type(AU1500_GPIO201_INT, IRQ_TYPE_LEVEL_LOW);
139 irq_set_irq_type(AU1500_GPIO202_INT, IRQ_TYPE_LEVEL_LOW);
140 irq_set_irq_type(AU1500_GPIO203_INT, IRQ_TYPE_LEVEL_LOW);
141 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
142 irq_set_irq_type(AU1500_GPIO207_INT, IRQ_TYPE_LEVEL_LOW);
143
144 irq_set_irq_type(AU1500_GPIO0_INT, IRQ_TYPE_LEVEL_LOW);
145 irq_set_irq_type(AU1500_GPIO1_INT, IRQ_TYPE_LEVEL_LOW);
146 irq_set_irq_type(AU1500_GPIO2_INT, IRQ_TYPE_LEVEL_LOW);
147 irq_set_irq_type(AU1500_GPIO3_INT, IRQ_TYPE_LEVEL_LOW);
148 irq_set_irq_type(AU1500_GPIO4_INT, IRQ_TYPE_LEVEL_LOW); /* CF irq */
149 irq_set_irq_type(AU1500_GPIO5_INT, IRQ_TYPE_LEVEL_LOW);
150
151 return platform_add_devices(xxs1500_devs,
152 ARRAY_SIZE(xxs1500_devs));
153}
154device_initcall(xxs1500_dev_init);
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 811ece7b22e3..407ebc00e661 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -6,9 +6,7 @@
6# 6#
7 7
8obj-y += prom.o time.o clocks.o platform.o power.o setup.o \ 8obj-y += prom.o time.o clocks.o platform.o power.o setup.o \
9 sleeper.o dma.o dbdma.o 9 sleeper.o dma.o dbdma.o vss.o irq.o
10
11obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
12 10
13# optional gpiolib support 11# optional gpiolib support
14ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) 12ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 9ba407b4fc97..cf02d7dc2df0 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -148,6 +148,50 @@ static dbdev_tab_t au1200_dbdev_tab[] __initdata = {
148 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 148 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
149}; 149};
150 150
151static dbdev_tab_t au1300_dbdev_tab[] __initdata = {
152 { AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 },
153 { AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 },
154 { AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x10101004, 0, 0 },
155 { AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 },
156 { AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x10102004, 0, 0 },
157 { AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 },
158 { AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x10103004, 0, 0 },
159 { AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 },
160
161 { AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
162 { AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
163 { AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 },
164 { AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 },
165
166 { AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
167 { AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
168
169 { AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 },
170 { AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 },
171 { AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 },
172 { AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 },
173 { AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 },
174 { AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 },
175 { AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 },
176 { AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 },
177
178 { AU1300_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
179 { AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
180
181 { AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 },
182 { AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 },
183
184 { AU1300_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
185
186 { AU1300_DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 },
187
188 { AU1300_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
189 { AU1300_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
190
191 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
192 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
193};
194
151/* 32 predefined plus 32 custom */ 195/* 32 predefined plus 32 custom */
152#define DBDEV_TAB_SIZE 64 196#define DBDEV_TAB_SIZE 64
153 197
@@ -1037,6 +1081,8 @@ static int __init alchemy_dbdma_init(void)
1037 return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab); 1081 return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
1038 case ALCHEMY_CPU_AU1200: 1082 case ALCHEMY_CPU_AU1200:
1039 return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab); 1083 return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
1084 case ALCHEMY_CPU_AU1300:
1085 return dbdma_setup(AU1300_DDMA_INT, au1300_dbdev_tab);
1040 } 1086 }
1041 return 0; 1087 return 0;
1042} 1088}
diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c
index 91fb4d9e30fd..f1b50f0c01db 100644
--- a/arch/mips/alchemy/common/gpiolib.c
+++ b/arch/mips/alchemy/common/gpiolib.c
@@ -27,6 +27,7 @@
27 * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail! 27 * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
28 * au1000 SoC have only one GPIO block : GPIO1 28 * au1000 SoC have only one GPIO block : GPIO1
29 * Au1100, Au15x0, Au12x0 have a second one : GPIO2 29 * Au1100, Au15x0, Au12x0 have a second one : GPIO2
30 * Au1300 is totally different: 1 block with up to 128 GPIOs
30 */ 31 */
31 32
32#include <linux/init.h> 33#include <linux/init.h>
@@ -35,6 +36,7 @@
35#include <linux/types.h> 36#include <linux/types.h>
36#include <linux/gpio.h> 37#include <linux/gpio.h>
37#include <asm/mach-au1x00/gpio-au1000.h> 38#include <asm/mach-au1x00/gpio-au1000.h>
39#include <asm/mach-au1x00/gpio-au1300.h>
38 40
39static int gpio2_get(struct gpio_chip *chip, unsigned offset) 41static int gpio2_get(struct gpio_chip *chip, unsigned offset)
40{ 42{
@@ -115,6 +117,43 @@ struct gpio_chip alchemy_gpio_chip[] = {
115 }, 117 },
116}; 118};
117 119
120static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off)
121{
122 return au1300_gpio_get_value(off + AU1300_GPIO_BASE);
123}
124
125static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)
126{
127 au1300_gpio_set_value(off + AU1300_GPIO_BASE, v);
128}
129
130static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off)
131{
132 return au1300_gpio_direction_input(off + AU1300_GPIO_BASE);
133}
134
135static int alchemy_gpic_dir_output(struct gpio_chip *chip, unsigned int off,
136 int v)
137{
138 return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v);
139}
140
141static int alchemy_gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off)
142{
143 return au1300_gpio_to_irq(off + AU1300_GPIO_BASE);
144}
145
146static struct gpio_chip au1300_gpiochip = {
147 .label = "alchemy-gpic",
148 .direction_input = alchemy_gpic_dir_input,
149 .direction_output = alchemy_gpic_dir_output,
150 .get = alchemy_gpic_get,
151 .set = alchemy_gpic_set,
152 .to_irq = alchemy_gpic_gpio_to_irq,
153 .base = AU1300_GPIO_BASE,
154 .ngpio = AU1300_GPIO_NUM,
155};
156
118static int __init alchemy_gpiochip_init(void) 157static int __init alchemy_gpiochip_init(void)
119{ 158{
120 int ret = 0; 159 int ret = 0;
@@ -127,6 +166,9 @@ static int __init alchemy_gpiochip_init(void)
127 ret = gpiochip_add(&alchemy_gpio_chip[0]); 166 ret = gpiochip_add(&alchemy_gpio_chip[0]);
128 ret |= gpiochip_add(&alchemy_gpio_chip[1]); 167 ret |= gpiochip_add(&alchemy_gpio_chip[1]);
129 break; 168 break;
169 case ALCHEMY_CPU_AU1300:
170 ret = gpiochip_add(&au1300_gpiochip);
171 break;
130 } 172 }
131 return ret; 173 return ret;
132} 174}
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 8b60ba0675e2..94fbcd19eb9c 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -25,19 +25,15 @@
25 * 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */ 26 */
27 27
28#include <linux/bitops.h> 28#include <linux/export.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/interrupt.h> 30#include <linux/interrupt.h>
31#include <linux/irq.h>
32#include <linux/slab.h> 31#include <linux/slab.h>
33#include <linux/syscore_ops.h> 32#include <linux/syscore_ops.h>
34 33
35#include <asm/irq_cpu.h> 34#include <asm/irq_cpu.h>
36#include <asm/mipsregs.h>
37#include <asm/mach-au1x00/au1000.h> 35#include <asm/mach-au1x00/au1000.h>
38#ifdef CONFIG_MIPS_PB1000 36#include <asm/mach-au1x00/gpio-au1300.h>
39#include <asm/mach-pb1x00/pb1000.h>
40#endif
41 37
42/* Interrupt Controller register offsets */ 38/* Interrupt Controller register offsets */
43#define IC_CFG0RD 0x40 39#define IC_CFG0RD 0x40
@@ -69,7 +65,17 @@
69#define IC_FALLINGCLR 0x7C 65#define IC_FALLINGCLR 0x7C
70#define IC_TESTBIT 0x80 66#define IC_TESTBIT 0x80
71 67
72static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type); 68/* per-processor fixed function irqs */
69struct alchemy_irqmap {
70 int irq; /* linux IRQ number */
71 int type; /* IRQ_TYPE_ */
72 int prio; /* irq priority, 0 highest, 3 lowest */
73 int internal; /* GPIC: internal source (no ext. pin)? */
74};
75
76static int au1x_ic_settype(struct irq_data *d, unsigned int type);
77static int au1300_gpic_settype(struct irq_data *d, unsigned int type);
78
73 79
74/* NOTE on interrupt priorities: The original writers of this code said: 80/* NOTE on interrupt priorities: The original writers of this code said:
75 * 81 *
@@ -77,176 +83,207 @@ static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type);
77 * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT) 83 * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT)
78 * needs the highest priority. 84 * needs the highest priority.
79 */ 85 */
80 86struct alchemy_irqmap au1000_irqmap[] __initdata = {
81/* per-processor fixed function irqs */ 87 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
82struct au1xxx_irqmap { 88 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
83 int im_irq; 89 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
84 int im_type; 90 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
85 int im_request; /* set 1 to get higher priority */ 91 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
92 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
93 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
94 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
95 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
96 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
97 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
98 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
99 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
100 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
101 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
102 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
103 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
104 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
105 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
106 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
107 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
108 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
109 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
110 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
111 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 },
112 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
113 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
114 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
115 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
116 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
117 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
118 { -1, },
86}; 119};
87 120
88struct au1xxx_irqmap au1000_irqmap[] __initdata = { 121struct alchemy_irqmap au1500_irqmap[] __initdata = {
89 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 122 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
90 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 123 { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 },
91 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 124 { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 },
92 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 125 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
93 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 126 { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 },
94 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 127 { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 },
95 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 128 { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
96 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 129 { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
97 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 130 { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
98 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 131 { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
99 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 132 { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
100 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 133 { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
101 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 134 { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
102 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 135 { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
103 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 136 { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
104 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 137 { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
105 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 138 { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
106 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 139 { AU1500_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
107 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 140 { AU1500_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
108 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 141 { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
109 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 142 { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
110 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 143 { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
111 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 144 { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 },
112 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 145 { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
113 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 146 { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
114 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 147 { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
115 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 148 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
116 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 149 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
117 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 150 { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
118 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
119 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
120 { -1, }, 151 { -1, },
121}; 152};
122 153
123struct au1xxx_irqmap au1500_irqmap[] __initdata = { 154struct alchemy_irqmap au1100_irqmap[] __initdata = {
124 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 155 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
125 { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, 156 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
126 { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, 157 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
127 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 158 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
128 { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, 159 { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
129 { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, 160 { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
130 { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 161 { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
131 { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 162 { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
132 { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 163 { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
133 { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 164 { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
134 { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 165 { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
135 { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 166 { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
136 { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 167 { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
137 { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 168 { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
138 { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 169 { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
139 { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 170 { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
140 { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 171 { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
141 { AU1500_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 172 { AU1100_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
142 { AU1500_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 173 { AU1100_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
143 { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 174 { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
144 { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 175 { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
145 { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 176 { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
146 { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 177 { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
147 { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 178 { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
148 { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 179 { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 },
149 { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 180 { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
150 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 181 { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
151 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 182 { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
152 { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, 183 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
184 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
185 { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
153 { -1, }, 186 { -1, },
154}; 187};
155 188
156struct au1xxx_irqmap au1100_irqmap[] __initdata = { 189struct alchemy_irqmap au1550_irqmap[] __initdata = {
157 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 190 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
158 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 191 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 },
159 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 192 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 },
160 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 193 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
161 { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 194 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
162 { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 195 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 },
163 { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 196 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 },
164 { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 197 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
165 { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 198 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
166 { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 199 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
167 { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 200 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
168 { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 201 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
169 { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 202 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
170 { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 203 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
171 { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 204 { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
172 { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 205 { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
173 { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 206 { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
174 { AU1100_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 207 { AU1550_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
175 { AU1100_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 208 { AU1550_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
176 { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 209 { AU1550_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
177 { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 210 { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
178 { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 211 { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
179 { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 212 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
180 { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 213 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 },
181 { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 214 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
182 { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 215 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
183 { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 216 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
184 { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 217 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
185 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
186 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
187 { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
188 { -1, }, 218 { -1, },
189}; 219};
190 220
191struct au1xxx_irqmap au1550_irqmap[] __initdata = { 221struct alchemy_irqmap au1200_irqmap[] __initdata = {
192 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 222 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
193 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, 223 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
194 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, 224 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
195 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 225 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
196 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 226 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
197 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, 227 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
198 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, 228 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
199 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 229 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
200 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 230 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
201 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 231 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
202 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 232 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
203 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 233 { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
204 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 234 { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
205 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 235 { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
206 { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 236 { AU1200_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
207 { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 237 { AU1200_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
208 { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 238 { AU1200_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
209 { AU1550_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 239 { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
210 { AU1550_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 240 { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
211 { AU1550_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 241 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
212 { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 242 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
213 { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 243 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
214 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, 244 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
215 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
216 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
217 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
218 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
219 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
220 { -1, }, 245 { -1, },
221}; 246};
222 247
223struct au1xxx_irqmap au1200_irqmap[] __initdata = { 248static struct alchemy_irqmap au1300_irqmap[] __initdata = {
224 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 249 /* multifunction: gpio pin or device */
225 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 }, 250 { AU1300_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
226 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 251 { AU1300_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
227 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 252 { AU1300_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
228 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 253 { AU1300_SD1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
229 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 254 { AU1300_SD2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
230 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 255 { AU1300_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
231 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 256 { AU1300_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
232 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 257 { AU1300_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
233 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 258 { AU1300_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
234 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 259 { AU1300_NAND_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
235 { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 260 /* au1300 internal */
236 { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 261 { AU1300_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
237 { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 262 { AU1300_MMU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
238 { AU1200_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 263 { AU1300_MPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
239 { AU1200_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 264 { AU1300_GPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
240 { AU1200_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 265 { AU1300_UDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
241 { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 266 { AU1300_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
242 { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 267 { AU1300_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
243 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, 268 { AU1300_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
244 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 269 { AU1300_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
245 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 270 { AU1300_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
246 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 271 { AU1300_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
247 { -1, }, 272 { AU1300_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
273 { AU1300_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 1, },
274 { AU1300_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
275 { AU1300_SD0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
276 { AU1300_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
277 { AU1300_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
278 { AU1300_BSA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
279 { AU1300_MPE_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
280 { AU1300_ITE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
281 { AU1300_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
282 { AU1300_CIM_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
283 { -1, }, /* terminator */
248}; 284};
249 285
286/******************************************************************************/
250 287
251static void au1x_ic0_unmask(struct irq_data *d) 288static void au1x_ic0_unmask(struct irq_data *d)
252{ 289{
@@ -265,14 +302,6 @@ static void au1x_ic1_unmask(struct irq_data *d)
265 302
266 __raw_writel(1 << bit, base + IC_MASKSET); 303 __raw_writel(1 << bit, base + IC_MASKSET);
267 __raw_writel(1 << bit, base + IC_WAKESET); 304 __raw_writel(1 << bit, base + IC_WAKESET);
268
269/* very hacky. does the pb1000 cpld auto-disable this int?
270 * nowhere in the current kernel sources is it disabled. --mlau
271 */
272#if defined(CONFIG_MIPS_PB1000)
273 if (d->irq == AU1000_GPIO15_INT)
274 __raw_writel(0x4000, (void __iomem *)PB1000_MDR); /* enable int */
275#endif
276 wmb(); 305 wmb();
277} 306}
278 307
@@ -470,40 +499,219 @@ static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type)
470 return ret; 499 return ret;
471} 500}
472 501
473asmlinkage void plat_irq_dispatch(void) 502/******************************************************************************/
503
504/*
505 * au1300_gpic_chgcfg - change PIN configuration.
506 * @gpio: pin to change (0-based GPIO number from datasheet).
507 * @clr: clear all bits set in 'clr'.
508 * @set: set these bits.
509 *
510 * modifies a pins' configuration register, bits set in @clr will
511 * be cleared in the register, bits in @set will be set.
512 */
513static inline void au1300_gpic_chgcfg(unsigned int gpio,
514 unsigned long clr,
515 unsigned long set)
516{
517 void __iomem *r = AU1300_GPIC_ADDR;
518 unsigned long l;
519
520 r += gpio * 4; /* offset into pin config array */
521 l = __raw_readl(r + AU1300_GPIC_PINCFG);
522 l &= ~clr;
523 l |= set;
524 __raw_writel(l, r + AU1300_GPIC_PINCFG);
525 wmb();
526}
527
528/*
529 * au1300_pinfunc_to_gpio - assign a pin as GPIO input (GPIO ctrl).
530 * @pin: pin (0-based GPIO number from datasheet).
531 *
532 * Assigns a GPIO pin to the GPIO controller, so its level can either
533 * be read or set through the generic GPIO functions.
534 * If you need a GPOUT, use au1300_gpio_set_value(pin, 0/1).
535 * REVISIT: is this function really necessary?
536 */
537void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio)
538{
539 au1300_gpio_direction_input(gpio + AU1300_GPIO_BASE);
540}
541EXPORT_SYMBOL_GPL(au1300_pinfunc_to_gpio);
542
543/*
544 * au1300_pinfunc_to_dev - assign a pin to the device function.
545 * @pin: pin (0-based GPIO number from datasheet).
546 *
547 * Assigns a GPIO pin to its associated device function; the pin will be
548 * driven by the device and not through GPIO functions.
549 */
550void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio)
551{
552 void __iomem *r = AU1300_GPIC_ADDR;
553 unsigned long bit;
554
555 r += GPIC_GPIO_BANKOFF(gpio);
556 bit = GPIC_GPIO_TO_BIT(gpio);
557 __raw_writel(bit, r + AU1300_GPIC_DEVSEL);
558 wmb();
559}
560EXPORT_SYMBOL_GPL(au1300_pinfunc_to_dev);
561
562/*
563 * au1300_set_irq_priority - set internal priority of IRQ.
564 * @irq: irq to set priority (linux irq number).
565 * @p: priority (0 = highest, 3 = lowest).
566 */
567void au1300_set_irq_priority(unsigned int irq, int p)
474{ 568{
475 unsigned int pending = read_c0_status() & read_c0_cause(); 569 irq -= ALCHEMY_GPIC_INT_BASE;
476 unsigned long s, off; 570 au1300_gpic_chgcfg(irq, GPIC_CFG_IL_MASK, GPIC_CFG_IL_SET(p));
477 571}
478 if (pending & CAUSEF_IP7) { 572EXPORT_SYMBOL_GPL(au1300_set_irq_priority);
479 off = MIPS_CPU_IRQ_BASE + 7; 573
480 goto handle; 574/*
481 } else if (pending & CAUSEF_IP2) { 575 * au1300_set_dbdma_gpio - assign a gpio to one of the DBDMA triggers.
482 s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ0INT; 576 * @dchan: dbdma trigger select (0, 1).
483 off = AU1000_INTC0_INT_BASE; 577 * @gpio: pin to assign as trigger.
484 } else if (pending & CAUSEF_IP3) { 578 *
485 s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ1INT; 579 * DBDMA controller has 2 external trigger sources; this function
486 off = AU1000_INTC0_INT_BASE; 580 * assigns a GPIO to the selected trigger.
487 } else if (pending & CAUSEF_IP4) { 581 */
488 s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ0INT; 582void au1300_set_dbdma_gpio(int dchan, unsigned int gpio)
489 off = AU1000_INTC1_INT_BASE; 583{
490 } else if (pending & CAUSEF_IP5) { 584 unsigned long r;
491 s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ1INT; 585
492 off = AU1000_INTC1_INT_BASE; 586 if ((dchan >= 0) && (dchan <= 1)) {
493 } else 587 r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
494 goto spurious; 588 r &= ~(0xff << (8 * dchan));
495 589 r |= (gpio & 0x7f) << (8 * dchan);
496 s = __raw_readl((void __iomem *)s); 590 __raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
497 if (unlikely(!s)) { 591 wmb();
498spurious:
499 spurious_interrupt();
500 return;
501 } 592 }
502 off += __ffs(s);
503handle:
504 do_IRQ(off);
505} 593}
506 594
595static inline void gpic_pin_set_idlewake(unsigned int gpio, int allow)
596{
597 au1300_gpic_chgcfg(gpio, GPIC_CFG_IDLEWAKE,
598 allow ? GPIC_CFG_IDLEWAKE : 0);
599}
600
601static void au1300_gpic_mask(struct irq_data *d)
602{
603 void __iomem *r = AU1300_GPIC_ADDR;
604 unsigned long bit, irq = d->irq;
605
606 irq -= ALCHEMY_GPIC_INT_BASE;
607 r += GPIC_GPIO_BANKOFF(irq);
608 bit = GPIC_GPIO_TO_BIT(irq);
609 __raw_writel(bit, r + AU1300_GPIC_IDIS);
610 wmb();
611
612 gpic_pin_set_idlewake(irq, 0);
613}
614
615static void au1300_gpic_unmask(struct irq_data *d)
616{
617 void __iomem *r = AU1300_GPIC_ADDR;
618 unsigned long bit, irq = d->irq;
619
620 irq -= ALCHEMY_GPIC_INT_BASE;
621
622 gpic_pin_set_idlewake(irq, 1);
623
624 r += GPIC_GPIO_BANKOFF(irq);
625 bit = GPIC_GPIO_TO_BIT(irq);
626 __raw_writel(bit, r + AU1300_GPIC_IEN);
627 wmb();
628}
629
630static void au1300_gpic_maskack(struct irq_data *d)
631{
632 void __iomem *r = AU1300_GPIC_ADDR;
633 unsigned long bit, irq = d->irq;
634
635 irq -= ALCHEMY_GPIC_INT_BASE;
636 r += GPIC_GPIO_BANKOFF(irq);
637 bit = GPIC_GPIO_TO_BIT(irq);
638 __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */
639 __raw_writel(bit, r + AU1300_GPIC_IDIS); /* mask */
640 wmb();
641
642 gpic_pin_set_idlewake(irq, 0);
643}
644
645static void au1300_gpic_ack(struct irq_data *d)
646{
647 void __iomem *r = AU1300_GPIC_ADDR;
648 unsigned long bit, irq = d->irq;
649
650 irq -= ALCHEMY_GPIC_INT_BASE;
651 r += GPIC_GPIO_BANKOFF(irq);
652 bit = GPIC_GPIO_TO_BIT(irq);
653 __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */
654 wmb();
655}
656
657static struct irq_chip au1300_gpic = {
658 .name = "GPIOINT",
659 .irq_ack = au1300_gpic_ack,
660 .irq_mask = au1300_gpic_mask,
661 .irq_mask_ack = au1300_gpic_maskack,
662 .irq_unmask = au1300_gpic_unmask,
663 .irq_set_type = au1300_gpic_settype,
664};
665
666static int au1300_gpic_settype(struct irq_data *d, unsigned int type)
667{
668 unsigned long s;
669 unsigned char *name = NULL;
670 irq_flow_handler_t hdl = NULL;
671
672 switch (type) {
673 case IRQ_TYPE_LEVEL_HIGH:
674 s = GPIC_CFG_IC_LEVEL_HIGH;
675 name = "high";
676 hdl = handle_level_irq;
677 break;
678 case IRQ_TYPE_LEVEL_LOW:
679 s = GPIC_CFG_IC_LEVEL_LOW;
680 name = "low";
681 hdl = handle_level_irq;
682 break;
683 case IRQ_TYPE_EDGE_RISING:
684 s = GPIC_CFG_IC_EDGE_RISE;
685 name = "posedge";
686 hdl = handle_edge_irq;
687 break;
688 case IRQ_TYPE_EDGE_FALLING:
689 s = GPIC_CFG_IC_EDGE_FALL;
690 name = "negedge";
691 hdl = handle_edge_irq;
692 break;
693 case IRQ_TYPE_EDGE_BOTH:
694 s = GPIC_CFG_IC_EDGE_BOTH;
695 name = "bothedge";
696 hdl = handle_edge_irq;
697 break;
698 case IRQ_TYPE_NONE:
699 s = GPIC_CFG_IC_OFF;
700 name = "disabled";
701 hdl = handle_level_irq;
702 break;
703 default:
704 return -EINVAL;
705 }
706
707 __irq_set_chip_handler_name_locked(d->irq, &au1300_gpic, hdl, name);
708
709 au1300_gpic_chgcfg(d->irq - ALCHEMY_GPIC_INT_BASE, GPIC_CFG_IC_MASK, s);
710
711 return 0;
712}
713
714/******************************************************************************/
507 715
508static inline void ic_init(void __iomem *base) 716static inline void ic_init(void __iomem *base)
509{ 717{
@@ -521,13 +729,159 @@ static inline void ic_init(void __iomem *base)
521 wmb(); 729 wmb();
522} 730}
523 731
524static void __init au1000_init_irq(struct au1xxx_irqmap *map) 732static unsigned long alchemy_gpic_pmdata[ALCHEMY_GPIC_INT_NUM + 6];
733
734static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d)
735{
736 d[0] = __raw_readl(base + IC_CFG0RD);
737 d[1] = __raw_readl(base + IC_CFG1RD);
738 d[2] = __raw_readl(base + IC_CFG2RD);
739 d[3] = __raw_readl(base + IC_SRCRD);
740 d[4] = __raw_readl(base + IC_ASSIGNRD);
741 d[5] = __raw_readl(base + IC_WAKERD);
742 d[6] = __raw_readl(base + IC_MASKRD);
743 ic_init(base); /* shut it up too while at it */
744}
745
746static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d)
747{
748 ic_init(base);
749
750 __raw_writel(d[0], base + IC_CFG0SET);
751 __raw_writel(d[1], base + IC_CFG1SET);
752 __raw_writel(d[2], base + IC_CFG2SET);
753 __raw_writel(d[3], base + IC_SRCSET);
754 __raw_writel(d[4], base + IC_ASSIGNSET);
755 __raw_writel(d[5], base + IC_WAKESET);
756 wmb();
757
758 __raw_writel(d[6], base + IC_MASKSET);
759 wmb();
760}
761
762static int alchemy_ic_suspend(void)
763{
764 alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
765 alchemy_gpic_pmdata);
766 alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
767 &alchemy_gpic_pmdata[7]);
768 return 0;
769}
770
771static void alchemy_ic_resume(void)
772{
773 alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
774 &alchemy_gpic_pmdata[7]);
775 alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
776 alchemy_gpic_pmdata);
777}
778
779static int alchemy_gpic_suspend(void)
780{
781 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
782 int i;
783
784 /* save 4 interrupt mask status registers */
785 alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0);
786 alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4);
787 alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8);
788 alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc);
789
790 /* save misc register(s) */
791 alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL);
792
793 /* molto silenzioso */
794 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
795 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
796 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
797 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
798 wmb();
799
800 /* save pin/int-type configuration */
801 base += AU1300_GPIC_PINCFG;
802 for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++)
803 alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2));
804
805 wmb();
806
807 return 0;
808}
809
810static void alchemy_gpic_resume(void)
811{
812 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
813 int i;
814
815 /* disable all first */
816 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
817 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
818 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
819 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
820 wmb();
821
822 /* restore pin/int-type configurations */
823 base += AU1300_GPIC_PINCFG;
824 for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++)
825 __raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2));
826 wmb();
827
828 /* restore misc register(s) */
829 base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
830 __raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL);
831 wmb();
832
833 /* finally restore masks */
834 __raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0);
835 __raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4);
836 __raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8);
837 __raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc);
838 wmb();
839}
840
841static struct syscore_ops alchemy_ic_pmops = {
842 .suspend = alchemy_ic_suspend,
843 .resume = alchemy_ic_resume,
844};
845
846static struct syscore_ops alchemy_gpic_pmops = {
847 .suspend = alchemy_gpic_suspend,
848 .resume = alchemy_gpic_resume,
849};
850
851/******************************************************************************/
852
853/* create chained handlers for the 4 IC requests to the MIPS IRQ ctrl */
854#define DISP(name, base, addr) \
855static void au1000_##name##_dispatch(unsigned int irq, struct irq_desc *d) \
856{ \
857 unsigned long r = __raw_readl((void __iomem *)KSEG1ADDR(addr)); \
858 if (likely(r)) \
859 generic_handle_irq(base + __ffs(r)); \
860 else \
861 spurious_interrupt(); \
862}
863
864DISP(ic0r0, AU1000_INTC0_INT_BASE, AU1000_IC0_PHYS_ADDR + IC_REQ0INT)
865DISP(ic0r1, AU1000_INTC0_INT_BASE, AU1000_IC0_PHYS_ADDR + IC_REQ1INT)
866DISP(ic1r0, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ0INT)
867DISP(ic1r1, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ1INT)
868
869static void alchemy_gpic_dispatch(unsigned int irq, struct irq_desc *d)
870{
871 int i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC);
872 generic_handle_irq(ALCHEMY_GPIC_INT_BASE + i);
873}
874
875/******************************************************************************/
876
877static void __init au1000_init_irq(struct alchemy_irqmap *map)
525{ 878{
526 unsigned int bit, irq_nr; 879 unsigned int bit, irq_nr;
527 void __iomem *base; 880 void __iomem *base;
528 881
529 ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR)); 882 ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR));
530 ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR)); 883 ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR));
884 register_syscore_ops(&alchemy_ic_pmops);
531 mips_cpu_irq_init(); 885 mips_cpu_irq_init();
532 886
533 /* register all 64 possible IC0+IC1 irq sources as type "none". 887 /* register all 64 possible IC0+IC1 irq sources as type "none".
@@ -544,8 +898,8 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map)
544 /* 898 /*
545 * Initialize IC0, which is fixed per processor. 899 * Initialize IC0, which is fixed per processor.
546 */ 900 */
547 while (map->im_irq != -1) { 901 while (map->irq != -1) {
548 irq_nr = map->im_irq; 902 irq_nr = map->irq;
549 903
550 if (irq_nr >= AU1000_INTC1_INT_BASE) { 904 if (irq_nr >= AU1000_INTC1_INT_BASE) {
551 bit = irq_nr - AU1000_INTC1_INT_BASE; 905 bit = irq_nr - AU1000_INTC1_INT_BASE;
@@ -554,16 +908,61 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map)
554 bit = irq_nr - AU1000_INTC0_INT_BASE; 908 bit = irq_nr - AU1000_INTC0_INT_BASE;
555 base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); 909 base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
556 } 910 }
557 if (map->im_request) 911 if (map->prio == 0)
558 __raw_writel(1 << bit, base + IC_ASSIGNSET); 912 __raw_writel(1 << bit, base + IC_ASSIGNSET);
559 913
560 au1x_ic_settype(irq_get_irq_data(irq_nr), map->im_type); 914 au1x_ic_settype(irq_get_irq_data(irq_nr), map->type);
561 ++map; 915 ++map;
562 } 916 }
563 917
564 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); 918 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, au1000_ic0r0_dispatch);
919 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, au1000_ic0r1_dispatch);
920 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, au1000_ic1r0_dispatch);
921 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, au1000_ic1r1_dispatch);
922}
923
924static void __init alchemy_gpic_init_irq(const struct alchemy_irqmap *dints)
925{
926 int i;
927 void __iomem *bank_base;
928
929 register_syscore_ops(&alchemy_gpic_pmops);
930 mips_cpu_irq_init();
931
932 /* disable & ack all possible interrupt sources */
933 for (i = 0; i < 4; i++) {
934 bank_base = AU1300_GPIC_ADDR + (i * 4);
935 __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS);
936 wmb();
937 __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND);
938 wmb();
939 }
940
941 /* register an irq_chip for them, with 2nd highest priority */
942 for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) {
943 au1300_set_irq_priority(i, 1);
944 au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);
945 }
946
947 /* setup known on-chip sources */
948 while ((i = dints->irq) != -1) {
949 au1300_gpic_settype(irq_get_irq_data(i), dints->type);
950 au1300_set_irq_priority(i, dints->prio);
951
952 if (dints->internal)
953 au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE);
954
955 dints++;
956 }
957
958 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, alchemy_gpic_dispatch);
959 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, alchemy_gpic_dispatch);
960 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, alchemy_gpic_dispatch);
961 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, alchemy_gpic_dispatch);
565} 962}
566 963
964/******************************************************************************/
965
567void __init arch_init_irq(void) 966void __init arch_init_irq(void)
568{ 967{
569 switch (alchemy_get_cputype()) { 968 switch (alchemy_get_cputype()) {
@@ -582,65 +981,17 @@ void __init arch_init_irq(void)
582 case ALCHEMY_CPU_AU1200: 981 case ALCHEMY_CPU_AU1200:
583 au1000_init_irq(au1200_irqmap); 982 au1000_init_irq(au1200_irqmap);
584 break; 983 break;
984 case ALCHEMY_CPU_AU1300:
985 alchemy_gpic_init_irq(au1300_irqmap);
986 break;
987 default:
988 pr_err("unknown Alchemy IRQ core\n");
989 break;
585 } 990 }
586} 991}
587 992
588 993asmlinkage void plat_irq_dispatch(void)
589static unsigned long alchemy_ic_pmdata[7 * 2];
590
591static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d)
592{
593 d[0] = __raw_readl(base + IC_CFG0RD);
594 d[1] = __raw_readl(base + IC_CFG1RD);
595 d[2] = __raw_readl(base + IC_CFG2RD);
596 d[3] = __raw_readl(base + IC_SRCRD);
597 d[4] = __raw_readl(base + IC_ASSIGNRD);
598 d[5] = __raw_readl(base + IC_WAKERD);
599 d[6] = __raw_readl(base + IC_MASKRD);
600 ic_init(base); /* shut it up too while at it */
601}
602
603static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d)
604{
605 ic_init(base);
606
607 __raw_writel(d[0], base + IC_CFG0SET);
608 __raw_writel(d[1], base + IC_CFG1SET);
609 __raw_writel(d[2], base + IC_CFG2SET);
610 __raw_writel(d[3], base + IC_SRCSET);
611 __raw_writel(d[4], base + IC_ASSIGNSET);
612 __raw_writel(d[5], base + IC_WAKESET);
613 wmb();
614
615 __raw_writel(d[6], base + IC_MASKSET);
616 wmb();
617}
618
619static int alchemy_ic_suspend(void)
620{
621 alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
622 alchemy_ic_pmdata);
623 alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
624 &alchemy_ic_pmdata[7]);
625 return 0;
626}
627
628static void alchemy_ic_resume(void)
629{
630 alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
631 &alchemy_ic_pmdata[7]);
632 alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
633 alchemy_ic_pmdata);
634}
635
636static struct syscore_ops alchemy_ic_syscore_ops = {
637 .suspend = alchemy_ic_suspend,
638 .resume = alchemy_ic_resume,
639};
640
641static int __init alchemy_ic_pm_init(void)
642{ 994{
643 register_syscore_ops(&alchemy_ic_syscore_ops); 995 unsigned long r = (read_c0_status() & read_c0_cause()) >> 8;
644 return 0; 996 do_IRQ(MIPS_CPU_IRQ_BASE + __ffs(r & 0xff));
645} 997}
646device_initcall(alchemy_ic_pm_init);
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index c8e5d72a5826..95cb9113b12c 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -82,6 +82,12 @@ static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = {
82 PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT), 82 PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),
83 PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT), 83 PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),
84 }, 84 },
85 [ALCHEMY_CPU_AU1300] = {
86 PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT),
87 PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT),
88 PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT),
89 PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT),
90 },
85}; 91};
86 92
87static struct platform_device au1xx0_uart_device = { 93static struct platform_device au1xx0_uart_device = {
@@ -122,10 +128,12 @@ static unsigned long alchemy_ohci_data[][2] __initdata = {
122 [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT }, 128 [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT },
123 [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT }, 129 [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT },
124 [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT }, 130 [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT },
131 [ALCHEMY_CPU_AU1300] = { AU1300_USB_OHCI0_PHYS_ADDR, AU1300_USB_INT },
125}; 132};
126 133
127static unsigned long alchemy_ehci_data[][2] __initdata = { 134static unsigned long alchemy_ehci_data[][2] __initdata = {
128 [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT }, 135 [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT },
136 [ALCHEMY_CPU_AU1300] = { AU1300_USB_EHCI_PHYS_ADDR, AU1300_USB_INT },
129}; 137};
130 138
131static int __init _new_usbres(struct resource **r, struct platform_device **d) 139static int __init _new_usbres(struct resource **r, struct platform_device **d)
@@ -169,8 +177,8 @@ static void __init alchemy_setup_usb(int ctype)
169 printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n"); 177 printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n");
170 178
171 179
172 /* setup EHCI0: Au1200 */ 180 /* setup EHCI0: Au1200/Au1300 */
173 if (ctype == ALCHEMY_CPU_AU1200) { 181 if ((ctype == ALCHEMY_CPU_AU1200) || (ctype == ALCHEMY_CPU_AU1300)) {
174 if (_new_usbres(&res, &pdev)) 182 if (_new_usbres(&res, &pdev))
175 return; 183 return;
176 184
@@ -187,6 +195,25 @@ static void __init alchemy_setup_usb(int ctype)
187 if (platform_device_register(pdev)) 195 if (platform_device_register(pdev))
188 printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n"); 196 printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n");
189 } 197 }
198
199 /* Au1300: OHCI1 */
200 if (ctype == ALCHEMY_CPU_AU1300) {
201 if (_new_usbres(&res, &pdev))
202 return;
203
204 res[0].start = AU1300_USB_OHCI1_PHYS_ADDR;
205 res[0].end = res[0].start + 0x100 - 1;
206 res[0].flags = IORESOURCE_MEM;
207 res[1].start = AU1300_USB_INT;
208 res[1].end = res[1].start;
209 res[1].flags = IORESOURCE_IRQ;
210 pdev->name = "au1xxx-ohci";
211 pdev->id = 1;
212 pdev->dev.dma_mask = &alchemy_ohci_dmamask;
213
214 if (platform_device_register(pdev))
215 printk(KERN_INFO "Alchemy USB: cannot add OHCI1\n");
216 }
190} 217}
191 218
192/* Macro to help defining the Ethernet MAC resources */ 219/* Macro to help defining the Ethernet MAC resources */
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index bdd6651e9a4f..0c7fce2a3c12 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -126,6 +126,9 @@ void au_sleep(void)
126 case ALCHEMY_CPU_AU1200: 126 case ALCHEMY_CPU_AU1200:
127 alchemy_sleep_au1550(); 127 alchemy_sleep_au1550();
128 break; 128 break;
129 case ALCHEMY_CPU_AU1300:
130 alchemy_sleep_au1300();
131 break;
129 } 132 }
130 133
131 restore_core_regs(); 134 restore_core_regs();
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 77f3c743b716..c7bcc7e5c822 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -153,6 +153,79 @@ LEAF(alchemy_sleep_au1550)
153 153
154END(alchemy_sleep_au1550) 154END(alchemy_sleep_au1550)
155 155
156/* sleepcode for Au1300 memory controller type */
157LEAF(alchemy_sleep_au1300)
158
159 SETUP_SLEEP
160
161 /* cache following instructions, as memory gets put to sleep */
162 la t0, 2f
163 la t1, 4f
164 subu t2, t1, t0
165
166 .set mips3
167
1681: cache 0x14, 0(t0)
169 subu t2, t2, 32
170 bgez t2, 1b
171 addu t0, t0, 32
172
173 .set mips0
174
1752: lui a0, 0xb400 /* mem_xxx */
176
177 /* disable all ports in mem_sdportcfga */
178 sw zero, 0x868(a0) /* mem_sdportcfga */
179 sync
180
181 /* disable ODT */
182 li t0, 0x03010000
183 sw t0, 0x08d8(a0) /* mem_sdcmd0 */
184 sw t0, 0x08dc(a0) /* mem_sdcmd1 */
185 sync
186
187 /* precharge */
188 li t0, 0x23000400
189 sw t0, 0x08dc(a0) /* mem_sdcmd1 */
190 sw t0, 0x08d8(a0) /* mem_sdcmd0 */
191 sync
192
193 /* auto refresh */
194 sw zero, 0x08c8(a0) /* mem_sdautoref */
195 sync
196
197 /* block access to the DDR */
198 lw t0, 0x0848(a0) /* mem_sdconfigb */
199 li t1, (1 << 7 | 0x3F)
200 or t0, t0, t1
201 sw t0, 0x0848(a0) /* mem_sdconfigb */
202 sync
203
204 /* issue the Self Refresh command */
205 li t0, 0x10000000
206 sw t0, 0x08dc(a0) /* mem_sdcmd1 */
207 sw t0, 0x08d8(a0) /* mem_sdcmd0 */
208 sync
209
210 /* wait for sdram to enter self-refresh mode */
211 lui t0, 0x0300
2123: lw t1, 0x0850(a0) /* mem_sdstat */
213 and t2, t1, t0
214 bne t2, t0, 3b
215 nop
216
217 /* disable SDRAM clocks */
218 li t0, ~(3<<28)
219 lw t1, 0x0840(a0) /* mem_sdconfiga */
220 and t1, t1, t0 /* clear CE[1:0] */
221 sw t1, 0x0840(a0) /* mem_sdconfiga */
222 sync
223
224 DO_SLEEP
2254:
226
227END(alchemy_sleep_au1300)
228
156 229
157 /* This is where we return upon wakeup. 230 /* This is where we return upon wakeup.
158 * Reload all of the registers and return. 231 * Reload all of the registers and return.
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 146a5fa80360..7da4d0081487 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -178,6 +178,7 @@ static int alchemy_m2inttab[] __initdata = {
178 AU1100_RTC_MATCH2_INT, 178 AU1100_RTC_MATCH2_INT,
179 AU1550_RTC_MATCH2_INT, 179 AU1550_RTC_MATCH2_INT,
180 AU1200_RTC_MATCH2_INT, 180 AU1200_RTC_MATCH2_INT,
181 AU1300_RTC_MATCH2_INT,
181}; 182};
182 183
183void __init plat_time_init(void) 184void __init plat_time_init(void)
diff --git a/arch/mips/alchemy/common/vss.c b/arch/mips/alchemy/common/vss.c
new file mode 100644
index 000000000000..d23b1444d365
--- /dev/null
+++ b/arch/mips/alchemy/common/vss.c
@@ -0,0 +1,84 @@
1/*
2 * Au1300 media block power gating (VSS)
3 *
4 * This is a stop-gap solution until I have the clock framework integration
5 * ready. This stuff here really must be handled transparently when clocks
6 * for various media blocks are enabled/disabled.
7 */
8
9#include <linux/module.h>
10#include <linux/spinlock.h>
11#include <asm/mach-au1x00/au1000.h>
12
13#define VSS_GATE 0x00 /* gate wait timers */
14#define VSS_CLKRST 0x04 /* clock/block control */
15#define VSS_FTR 0x08 /* footers */
16
17#define VSS_ADDR(blk) (KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c))
18
19static DEFINE_SPINLOCK(au1300_vss_lock);
20
21/* enable a block as outlined in the databook */
22static inline void __enable_block(int block)
23{
24 void __iomem *base = (void __iomem *)VSS_ADDR(block);
25
26 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */
27 wmb();
28
29 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */
30 wmb();
31
32 /* enable footers in sequence */
33 __raw_writel(0x01, base + VSS_FTR);
34 wmb();
35 __raw_writel(0x03, base + VSS_FTR);
36 wmb();
37 __raw_writel(0x07, base + VSS_FTR);
38 wmb();
39 __raw_writel(0x0f, base + VSS_FTR);
40 wmb();
41
42 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */
43 wmb();
44
45 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */
46 wmb();
47
48 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */
49 wmb();
50}
51
52/* disable a block as outlined in the databook */
53static inline void __disable_block(int block)
54{
55 void __iomem *base = (void __iomem *)VSS_ADDR(block);
56
57 __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */
58 wmb();
59 __raw_writel(0, base + VSS_GATE); /* disable FSM */
60 wmb();
61 __raw_writel(3, base + VSS_CLKRST); /* assert reset */
62 wmb();
63 __raw_writel(1, base + VSS_CLKRST); /* disable clock */
64 wmb();
65 __raw_writel(0, base + VSS_FTR); /* disable all footers */
66 wmb();
67}
68
69void au1300_vss_block_control(int block, int enable)
70{
71 unsigned long flags;
72
73 if (alchemy_get_cputype() != ALCHEMY_CPU_AU1300)
74 return;
75
76 /* only one block at a time */
77 spin_lock_irqsave(&au1300_vss_lock, flags);
78 if (enable)
79 __enable_block(block);
80 else
81 __disable_block(block);
82 spin_unlock_irqrestore(&au1300_vss_lock, flags);
83}
84EXPORT_SYMBOL_GPL(au1300_vss_block_control);
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index 826449c817c3..3c37fb303364 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -4,15 +4,10 @@
4 4
5obj-y += prom.o bcsr.o platform.o 5obj-y += prom.o bcsr.o platform.o
6obj-$(CONFIG_PM) += pm.o 6obj-$(CONFIG_PM) += pm.o
7obj-$(CONFIG_MIPS_PB1000) += pb1000/ 7obj-$(CONFIG_MIPS_PB1100) += pb1100.o
8obj-$(CONFIG_MIPS_PB1100) += pb1100/ 8obj-$(CONFIG_MIPS_PB1500) += pb1500.o
9obj-$(CONFIG_MIPS_PB1200) += pb1200/ 9obj-$(CONFIG_MIPS_PB1550) += pb1550.o
10obj-$(CONFIG_MIPS_PB1500) += pb1500/ 10obj-$(CONFIG_MIPS_DB1000) += db1000.o
11obj-$(CONFIG_MIPS_PB1550) += pb1550/ 11obj-$(CONFIG_MIPS_DB1200) += db1200.o
12obj-$(CONFIG_MIPS_DB1000) += db1x00/ 12obj-$(CONFIG_MIPS_DB1300) += db1300.o
13obj-$(CONFIG_MIPS_DB1100) += db1x00/ 13obj-$(CONFIG_MIPS_DB1550) += db1550.o
14obj-$(CONFIG_MIPS_DB1200) += db1200/
15obj-$(CONFIG_MIPS_DB1500) += db1x00/
16obj-$(CONFIG_MIPS_DB1550) += db1x00/
17obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/
18obj-$(CONFIG_MIPS_MIRAGE) += db1x00/
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index 463d2c4d9441..1e83ce2e1147 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -97,14 +97,9 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
97 enable_irq(irq); 97 enable_irq(irq);
98} 98}
99 99
100/* NOTE: both the enable and mask bits must be cleared, otherwise the
101 * CPLD generates tons of spurious interrupts (at least on my DB1200).
102 * -- mlau
103 */
104static void bcsr_irq_mask(struct irq_data *d) 100static void bcsr_irq_mask(struct irq_data *d)
105{ 101{
106 unsigned short v = 1 << (d->irq - bcsr_csc_base); 102 unsigned short v = 1 << (d->irq - bcsr_csc_base);
107 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
108 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); 103 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
109 wmb(); 104 wmb();
110} 105}
@@ -112,7 +107,6 @@ static void bcsr_irq_mask(struct irq_data *d)
112static void bcsr_irq_maskack(struct irq_data *d) 107static void bcsr_irq_maskack(struct irq_data *d)
113{ 108{
114 unsigned short v = 1 << (d->irq - bcsr_csc_base); 109 unsigned short v = 1 << (d->irq - bcsr_csc_base);
115 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
116 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); 110 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
117 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ 111 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
118 wmb(); 112 wmb();
@@ -121,7 +115,6 @@ static void bcsr_irq_maskack(struct irq_data *d)
121static void bcsr_irq_unmask(struct irq_data *d) 115static void bcsr_irq_unmask(struct irq_data *d)
122{ 116{
123 unsigned short v = 1 << (d->irq - bcsr_csc_base); 117 unsigned short v = 1 << (d->irq - bcsr_csc_base);
124 __raw_writew(v, bcsr_virt + BCSR_REG_INTSET);
125 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); 118 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
126 wmb(); 119 wmb();
127} 120}
@@ -137,9 +130,9 @@ void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
137{ 130{
138 unsigned int irq; 131 unsigned int irq;
139 132
140 /* mask & disable & ack all */ 133 /* mask & enable & ack all */
141 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTCLR);
142 __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR); 134 __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR);
135 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET);
143 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT); 136 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT);
144 wmb(); 137 wmb();
145 138
diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c
new file mode 100644
index 000000000000..1b81dbf6b804
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1000.c
@@ -0,0 +1,565 @@
1/*
2 * DBAu1000/1500/1100 board support
3 *
4 * Copyright 2000, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <linux/dma-mapping.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/leds.h>
27#include <linux/mmc/host.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
30#include <linux/pm.h>
31#include <linux/spi/spi.h>
32#include <linux/spi/spi_gpio.h>
33#include <linux/spi/ads7846.h>
34#include <asm/mach-au1x00/au1000.h>
35#include <asm/mach-au1x00/au1000_dma.h>
36#include <asm/mach-au1x00/au1100_mmc.h>
37#include <asm/mach-db1x00/bcsr.h>
38#include <asm/reboot.h>
39#include <prom.h>
40#include "platform.h"
41
42#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
43
44struct pci_dev;
45
46static const char *board_type_str(void)
47{
48 switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
49 case BCSR_WHOAMI_DB1000:
50 return "DB1000";
51 case BCSR_WHOAMI_DB1500:
52 return "DB1500";
53 case BCSR_WHOAMI_DB1100:
54 return "DB1100";
55 default:
56 return "(unknown)";
57 }
58}
59
60const char *get_system_type(void)
61{
62 return board_type_str();
63}
64
65void __init board_setup(void)
66{
67 /* initialize board register space */
68 bcsr_init(DB1000_BCSR_PHYS_ADDR,
69 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
70
71 printk(KERN_INFO "AMD Alchemy %s Board\n", board_type_str());
72}
73
74
75static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
76{
77 if ((slot < 12) || (slot > 13) || pin == 0)
78 return -1;
79 if (slot == 12)
80 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
81 if (slot == 13) {
82 switch (pin) {
83 case 1: return AU1500_PCI_INTA;
84 case 2: return AU1500_PCI_INTB;
85 case 3: return AU1500_PCI_INTC;
86 case 4: return AU1500_PCI_INTD;
87 }
88 }
89 return -1;
90}
91
92static struct resource alchemy_pci_host_res[] = {
93 [0] = {
94 .start = AU1500_PCI_PHYS_ADDR,
95 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
96 .flags = IORESOURCE_MEM,
97 },
98};
99
100static struct alchemy_pci_platdata db1500_pci_pd = {
101 .board_map_irq = db1500_map_pci_irq,
102};
103
104static struct platform_device db1500_pci_host_dev = {
105 .dev.platform_data = &db1500_pci_pd,
106 .name = "alchemy-pci",
107 .id = 0,
108 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
109 .resource = alchemy_pci_host_res,
110};
111
112static int __init db1500_pci_init(void)
113{
114 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1500)
115 return platform_device_register(&db1500_pci_host_dev);
116 return 0;
117}
118/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
119arch_initcall(db1500_pci_init);
120
121
122static struct resource au1100_lcd_resources[] = {
123 [0] = {
124 .start = AU1100_LCD_PHYS_ADDR,
125 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
126 .flags = IORESOURCE_MEM,
127 },
128 [1] = {
129 .start = AU1100_LCD_INT,
130 .end = AU1100_LCD_INT,
131 .flags = IORESOURCE_IRQ,
132 }
133};
134
135static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
136
137static struct platform_device au1100_lcd_device = {
138 .name = "au1100-lcd",
139 .id = 0,
140 .dev = {
141 .dma_mask = &au1100_lcd_dmamask,
142 .coherent_dma_mask = DMA_BIT_MASK(32),
143 },
144 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
145 .resource = au1100_lcd_resources,
146};
147
148static struct resource alchemy_ac97c_res[] = {
149 [0] = {
150 .start = AU1000_AC97_PHYS_ADDR,
151 .end = AU1000_AC97_PHYS_ADDR + 0xfff,
152 .flags = IORESOURCE_MEM,
153 },
154 [1] = {
155 .start = DMA_ID_AC97C_TX,
156 .end = DMA_ID_AC97C_TX,
157 .flags = IORESOURCE_DMA,
158 },
159 [2] = {
160 .start = DMA_ID_AC97C_RX,
161 .end = DMA_ID_AC97C_RX,
162 .flags = IORESOURCE_DMA,
163 },
164};
165
166static struct platform_device alchemy_ac97c_dev = {
167 .name = "alchemy-ac97c",
168 .id = -1,
169 .resource = alchemy_ac97c_res,
170 .num_resources = ARRAY_SIZE(alchemy_ac97c_res),
171};
172
173static struct platform_device alchemy_ac97c_dma_dev = {
174 .name = "alchemy-pcm-dma",
175 .id = 0,
176};
177
178static struct platform_device db1x00_codec_dev = {
179 .name = "ac97-codec",
180 .id = -1,
181};
182
183static struct platform_device db1x00_audio_dev = {
184 .name = "db1000-audio",
185};
186
187/******************************************************************************/
188
189static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
190{
191 void (*mmc_cd)(struct mmc_host *, unsigned long);
192 /* link against CONFIG_MMC=m */
193 mmc_cd = symbol_get(mmc_detect_change);
194 mmc_cd(ptr, msecs_to_jiffies(500));
195 symbol_put(mmc_detect_change);
196
197 return IRQ_HANDLED;
198}
199
200static int db1100_mmc_cd_setup(void *mmc_host, int en)
201{
202 int ret = 0;
203
204 if (en) {
205 irq_set_irq_type(AU1100_GPIO19_INT, IRQ_TYPE_EDGE_BOTH);
206 ret = request_irq(AU1100_GPIO19_INT, db1100_mmc_cd, 0,
207 "sd0_cd", mmc_host);
208 } else
209 free_irq(AU1100_GPIO19_INT, mmc_host);
210 return ret;
211}
212
213static int db1100_mmc1_cd_setup(void *mmc_host, int en)
214{
215 int ret = 0;
216
217 if (en) {
218 irq_set_irq_type(AU1100_GPIO20_INT, IRQ_TYPE_EDGE_BOTH);
219 ret = request_irq(AU1100_GPIO20_INT, db1100_mmc_cd, 0,
220 "sd1_cd", mmc_host);
221 } else
222 free_irq(AU1100_GPIO20_INT, mmc_host);
223 return ret;
224}
225
226static int db1100_mmc_card_readonly(void *mmc_host)
227{
228 /* testing suggests that this bit is inverted */
229 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1;
230}
231
232static int db1100_mmc_card_inserted(void *mmc_host)
233{
234 return !alchemy_gpio_get_value(19);
235}
236
237static void db1100_mmc_set_power(void *mmc_host, int state)
238{
239 if (state) {
240 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
241 msleep(400); /* stabilization time */
242 } else
243 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
244}
245
246static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b)
247{
248 if (b != LED_OFF)
249 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
250 else
251 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
252}
253
254static struct led_classdev db1100_mmc_led = {
255 .brightness_set = db1100_mmcled_set,
256};
257
258static int db1100_mmc1_card_readonly(void *mmc_host)
259{
260 return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0;
261}
262
263static int db1100_mmc1_card_inserted(void *mmc_host)
264{
265 return !alchemy_gpio_get_value(20);
266}
267
268static void db1100_mmc1_set_power(void *mmc_host, int state)
269{
270 if (state) {
271 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
272 msleep(400); /* stabilization time */
273 } else
274 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
275}
276
277static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b)
278{
279 if (b != LED_OFF)
280 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
281 else
282 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
283}
284
285static struct led_classdev db1100_mmc1_led = {
286 .brightness_set = db1100_mmc1led_set,
287};
288
289static struct au1xmmc_platform_data db1100_mmc_platdata[2] = {
290 [0] = {
291 .cd_setup = db1100_mmc_cd_setup,
292 .set_power = db1100_mmc_set_power,
293 .card_inserted = db1100_mmc_card_inserted,
294 .card_readonly = db1100_mmc_card_readonly,
295 .led = &db1100_mmc_led,
296 },
297 [1] = {
298 .cd_setup = db1100_mmc1_cd_setup,
299 .set_power = db1100_mmc1_set_power,
300 .card_inserted = db1100_mmc1_card_inserted,
301 .card_readonly = db1100_mmc1_card_readonly,
302 .led = &db1100_mmc1_led,
303 },
304};
305
306static struct resource au1100_mmc0_resources[] = {
307 [0] = {
308 .start = AU1100_SD0_PHYS_ADDR,
309 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
310 .flags = IORESOURCE_MEM,
311 },
312 [1] = {
313 .start = AU1100_SD_INT,
314 .end = AU1100_SD_INT,
315 .flags = IORESOURCE_IRQ,
316 },
317 [2] = {
318 .start = DMA_ID_SD0_TX,
319 .end = DMA_ID_SD0_TX,
320 .flags = IORESOURCE_DMA,
321 },
322 [3] = {
323 .start = DMA_ID_SD0_RX,
324 .end = DMA_ID_SD0_RX,
325 .flags = IORESOURCE_DMA,
326 }
327};
328
329static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
330
331static struct platform_device db1100_mmc0_dev = {
332 .name = "au1xxx-mmc",
333 .id = 0,
334 .dev = {
335 .dma_mask = &au1xxx_mmc_dmamask,
336 .coherent_dma_mask = DMA_BIT_MASK(32),
337 .platform_data = &db1100_mmc_platdata[0],
338 },
339 .num_resources = ARRAY_SIZE(au1100_mmc0_resources),
340 .resource = au1100_mmc0_resources,
341};
342
343static struct resource au1100_mmc1_res[] = {
344 [0] = {
345 .start = AU1100_SD1_PHYS_ADDR,
346 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
347 .flags = IORESOURCE_MEM,
348 },
349 [1] = {
350 .start = AU1100_SD_INT,
351 .end = AU1100_SD_INT,
352 .flags = IORESOURCE_IRQ,
353 },
354 [2] = {
355 .start = DMA_ID_SD1_TX,
356 .end = DMA_ID_SD1_TX,
357 .flags = IORESOURCE_DMA,
358 },
359 [3] = {
360 .start = DMA_ID_SD1_RX,
361 .end = DMA_ID_SD1_RX,
362 .flags = IORESOURCE_DMA,
363 }
364};
365
366static struct platform_device db1100_mmc1_dev = {
367 .name = "au1xxx-mmc",
368 .id = 1,
369 .dev = {
370 .dma_mask = &au1xxx_mmc_dmamask,
371 .coherent_dma_mask = DMA_BIT_MASK(32),
372 .platform_data = &db1100_mmc_platdata[1],
373 },
374 .num_resources = ARRAY_SIZE(au1100_mmc1_res),
375 .resource = au1100_mmc1_res,
376};
377
378/******************************************************************************/
379
380static void db1000_irda_set_phy_mode(int mode)
381{
382 unsigned short mask = BCSR_RESETS_IRDA_MODE_MASK | BCSR_RESETS_FIR_SEL;
383
384 switch (mode) {
385 case AU1000_IRDA_PHY_MODE_OFF:
386 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_OFF);
387 break;
388 case AU1000_IRDA_PHY_MODE_SIR:
389 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL);
390 break;
391 case AU1000_IRDA_PHY_MODE_FIR:
392 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL |
393 BCSR_RESETS_FIR_SEL);
394 break;
395 }
396}
397
398static struct au1k_irda_platform_data db1000_irda_platdata = {
399 .set_phy_mode = db1000_irda_set_phy_mode,
400};
401
402static struct resource au1000_irda_res[] = {
403 [0] = {
404 .start = AU1000_IRDA_PHYS_ADDR,
405 .end = AU1000_IRDA_PHYS_ADDR + 0x0fff,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = AU1000_IRDA_TX_INT,
410 .end = AU1000_IRDA_TX_INT,
411 .flags = IORESOURCE_IRQ,
412 },
413 [2] = {
414 .start = AU1000_IRDA_RX_INT,
415 .end = AU1000_IRDA_RX_INT,
416 .flags = IORESOURCE_IRQ,
417 },
418};
419
420static struct platform_device db1000_irda_dev = {
421 .name = "au1000-irda",
422 .id = -1,
423 .dev = {
424 .platform_data = &db1000_irda_platdata,
425 },
426 .resource = au1000_irda_res,
427 .num_resources = ARRAY_SIZE(au1000_irda_res),
428};
429
430/******************************************************************************/
431
432static struct ads7846_platform_data db1100_touch_pd = {
433 .model = 7846,
434 .vref_mv = 3300,
435 .gpio_pendown = 21,
436};
437
438static struct spi_gpio_platform_data db1100_spictl_pd = {
439 .sck = 209,
440 .mosi = 208,
441 .miso = 207,
442 .num_chipselect = 1,
443};
444
445static struct spi_board_info db1100_spi_info[] __initdata = {
446 [0] = {
447 .modalias = "ads7846",
448 .max_speed_hz = 3250000,
449 .bus_num = 0,
450 .chip_select = 0,
451 .mode = 0,
452 .irq = AU1100_GPIO21_INT,
453 .platform_data = &db1100_touch_pd,
454 .controller_data = (void *)210, /* for spi_gpio: CS# GPIO210 */
455 },
456};
457
458static struct platform_device db1100_spi_dev = {
459 .name = "spi_gpio",
460 .id = 0,
461 .dev = {
462 .platform_data = &db1100_spictl_pd,
463 },
464};
465
466
467static struct platform_device *db1x00_devs[] = {
468 &db1x00_codec_dev,
469 &alchemy_ac97c_dma_dev,
470 &alchemy_ac97c_dev,
471 &db1x00_audio_dev,
472};
473
474static struct platform_device *db1000_devs[] = {
475 &db1000_irda_dev,
476};
477
478static struct platform_device *db1100_devs[] = {
479 &au1100_lcd_device,
480 &db1100_mmc0_dev,
481 &db1100_mmc1_dev,
482 &db1000_irda_dev,
483 &db1100_spi_dev,
484};
485
486static int __init db1000_dev_init(void)
487{
488 int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
489 int c0, c1, d0, d1, s0, s1;
490 unsigned long pfc;
491
492 if (board == BCSR_WHOAMI_DB1500) {
493 c0 = AU1500_GPIO2_INT;
494 c1 = AU1500_GPIO5_INT;
495 d0 = AU1500_GPIO0_INT;
496 d1 = AU1500_GPIO3_INT;
497 s0 = AU1500_GPIO1_INT;
498 s1 = AU1500_GPIO4_INT;
499 } else if (board == BCSR_WHOAMI_DB1100) {
500 c0 = AU1100_GPIO2_INT;
501 c1 = AU1100_GPIO5_INT;
502 d0 = AU1100_GPIO0_INT;
503 d1 = AU1100_GPIO3_INT;
504 s0 = AU1100_GPIO1_INT;
505 s1 = AU1100_GPIO4_INT;
506
507 gpio_direction_input(19); /* sd0 cd# */
508 gpio_direction_input(20); /* sd1 cd# */
509 gpio_direction_input(21); /* touch pendown# */
510 gpio_direction_input(207); /* SPI MISO */
511 gpio_direction_output(208, 0); /* SPI MOSI */
512 gpio_direction_output(209, 1); /* SPI SCK */
513 gpio_direction_output(210, 1); /* SPI CS# */
514
515 /* spi_gpio on SSI0 pins */
516 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
517 pfc |= (1 << 0); /* SSI0 pins as GPIOs */
518 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
519 wmb();
520
521 spi_register_board_info(db1100_spi_info,
522 ARRAY_SIZE(db1100_spi_info));
523
524 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
525 } else if (board == BCSR_WHOAMI_DB1000) {
526 c0 = AU1000_GPIO2_INT;
527 c1 = AU1000_GPIO5_INT;
528 d0 = AU1000_GPIO0_INT;
529 d1 = AU1000_GPIO3_INT;
530 s0 = AU1000_GPIO1_INT;
531 s1 = AU1000_GPIO4_INT;
532 platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs));
533 } else
534 return 0; /* unknown board, no further dev setup to do */
535
536 irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH);
537 irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH);
538 irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);
539 irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
540 irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
541 irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
542
543 db1x_register_pcmcia_socket(
544 AU1000_PCMCIA_ATTR_PHYS_ADDR,
545 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
546 AU1000_PCMCIA_MEM_PHYS_ADDR,
547 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
548 AU1000_PCMCIA_IO_PHYS_ADDR,
549 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
550 c0, d0, /*s0*/0, 0, 0);
551
552 db1x_register_pcmcia_socket(
553 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
554 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
555 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
556 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
557 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
558 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
559 c1, d1, /*s1*/0, 0, 1);
560
561 platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));
562 db1x_register_norflash(32 << 20, 4 /* 32bit */, F_SWAPPED);
563 return 0;
564}
565device_initcall(db1000_dev_init);
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200.c
index 78459c17c628..a83302b96c01 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * DBAu1200 board platform device registration 2 * DBAu1200/PBAu1200 board platform device registration
3 * 3 *
4 * Copyright (C) 2008-2009 Manuel Lauss 4 * Copyright (C) 2008-2011 Manuel Lauss
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -22,6 +22,7 @@
22#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/i2c.h> 23#include <linux/i2c.h>
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/interrupt.h>
25#include <linux/io.h> 26#include <linux/io.h>
26#include <linux/leds.h> 27#include <linux/leds.h>
27#include <linux/mmc/host.h> 28#include <linux/mmc/host.h>
@@ -33,18 +34,116 @@
33#include <linux/spi/spi.h> 34#include <linux/spi/spi.h>
34#include <linux/spi/flash.h> 35#include <linux/spi/flash.h>
35#include <linux/smc91x.h> 36#include <linux/smc91x.h>
36 37#include <asm/mach-au1x00/au1000.h>
37#include <asm/mach-au1x00/au1100_mmc.h> 38#include <asm/mach-au1x00/au1100_mmc.h>
38#include <asm/mach-au1x00/au1xxx_dbdma.h> 39#include <asm/mach-au1x00/au1xxx_dbdma.h>
40#include <asm/mach-au1x00/au1200fb.h>
39#include <asm/mach-au1x00/au1550_spi.h> 41#include <asm/mach-au1x00/au1550_spi.h>
40#include <asm/mach-db1x00/bcsr.h> 42#include <asm/mach-db1x00/bcsr.h>
41#include <asm/mach-db1x00/db1200.h> 43#include <asm/mach-db1x00/db1200.h>
42 44
43#include "../platform.h" 45#include "platform.h"
46
47static const char *board_type_str(void)
48{
49 switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
50 case BCSR_WHOAMI_PB1200_DDR1:
51 case BCSR_WHOAMI_PB1200_DDR2:
52 return "PB1200";
53 case BCSR_WHOAMI_DB1200:
54 return "DB1200";
55 default:
56 return "(unknown)";
57 }
58}
59
60const char *get_system_type(void)
61{
62 return board_type_str();
63}
64
65static int __init detect_board(void)
66{
67 int bid;
68
69 /* try the DB1200 first */
70 bcsr_init(DB1200_BCSR_PHYS_ADDR,
71 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
72 if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
73 unsigned short t = bcsr_read(BCSR_HEXLEDS);
74 bcsr_write(BCSR_HEXLEDS, ~t);
75 if (bcsr_read(BCSR_HEXLEDS) != t) {
76 bcsr_write(BCSR_HEXLEDS, t);
77 return 0;
78 }
79 }
80
81 /* okay, try the PB1200 then */
82 bcsr_init(PB1200_BCSR_PHYS_ADDR,
83 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
84 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
85 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
86 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
87 unsigned short t = bcsr_read(BCSR_HEXLEDS);
88 bcsr_write(BCSR_HEXLEDS, ~t);
89 if (bcsr_read(BCSR_HEXLEDS) != t) {
90 bcsr_write(BCSR_HEXLEDS, t);
91 return 0;
92 }
93 }
94
95 return 1; /* it's neither */
96}
97
98void __init board_setup(void)
99{
100 unsigned long freq0, clksrc, div, pfc;
101 unsigned short whoami;
102
103 if (detect_board()) {
104 printk(KERN_ERR "NOT running on a DB1200/PB1200 board!\n");
105 return;
106 }
107
108 whoami = bcsr_read(BCSR_WHOAMI);
109 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
110 " Board-ID %d Daughtercard ID %d\n", board_type_str(),
111 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
112
113 /* SMBus/SPI on PSC0, Audio on PSC1 */
114 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
115 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
116 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
117 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
118 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
119 wmb();
120
121 /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
122 * CPU clock; all other clock generators off/unused.
123 */
124 div = (get_au1x00_speed() + 25000000) / 50000000;
125 if (div & 1)
126 div++;
127 div = ((div >> 1) - 1) & 0xff;
128
129 freq0 = div << SYS_FC_FRDIV0_BIT;
130 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
131 wmb();
132 freq0 |= SYS_FC_FE0; /* enable F0 */
133 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
134 wmb();
135
136 /* psc0_intclk comes 1:1 from F0 */
137 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
138 __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
139 wmb();
140}
141
142/******************************************************************************/
44 143
45static struct mtd_partition db1200_spiflash_parts[] = { 144static struct mtd_partition db1200_spiflash_parts[] = {
46 { 145 {
47 .name = "DB1200 SPI flash", 146 .name = "spi_flash",
48 .offset = 0, 147 .offset = 0,
49 .size = MTDPART_SIZ_FULL, 148 .size = MTDPART_SIZ_FULL,
50 }, 149 },
@@ -78,18 +177,9 @@ static struct spi_board_info db1200_spi_devs[] __initdata = {
78}; 177};
79 178
80static struct i2c_board_info db1200_i2c_devs[] __initdata = { 179static struct i2c_board_info db1200_i2c_devs[] __initdata = {
81 { 180 { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */
82 /* AT24C04-10 I2C eeprom */ 181 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
83 I2C_BOARD_INFO("24c04", 0x52), 182 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */
84 },
85 {
86 /* Philips NE1619 temp/voltage sensor (adm1025 drv) */
87 I2C_BOARD_INFO("ne1619", 0x2d),
88 },
89 {
90 /* I2S audio codec WM8731 */
91 I2C_BOARD_INFO("wm8731", 0x1b),
92 },
93}; 183};
94 184
95/**********************************************************************/ 185/**********************************************************************/
@@ -206,7 +296,7 @@ static struct platform_device db1200_eth_dev = {
206static struct resource db1200_ide_res[] = { 296static struct resource db1200_ide_res[] = {
207 [0] = { 297 [0] = {
208 .start = DB1200_IDE_PHYS_ADDR, 298 .start = DB1200_IDE_PHYS_ADDR,
209 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1, 299 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
210 .flags = IORESOURCE_MEM, 300 .flags = IORESOURCE_MEM,
211 }, 301 },
212 [1] = { 302 [1] = {
@@ -221,13 +311,13 @@ static struct resource db1200_ide_res[] = {
221 }, 311 },
222}; 312};
223 313
224static u64 ide_dmamask = DMA_BIT_MASK(32); 314static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);
225 315
226static struct platform_device db1200_ide_dev = { 316static struct platform_device db1200_ide_dev = {
227 .name = "au1200-ide", 317 .name = "au1200-ide",
228 .id = 0, 318 .id = 0,
229 .dev = { 319 .dev = {
230 .dma_mask = &ide_dmamask, 320 .dma_mask = &au1200_ide_dmamask,
231 .coherent_dma_mask = DMA_BIT_MASK(32), 321 .coherent_dma_mask = DMA_BIT_MASK(32),
232 }, 322 },
233 .num_resources = ARRAY_SIZE(db1200_ide_res), 323 .num_resources = ARRAY_SIZE(db1200_ide_res),
@@ -236,13 +326,6 @@ static struct platform_device db1200_ide_dev = {
236 326
237/**********************************************************************/ 327/**********************************************************************/
238 328
239static struct platform_device db1200_rtc_dev = {
240 .name = "rtc-au1xxx",
241 .id = -1,
242};
243
244/**********************************************************************/
245
246/* SD carddetects: they're supposed to be edge-triggered, but ack 329/* SD carddetects: they're supposed to be edge-triggered, but ack
247 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one 330 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one
248 * is disabled and its counterpart enabled. The 500ms timeout is 331 * is disabled and its counterpart enabled. The 500ms timeout is
@@ -333,12 +416,109 @@ static struct led_classdev db1200_mmc_led = {
333 .brightness_set = db1200_mmcled_set, 416 .brightness_set = db1200_mmcled_set,
334}; 417};
335 418
336static struct au1xmmc_platform_data db1200mmc_platdata = { 419/* -- */
337 .cd_setup = db1200_mmc_cd_setup, 420
338 .set_power = db1200_mmc_set_power, 421static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
339 .card_inserted = db1200_mmc_card_inserted, 422{
340 .card_readonly = db1200_mmc_card_readonly, 423 void(*mmc_cd)(struct mmc_host *, unsigned long);
341 .led = &db1200_mmc_led, 424
425 if (irq == PB1200_SD1_INSERT_INT) {
426 disable_irq_nosync(PB1200_SD1_INSERT_INT);
427 enable_irq(PB1200_SD1_EJECT_INT);
428 } else {
429 disable_irq_nosync(PB1200_SD1_EJECT_INT);
430 enable_irq(PB1200_SD1_INSERT_INT);
431 }
432
433 /* link against CONFIG_MMC=m */
434 mmc_cd = symbol_get(mmc_detect_change);
435 if (mmc_cd) {
436 mmc_cd(ptr, msecs_to_jiffies(500));
437 symbol_put(mmc_detect_change);
438 }
439
440 return IRQ_HANDLED;
441}
442
443static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
444{
445 int ret;
446
447 if (en) {
448 ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0,
449 "sd1_insert", mmc_host);
450 if (ret)
451 goto out;
452
453 ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0,
454 "sd1_eject", mmc_host);
455 if (ret) {
456 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
457 goto out;
458 }
459
460 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
461 enable_irq(PB1200_SD1_EJECT_INT);
462 else
463 enable_irq(PB1200_SD1_INSERT_INT);
464
465 } else {
466 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
467 free_irq(PB1200_SD1_EJECT_INT, mmc_host);
468 }
469 ret = 0;
470out:
471 return ret;
472}
473
474static void pb1200_mmc1led_set(struct led_classdev *led,
475 enum led_brightness brightness)
476{
477 if (brightness != LED_OFF)
478 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
479 else
480 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
481}
482
483static struct led_classdev pb1200_mmc1_led = {
484 .brightness_set = pb1200_mmc1led_set,
485};
486
487static void pb1200_mmc1_set_power(void *mmc_host, int state)
488{
489 if (state) {
490 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
491 msleep(400); /* stabilization time */
492 } else
493 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
494}
495
496static int pb1200_mmc1_card_readonly(void *mmc_host)
497{
498 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
499}
500
501static int pb1200_mmc1_card_inserted(void *mmc_host)
502{
503 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
504}
505
506
507static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
508 [0] = {
509 .cd_setup = db1200_mmc_cd_setup,
510 .set_power = db1200_mmc_set_power,
511 .card_inserted = db1200_mmc_card_inserted,
512 .card_readonly = db1200_mmc_card_readonly,
513 .led = &db1200_mmc_led,
514 },
515 [1] = {
516 .cd_setup = pb1200_mmc1_cd_setup,
517 .set_power = pb1200_mmc1_set_power,
518 .card_inserted = pb1200_mmc1_card_inserted,
519 .card_readonly = pb1200_mmc1_card_readonly,
520 .led = &pb1200_mmc1_led,
521 },
342}; 522};
343 523
344static struct resource au1200_mmc0_resources[] = { 524static struct resource au1200_mmc0_resources[] = {
@@ -372,14 +552,76 @@ static struct platform_device db1200_mmc0_dev = {
372 .dev = { 552 .dev = {
373 .dma_mask = &au1xxx_mmc_dmamask, 553 .dma_mask = &au1xxx_mmc_dmamask,
374 .coherent_dma_mask = DMA_BIT_MASK(32), 554 .coherent_dma_mask = DMA_BIT_MASK(32),
375 .platform_data = &db1200mmc_platdata, 555 .platform_data = &db1200_mmc_platdata[0],
376 }, 556 },
377 .num_resources = ARRAY_SIZE(au1200_mmc0_resources), 557 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
378 .resource = au1200_mmc0_resources, 558 .resource = au1200_mmc0_resources,
379}; 559};
380 560
561static struct resource au1200_mmc1_res[] = {
562 [0] = {
563 .start = AU1100_SD1_PHYS_ADDR,
564 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
565 .flags = IORESOURCE_MEM,
566 },
567 [1] = {
568 .start = AU1200_SD_INT,
569 .end = AU1200_SD_INT,
570 .flags = IORESOURCE_IRQ,
571 },
572 [2] = {
573 .start = AU1200_DSCR_CMD0_SDMS_TX1,
574 .end = AU1200_DSCR_CMD0_SDMS_TX1,
575 .flags = IORESOURCE_DMA,
576 },
577 [3] = {
578 .start = AU1200_DSCR_CMD0_SDMS_RX1,
579 .end = AU1200_DSCR_CMD0_SDMS_RX1,
580 .flags = IORESOURCE_DMA,
581 }
582};
583
584static struct platform_device pb1200_mmc1_dev = {
585 .name = "au1xxx-mmc",
586 .id = 1,
587 .dev = {
588 .dma_mask = &au1xxx_mmc_dmamask,
589 .coherent_dma_mask = DMA_BIT_MASK(32),
590 .platform_data = &db1200_mmc_platdata[1],
591 },
592 .num_resources = ARRAY_SIZE(au1200_mmc1_res),
593 .resource = au1200_mmc1_res,
594};
595
381/**********************************************************************/ 596/**********************************************************************/
382 597
598static int db1200fb_panel_index(void)
599{
600 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
601}
602
603static int db1200fb_panel_init(void)
604{
605 /* Apply power */
606 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
607 BCSR_BOARD_LCDBL);
608 return 0;
609}
610
611static int db1200fb_panel_shutdown(void)
612{
613 /* Remove power */
614 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
615 BCSR_BOARD_LCDBL, 0);
616 return 0;
617}
618
619static struct au1200fb_platdata db1200fb_pd = {
620 .panel_index = db1200fb_panel_index,
621 .panel_init = db1200fb_panel_init,
622 .panel_shutdown = db1200fb_panel_shutdown,
623};
624
383static struct resource au1200_lcd_res[] = { 625static struct resource au1200_lcd_res[] = {
384 [0] = { 626 [0] = {
385 .start = AU1200_LCD_PHYS_ADDR, 627 .start = AU1200_LCD_PHYS_ADDR,
@@ -401,6 +643,7 @@ static struct platform_device au1200_lcd_dev = {
401 .dev = { 643 .dev = {
402 .dma_mask = &au1200_lcd_dmamask, 644 .dma_mask = &au1200_lcd_dmamask,
403 .coherent_dma_mask = DMA_BIT_MASK(32), 645 .coherent_dma_mask = DMA_BIT_MASK(32),
646 .platform_data = &db1200fb_pd,
404 }, 647 },
405 .num_resources = ARRAY_SIZE(au1200_lcd_res), 648 .num_resources = ARRAY_SIZE(au1200_lcd_res),
406 .resource = au1200_lcd_res, 649 .resource = au1200_lcd_res,
@@ -519,7 +762,6 @@ static struct platform_device *db1200_devs[] __initdata = {
519 &db1200_mmc0_dev, 762 &db1200_mmc0_dev,
520 &au1200_lcd_dev, 763 &au1200_lcd_dev,
521 &db1200_eth_dev, 764 &db1200_eth_dev,
522 &db1200_rtc_dev,
523 &db1200_nand_dev, 765 &db1200_nand_dev,
524 &db1200_audiodma_dev, 766 &db1200_audiodma_dev,
525 &db1200_audio_dev, 767 &db1200_audio_dev,
@@ -527,11 +769,62 @@ static struct platform_device *db1200_devs[] __initdata = {
527 &db1200_sound_dev, 769 &db1200_sound_dev,
528}; 770};
529 771
772static struct platform_device *pb1200_devs[] __initdata = {
773 &pb1200_mmc1_dev,
774};
775
776/* Some peripheral base addresses differ on the PB1200 */
777static int __init pb1200_res_fixup(void)
778{
779 /* CPLD Revs earlier than 4 cause problems */
780 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
781 printk(KERN_ERR "WARNING!!!\n");
782 printk(KERN_ERR "WARNING!!!\n");
783 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
784 printk(KERN_ERR "the board updated to latest revisions.\n");
785 printk(KERN_ERR "This software will not work reliably\n");
786 printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
787 printk(KERN_ERR "WARNING!!!\n");
788 printk(KERN_ERR "WARNING!!!\n");
789 return 1;
790 }
791
792 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
793 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff;
794 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
795 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
796 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
797 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff;
798 return 0;
799}
800
530static int __init db1200_dev_init(void) 801static int __init db1200_dev_init(void)
531{ 802{
532 unsigned long pfc; 803 unsigned long pfc;
533 unsigned short sw; 804 unsigned short sw;
534 int swapped; 805 int swapped, bid;
806
807 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
808 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
809 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
810 if (pb1200_res_fixup())
811 return -ENODEV;
812 }
813
814 /* GPIO7 is low-level triggered CPLD cascade */
815 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
816 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
817
818 /* insert/eject pairs: one of both is always screaming. To avoid
819 * issues they must not be automatically enabled when initially
820 * requested.
821 */
822 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
823 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
824 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
825 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
826 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
827 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
535 828
536 i2c_register_board_info(0, db1200_i2c_devs, 829 i2c_register_board_info(0, db1200_i2c_devs,
537 ARRAY_SIZE(db1200_i2c_devs)); 830 ARRAY_SIZE(db1200_i2c_devs));
@@ -540,6 +833,7 @@ static int __init db1200_dev_init(void)
540 833
541 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) 834 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
542 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) 835 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
836 * or S12 on the PB1200.
543 */ 837 */
544 838
545 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however 839 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however
@@ -554,7 +848,7 @@ static int __init db1200_dev_init(void)
554 gpio_request(215, "otg-vbus"); 848 gpio_request(215, "otg-vbus");
555 gpio_direction_output(215, 1); 849 gpio_direction_output(215, 1);
556 850
557 printk(KERN_INFO "DB1200 device configuration:\n"); 851 printk(KERN_INFO "%s device configuration:\n", board_type_str());
558 852
559 sw = bcsr_read(BCSR_SWITCHES); 853 sw = bcsr_read(BCSR_SWITCHES);
560 if (sw & BCSR_SWITCHES_DIP_8) { 854 if (sw & BCSR_SWITCHES_DIP_8) {
@@ -595,7 +889,7 @@ static int __init db1200_dev_init(void)
595 889
596 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ 890 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
597 __raw_writel(PSC_SEL_CLK_SERCLK, 891 __raw_writel(PSC_SEL_CLK_SERCLK,
598 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 892 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
599 wmb(); 893 wmb();
600 894
601 db1x_register_pcmcia_socket( 895 db1x_register_pcmcia_socket(
@@ -621,28 +915,13 @@ static int __init db1200_dev_init(void)
621 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 915 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
622 db1x_register_norflash(64 << 20, 2, swapped); 916 db1x_register_norflash(64 << 20, 2, swapped);
623 917
624 return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); 918 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
625}
626device_initcall(db1200_dev_init);
627
628/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */
629int board_au1200fb_panel(void)
630{
631 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
632}
633 919
634int board_au1200fb_panel_init(void) 920 /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */
635{ 921 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
636 /* Apply power */ 922 (bid == BCSR_WHOAMI_PB1200_DDR2))
637 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 923 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
638 BCSR_BOARD_LCDBL);
639 return 0;
640}
641 924
642int board_au1200fb_panel_shutdown(void)
643{
644 /* Remove power */
645 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
646 BCSR_BOARD_LCDBL, 0);
647 return 0; 925 return 0;
648} 926}
927device_initcall(db1200_dev_init);
diff --git a/arch/mips/alchemy/devboards/db1200/Makefile b/arch/mips/alchemy/devboards/db1200/Makefile
deleted file mode 100644
index 17840a5e2738..000000000000
--- a/arch/mips/alchemy/devboards/db1200/Makefile
+++ /dev/null
@@ -1 +0,0 @@
1obj-y += setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
deleted file mode 100644
index 4a8980027ecf..000000000000
--- a/arch/mips/alchemy/devboards/db1200/setup.c
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * Alchemy/AMD/RMI DB1200 board setup.
3 *
4 * Licensed under the terms outlined in the file COPYING in the root of
5 * this source archive.
6 */
7
8#include <linux/init.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <asm/mach-au1x00/au1000.h>
13#include <asm/mach-db1x00/bcsr.h>
14#include <asm/mach-db1x00/db1200.h>
15
16const char *get_system_type(void)
17{
18 return "Alchemy Db1200";
19}
20
21void __init board_setup(void)
22{
23 unsigned long freq0, clksrc, div, pfc;
24 unsigned short whoami;
25
26 bcsr_init(DB1200_BCSR_PHYS_ADDR,
27 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
28
29 whoami = bcsr_read(BCSR_WHOAMI);
30 printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
31 " Board-ID %d Daughtercard ID %d\n",
32 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
33
34 /* SMBus/SPI on PSC0, Audio on PSC1 */
35 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
36 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
37 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
38 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
39 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
40 wmb();
41
42 /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
43 * CPU clock; all other clock generators off/unused.
44 */
45 div = (get_au1x00_speed() + 25000000) / 50000000;
46 if (div & 1)
47 div++;
48 div = ((div >> 1) - 1) & 0xff;
49
50 freq0 = div << SYS_FC_FRDIV0_BIT;
51 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
52 wmb();
53 freq0 |= SYS_FC_FE0; /* enable F0 */
54 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
55 wmb();
56
57 /* psc0_intclk comes 1:1 from F0 */
58 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
59 __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
60 wmb();
61}
62
63static int __init db1200_arch_init(void)
64{
65 /* GPIO7 is low-level triggered CPLD cascade */
66 irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
67 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
68
69 /* insert/eject pairs: one of both is always screaming. To avoid
70 * issues they must not be automatically enabled when initially
71 * requested.
72 */
73 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
74 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
75 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
76 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
77 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
78 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
79 return 0;
80}
81arch_initcall(db1200_arch_init);
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
new file mode 100644
index 000000000000..0893f2af0d01
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -0,0 +1,785 @@
1/*
2 * DBAu1300 init and platform device setup.
3 *
4 * (c) 2009 Manuel Lauss <manuel.lauss@googlemail.com>
5 */
6
7#include <linux/dma-mapping.h>
8#include <linux/gpio.h>
9#include <linux/gpio_keys.h>
10#include <linux/init.h>
11#include <linux/input.h> /* KEY_* codes */
12#include <linux/i2c.h>
13#include <linux/io.h>
14#include <linux/leds.h>
15#include <linux/ata_platform.h>
16#include <linux/mmc/host.h>
17#include <linux/module.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21#include <linux/platform_device.h>
22#include <linux/smsc911x.h>
23
24#include <asm/mach-au1x00/au1000.h>
25#include <asm/mach-au1x00/au1100_mmc.h>
26#include <asm/mach-au1x00/au1200fb.h>
27#include <asm/mach-au1x00/au1xxx_dbdma.h>
28#include <asm/mach-au1x00/au1xxx_psc.h>
29#include <asm/mach-db1x00/db1300.h>
30#include <asm/mach-db1x00/bcsr.h>
31#include <asm/mach-au1x00/prom.h>
32
33#include "platform.h"
34
35static struct i2c_board_info db1300_i2c_devs[] __initdata = {
36 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */
37 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
38};
39
40/* multifunction pins to assign to GPIO controller */
41static int db1300_gpio_pins[] __initdata = {
42 AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1,
43 AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX,
44 AU1300_PIN_EXTCLK1,
45 -1, /* terminator */
46};
47
48/* multifunction pins to assign to device functions */
49static int db1300_dev_pins[] __initdata = {
50 /* wake-from-str pins 0-3 */
51 AU1300_PIN_WAKE0,
52 /* external clock sources for PSC0 */
53 AU1300_PIN_EXTCLK0,
54 /* 8bit MMC interface on SD0: 6-9 */
55 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
56 AU1300_PIN_SD0DAT7,
57 /* UART1 pins: 11-18 */
58 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
59 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
60 AU1300_PIN_U1RX, AU1300_PIN_U1TX,
61 /* UART0 pins: 19-24 */
62 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
63 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
64 /* UART2: 25-26 */
65 AU1300_PIN_U2RX, AU1300_PIN_U2TX,
66 /* UART3: 27-28 */
67 AU1300_PIN_U3RX, AU1300_PIN_U3TX,
68 /* LCD controller PWMs, ext pixclock: 30-31 */
69 AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
70 /* SD1 interface: 32-37 */
71 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
72 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
73 /* SD2 interface: 38-43 */
74 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
75 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
76 /* PSC0/1 clocks: 44-45 */
77 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
78 /* PSCs: 46-49/50-53/54-57/58-61 */
79 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
80 AU1300_PIN_PSC0D1,
81 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
82 AU1300_PIN_PSC1D1,
83 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0,
84 AU1300_PIN_PSC2D1,
85 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
86 AU1300_PIN_PSC3D1,
87 /* PCMCIA interface: 62-70 */
88 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
89 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
90 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
91 /* camera interface H/V sync inputs: 71-72 */
92 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
93 /* PSC2/3 clocks: 73-74 */
94 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
95 -1, /* terminator */
96};
97
98static void __init db1300_gpio_config(void)
99{
100 int *i;
101
102 i = &db1300_dev_pins[0];
103 while (*i != -1)
104 au1300_pinfunc_to_dev(*i++);
105
106 i = &db1300_gpio_pins[0];
107 while (*i != -1)
108 au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */
109
110 au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX);
111}
112
113char *get_system_type(void)
114{
115 return "DB1300";
116}
117
118/**********************************************************************/
119
120static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
121 unsigned int ctrl)
122{
123 struct nand_chip *this = mtd->priv;
124 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
125
126 ioaddr &= 0xffffff00;
127
128 if (ctrl & NAND_CLE) {
129 ioaddr += MEM_STNAND_CMD;
130 } else if (ctrl & NAND_ALE) {
131 ioaddr += MEM_STNAND_ADDR;
132 } else {
133 /* assume we want to r/w real data by default */
134 ioaddr += MEM_STNAND_DATA;
135 }
136 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
137 if (cmd != NAND_CMD_NONE) {
138 __raw_writeb(cmd, this->IO_ADDR_W);
139 wmb();
140 }
141}
142
143static int au1300_nand_device_ready(struct mtd_info *mtd)
144{
145 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
146}
147
148static const char *db1300_part_probes[] = { "cmdlinepart", NULL };
149
150static struct mtd_partition db1300_nand_parts[] = {
151 {
152 .name = "NAND FS 0",
153 .offset = 0,
154 .size = 8 * 1024 * 1024,
155 },
156 {
157 .name = "NAND FS 1",
158 .offset = MTDPART_OFS_APPEND,
159 .size = MTDPART_SIZ_FULL
160 },
161};
162
163struct platform_nand_data db1300_nand_platdata = {
164 .chip = {
165 .nr_chips = 1,
166 .chip_offset = 0,
167 .nr_partitions = ARRAY_SIZE(db1300_nand_parts),
168 .partitions = db1300_nand_parts,
169 .chip_delay = 20,
170 .part_probe_types = db1300_part_probes,
171 },
172 .ctrl = {
173 .dev_ready = au1300_nand_device_ready,
174 .cmd_ctrl = au1300_nand_cmd_ctrl,
175 },
176};
177
178static struct resource db1300_nand_res[] = {
179 [0] = {
180 .start = DB1300_NAND_PHYS_ADDR,
181 .end = DB1300_NAND_PHYS_ADDR + 0xff,
182 .flags = IORESOURCE_MEM,
183 },
184};
185
186static struct platform_device db1300_nand_dev = {
187 .name = "gen_nand",
188 .num_resources = ARRAY_SIZE(db1300_nand_res),
189 .resource = db1300_nand_res,
190 .id = -1,
191 .dev = {
192 .platform_data = &db1300_nand_platdata,
193 }
194};
195
196/**********************************************************************/
197
198static struct resource db1300_eth_res[] = {
199 [0] = {
200 .start = DB1300_ETH_PHYS_ADDR,
201 .end = DB1300_ETH_PHYS_END,
202 .flags = IORESOURCE_MEM,
203 },
204 [1] = {
205 .start = DB1300_ETH_INT,
206 .end = DB1300_ETH_INT,
207 .flags = IORESOURCE_IRQ,
208 },
209};
210
211static struct smsc911x_platform_config db1300_eth_config = {
212 .phy_interface = PHY_INTERFACE_MODE_MII,
213 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
214 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
215 .flags = SMSC911X_USE_32BIT,
216};
217
218static struct platform_device db1300_eth_dev = {
219 .name = "smsc911x",
220 .id = -1,
221 .num_resources = ARRAY_SIZE(db1300_eth_res),
222 .resource = db1300_eth_res,
223 .dev = {
224 .platform_data = &db1300_eth_config,
225 },
226};
227
228/**********************************************************************/
229
230static struct resource au1300_psc1_res[] = {
231 [0] = {
232 .start = AU1300_PSC1_PHYS_ADDR,
233 .end = AU1300_PSC1_PHYS_ADDR + 0x0fff,
234 .flags = IORESOURCE_MEM,
235 },
236 [1] = {
237 .start = AU1300_PSC1_INT,
238 .end = AU1300_PSC1_INT,
239 .flags = IORESOURCE_IRQ,
240 },
241 [2] = {
242 .start = AU1300_DSCR_CMD0_PSC1_TX,
243 .end = AU1300_DSCR_CMD0_PSC1_TX,
244 .flags = IORESOURCE_DMA,
245 },
246 [3] = {
247 .start = AU1300_DSCR_CMD0_PSC1_RX,
248 .end = AU1300_DSCR_CMD0_PSC1_RX,
249 .flags = IORESOURCE_DMA,
250 },
251};
252
253static struct platform_device db1300_ac97_dev = {
254 .name = "au1xpsc_ac97",
255 .id = 1, /* PSC ID. match with AC97 codec ID! */
256 .num_resources = ARRAY_SIZE(au1300_psc1_res),
257 .resource = au1300_psc1_res,
258};
259
260/**********************************************************************/
261
262static struct resource au1300_psc2_res[] = {
263 [0] = {
264 .start = AU1300_PSC2_PHYS_ADDR,
265 .end = AU1300_PSC2_PHYS_ADDR + 0x0fff,
266 .flags = IORESOURCE_MEM,
267 },
268 [1] = {
269 .start = AU1300_PSC2_INT,
270 .end = AU1300_PSC2_INT,
271 .flags = IORESOURCE_IRQ,
272 },
273 [2] = {
274 .start = AU1300_DSCR_CMD0_PSC2_TX,
275 .end = AU1300_DSCR_CMD0_PSC2_TX,
276 .flags = IORESOURCE_DMA,
277 },
278 [3] = {
279 .start = AU1300_DSCR_CMD0_PSC2_RX,
280 .end = AU1300_DSCR_CMD0_PSC2_RX,
281 .flags = IORESOURCE_DMA,
282 },
283};
284
285static struct platform_device db1300_i2s_dev = {
286 .name = "au1xpsc_i2s",
287 .id = 2, /* PSC ID */
288 .num_resources = ARRAY_SIZE(au1300_psc2_res),
289 .resource = au1300_psc2_res,
290};
291
292/**********************************************************************/
293
294static struct resource au1300_psc3_res[] = {
295 [0] = {
296 .start = AU1300_PSC3_PHYS_ADDR,
297 .end = AU1300_PSC3_PHYS_ADDR + 0x0fff,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = AU1300_PSC3_INT,
302 .end = AU1300_PSC3_INT,
303 .flags = IORESOURCE_IRQ,
304 },
305 [2] = {
306 .start = AU1300_DSCR_CMD0_PSC3_TX,
307 .end = AU1300_DSCR_CMD0_PSC3_TX,
308 .flags = IORESOURCE_DMA,
309 },
310 [3] = {
311 .start = AU1300_DSCR_CMD0_PSC3_RX,
312 .end = AU1300_DSCR_CMD0_PSC3_RX,
313 .flags = IORESOURCE_DMA,
314 },
315};
316
317static struct platform_device db1300_i2c_dev = {
318 .name = "au1xpsc_smbus",
319 .id = 0, /* bus number */
320 .num_resources = ARRAY_SIZE(au1300_psc3_res),
321 .resource = au1300_psc3_res,
322};
323
324/**********************************************************************/
325
326/* proper key assignments when facing the LCD panel. For key assignments
327 * according to the schematics swap up with down and left with right.
328 * I chose to use it to emulate the arrow keys of a keyboard.
329 */
330static struct gpio_keys_button db1300_5waysw_arrowkeys[] = {
331 {
332 .code = KEY_DOWN,
333 .gpio = AU1300_PIN_LCDPWM0,
334 .type = EV_KEY,
335 .debounce_interval = 1,
336 .active_low = 1,
337 .desc = "5waysw-down",
338 },
339 {
340 .code = KEY_UP,
341 .gpio = AU1300_PIN_PSC2SYNC1,
342 .type = EV_KEY,
343 .debounce_interval = 1,
344 .active_low = 1,
345 .desc = "5waysw-up",
346 },
347 {
348 .code = KEY_RIGHT,
349 .gpio = AU1300_PIN_WAKE3,
350 .type = EV_KEY,
351 .debounce_interval = 1,
352 .active_low = 1,
353 .desc = "5waysw-right",
354 },
355 {
356 .code = KEY_LEFT,
357 .gpio = AU1300_PIN_WAKE2,
358 .type = EV_KEY,
359 .debounce_interval = 1,
360 .active_low = 1,
361 .desc = "5waysw-left",
362 },
363 {
364 .code = KEY_ENTER,
365 .gpio = AU1300_PIN_WAKE1,
366 .type = EV_KEY,
367 .debounce_interval = 1,
368 .active_low = 1,
369 .desc = "5waysw-push",
370 },
371};
372
373static struct gpio_keys_platform_data db1300_5waysw_data = {
374 .buttons = db1300_5waysw_arrowkeys,
375 .nbuttons = ARRAY_SIZE(db1300_5waysw_arrowkeys),
376 .rep = 1,
377 .name = "db1300-5wayswitch",
378};
379
380static struct platform_device db1300_5waysw_dev = {
381 .name = "gpio-keys",
382 .dev = {
383 .platform_data = &db1300_5waysw_data,
384 },
385};
386
387/**********************************************************************/
388
389static struct pata_platform_info db1300_ide_info = {
390 .ioport_shift = DB1300_IDE_REG_SHIFT,
391};
392
393#define IDE_ALT_START (14 << DB1300_IDE_REG_SHIFT)
394static struct resource db1300_ide_res[] = {
395 [0] = {
396 .start = DB1300_IDE_PHYS_ADDR,
397 .end = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1,
398 .flags = IORESOURCE_MEM,
399 },
400 [1] = {
401 .start = DB1300_IDE_PHYS_ADDR + IDE_ALT_START,
402 .end = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1,
403 .flags = IORESOURCE_MEM,
404 },
405 [2] = {
406 .start = DB1300_IDE_INT,
407 .end = DB1300_IDE_INT,
408 .flags = IORESOURCE_IRQ,
409 },
410};
411
412static struct platform_device db1300_ide_dev = {
413 .dev = {
414 .platform_data = &db1300_ide_info,
415 },
416 .name = "pata_platform",
417 .resource = db1300_ide_res,
418 .num_resources = ARRAY_SIZE(db1300_ide_res),
419};
420
421/**********************************************************************/
422
423static irqreturn_t db1300_mmc_cd(int irq, void *ptr)
424{
425 void(*mmc_cd)(struct mmc_host *, unsigned long);
426
427 /* disable the one currently screaming. No other way to shut it up */
428 if (irq == DB1300_SD1_INSERT_INT) {
429 disable_irq_nosync(DB1300_SD1_INSERT_INT);
430 enable_irq(DB1300_SD1_EJECT_INT);
431 } else {
432 disable_irq_nosync(DB1300_SD1_EJECT_INT);
433 enable_irq(DB1300_SD1_INSERT_INT);
434 }
435
436 /* link against CONFIG_MMC=m. We can only be called once MMC core has
437 * initialized the controller, so symbol_get() should always succeed.
438 */
439 mmc_cd = symbol_get(mmc_detect_change);
440 mmc_cd(ptr, msecs_to_jiffies(500));
441 symbol_put(mmc_detect_change);
442
443 return IRQ_HANDLED;
444}
445
446static int db1300_mmc_card_readonly(void *mmc_host)
447{
448 /* it uses SD1 interface, but the DB1200's SD0 bit in the CPLD */
449 return bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP;
450}
451
452static int db1300_mmc_card_inserted(void *mmc_host)
453{
454 return bcsr_read(BCSR_SIGSTAT) & (1 << 12); /* insertion irq signal */
455}
456
457static int db1300_mmc_cd_setup(void *mmc_host, int en)
458{
459 int ret;
460
461 if (en) {
462 ret = request_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 0,
463 "sd_insert", mmc_host);
464 if (ret)
465 goto out;
466
467 ret = request_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 0,
468 "sd_eject", mmc_host);
469 if (ret) {
470 free_irq(DB1300_SD1_INSERT_INT, mmc_host);
471 goto out;
472 }
473
474 if (db1300_mmc_card_inserted(mmc_host))
475 enable_irq(DB1300_SD1_EJECT_INT);
476 else
477 enable_irq(DB1300_SD1_INSERT_INT);
478
479 } else {
480 free_irq(DB1300_SD1_INSERT_INT, mmc_host);
481 free_irq(DB1300_SD1_EJECT_INT, mmc_host);
482 }
483 ret = 0;
484out:
485 return ret;
486}
487
488static void db1300_mmcled_set(struct led_classdev *led,
489 enum led_brightness brightness)
490{
491 if (brightness != LED_OFF)
492 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
493 else
494 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
495}
496
497static struct led_classdev db1300_mmc_led = {
498 .brightness_set = db1300_mmcled_set,
499};
500
501struct au1xmmc_platform_data db1300_sd1_platdata = {
502 .cd_setup = db1300_mmc_cd_setup,
503 .card_inserted = db1300_mmc_card_inserted,
504 .card_readonly = db1300_mmc_card_readonly,
505 .led = &db1300_mmc_led,
506};
507
508static struct resource au1300_sd1_res[] = {
509 [0] = {
510 .start = AU1300_SD1_PHYS_ADDR,
511 .end = AU1300_SD1_PHYS_ADDR,
512 .flags = IORESOURCE_MEM,
513 },
514 [1] = {
515 .start = AU1300_SD1_INT,
516 .end = AU1300_SD1_INT,
517 .flags = IORESOURCE_IRQ,
518 },
519 [2] = {
520 .start = AU1300_DSCR_CMD0_SDMS_TX1,
521 .end = AU1300_DSCR_CMD0_SDMS_TX1,
522 .flags = IORESOURCE_DMA,
523 },
524 [3] = {
525 .start = AU1300_DSCR_CMD0_SDMS_RX1,
526 .end = AU1300_DSCR_CMD0_SDMS_RX1,
527 .flags = IORESOURCE_DMA,
528 },
529};
530
531static struct platform_device db1300_sd1_dev = {
532 .dev = {
533 .platform_data = &db1300_sd1_platdata,
534 },
535 .name = "au1xxx-mmc",
536 .id = 1,
537 .resource = au1300_sd1_res,
538 .num_resources = ARRAY_SIZE(au1300_sd1_res),
539};
540
541/**********************************************************************/
542
543static int db1300_movinand_inserted(void *mmc_host)
544{
545 return 0; /* disable for now, it doesn't work yet */
546}
547
548static int db1300_movinand_readonly(void *mmc_host)
549{
550 return 0;
551}
552
553static void db1300_movinand_led_set(struct led_classdev *led,
554 enum led_brightness brightness)
555{
556 if (brightness != LED_OFF)
557 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
558 else
559 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
560}
561
562static struct led_classdev db1300_movinand_led = {
563 .brightness_set = db1300_movinand_led_set,
564};
565
566struct au1xmmc_platform_data db1300_sd0_platdata = {
567 .card_inserted = db1300_movinand_inserted,
568 .card_readonly = db1300_movinand_readonly,
569 .led = &db1300_movinand_led,
570 .mask_host_caps = MMC_CAP_NEEDS_POLL,
571};
572
573static struct resource au1300_sd0_res[] = {
574 [0] = {
575 .start = AU1100_SD0_PHYS_ADDR,
576 .end = AU1100_SD0_PHYS_ADDR,
577 .flags = IORESOURCE_MEM,
578 },
579 [1] = {
580 .start = AU1300_SD0_INT,
581 .end = AU1300_SD0_INT,
582 .flags = IORESOURCE_IRQ,
583 },
584 [2] = {
585 .start = AU1300_DSCR_CMD0_SDMS_TX0,
586 .end = AU1300_DSCR_CMD0_SDMS_TX0,
587 .flags = IORESOURCE_DMA,
588 },
589 [3] = {
590 .start = AU1300_DSCR_CMD0_SDMS_RX0,
591 .end = AU1300_DSCR_CMD0_SDMS_RX0,
592 .flags = IORESOURCE_DMA,
593 },
594};
595
596static struct platform_device db1300_sd0_dev = {
597 .dev = {
598 .platform_data = &db1300_sd0_platdata,
599 },
600 .name = "au1xxx-mmc",
601 .id = 0,
602 .resource = au1300_sd0_res,
603 .num_resources = ARRAY_SIZE(au1300_sd0_res),
604};
605
606/**********************************************************************/
607
608static struct platform_device db1300_wm9715_dev = {
609 .name = "wm9712-codec",
610 .id = 1, /* ID of PSC for AC97 audio, see asoc glue! */
611};
612
613static struct platform_device db1300_ac97dma_dev = {
614 .name = "au1xpsc-pcm",
615 .id = 1, /* PSC ID */
616};
617
618static struct platform_device db1300_i2sdma_dev = {
619 .name = "au1xpsc-pcm",
620 .id = 2, /* PSC ID */
621};
622
623static struct platform_device db1300_sndac97_dev = {
624 .name = "db1300-ac97",
625};
626
627static struct platform_device db1300_sndi2s_dev = {
628 .name = "db1300-i2s",
629};
630
631/**********************************************************************/
632
633static int db1300fb_panel_index(void)
634{
635 return 9; /* DB1300_800x480 */
636}
637
638static int db1300fb_panel_init(void)
639{
640 /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
641 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD,
642 BCSR_BOARD_LCDBL);
643 return 0;
644}
645
646static int db1300fb_panel_shutdown(void)
647{
648 /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
649 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL,
650 BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD);
651 return 0;
652}
653
654static struct au1200fb_platdata db1300fb_pd = {
655 .panel_index = db1300fb_panel_index,
656 .panel_init = db1300fb_panel_init,
657 .panel_shutdown = db1300fb_panel_shutdown,
658};
659
660static struct resource au1300_lcd_res[] = {
661 [0] = {
662 .start = AU1200_LCD_PHYS_ADDR,
663 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
664 .flags = IORESOURCE_MEM,
665 },
666 [1] = {
667 .start = AU1300_LCD_INT,
668 .end = AU1300_LCD_INT,
669 .flags = IORESOURCE_IRQ,
670 }
671};
672
673static u64 au1300_lcd_dmamask = DMA_BIT_MASK(32);
674
675static struct platform_device db1300_lcd_dev = {
676 .name = "au1200-lcd",
677 .id = 0,
678 .dev = {
679 .dma_mask = &au1300_lcd_dmamask,
680 .coherent_dma_mask = DMA_BIT_MASK(32),
681 .platform_data = &db1300fb_pd,
682 },
683 .num_resources = ARRAY_SIZE(au1300_lcd_res),
684 .resource = au1300_lcd_res,
685};
686
687/**********************************************************************/
688
689static struct platform_device *db1300_dev[] __initdata = {
690 &db1300_eth_dev,
691 &db1300_i2c_dev,
692 &db1300_5waysw_dev,
693 &db1300_nand_dev,
694 &db1300_ide_dev,
695 &db1300_sd0_dev,
696 &db1300_sd1_dev,
697 &db1300_lcd_dev,
698 &db1300_ac97_dev,
699 &db1300_i2s_dev,
700 &db1300_wm9715_dev,
701 &db1300_ac97dma_dev,
702 &db1300_i2sdma_dev,
703 &db1300_sndac97_dev,
704 &db1300_sndi2s_dev,
705};
706
707static int __init db1300_device_init(void)
708{
709 int swapped, cpldirq;
710
711 /* setup CPLD IRQ muxer */
712 cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1);
713 irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH);
714 bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq);
715
716 /* insert/eject IRQs: one always triggers so don't enable them
717 * when doing request_irq() on them. DB1200 has this bug too.
718 */
719 irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN);
720 irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN);
721 irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN);
722 irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN);
723
724 /*
725 * setup board
726 */
727 prom_get_ethernet_addr(&db1300_eth_config.mac[0]);
728
729 i2c_register_board_info(0, db1300_i2c_devs,
730 ARRAY_SIZE(db1300_i2c_devs));
731
732 /* Audio PSC clock is supplied by codecs (PSC1, 2) */
733 __raw_writel(PSC_SEL_CLK_SERCLK,
734 (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
735 wmb();
736 __raw_writel(PSC_SEL_CLK_SERCLK,
737 (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
738 wmb();
739 /* I2C uses internal 48MHz EXTCLK1 */
740 __raw_writel(PSC_SEL_CLK_INTCLK,
741 (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
742 wmb();
743
744 /* enable power to USB ports */
745 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR);
746
747 /* although it is socket #0, it uses the CPLD bits which previous boards
748 * have used for socket #1.
749 */
750 db1x_register_pcmcia_socket(
751 AU1000_PCMCIA_ATTR_PHYS_ADDR,
752 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1,
753 AU1000_PCMCIA_MEM_PHYS_ADDR,
754 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1,
755 AU1000_PCMCIA_IO_PHYS_ADDR,
756 AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1,
757 DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1);
758
759 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
760 db1x_register_norflash(64 << 20, 2, swapped);
761
762 return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev));
763}
764device_initcall(db1300_device_init);
765
766
767void __init board_setup(void)
768{
769 unsigned short whoami;
770
771 db1300_gpio_config();
772 bcsr_init(DB1300_BCSR_PHYS_ADDR,
773 DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS);
774
775 whoami = bcsr_read(BCSR_WHOAMI);
776 printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t"
777 "BoardID %d CPLD Rev %d DaughtercardID %d\n",
778 BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami),
779 BCSR_WHOAMI_DCID(whoami));
780
781 /* enable UARTs, YAMON only enables #2 */
782 alchemy_uart_enable(AU1300_UART0_PHYS_ADDR);
783 alchemy_uart_enable(AU1300_UART1_PHYS_ADDR);
784 alchemy_uart_enable(AU1300_UART3_PHYS_ADDR);
785}
diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c
new file mode 100644
index 000000000000..6815d0783cd8
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1550.c
@@ -0,0 +1,498 @@
1/*
2 * Alchemy Db1550 board support
3 *
4 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
5 */
6
7#include <linux/dma-mapping.h>
8#include <linux/gpio.h>
9#include <linux/i2c.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/interrupt.h>
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/nand.h>
15#include <linux/mtd/partitions.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/spi/spi.h>
19#include <linux/spi/flash.h>
20#include <asm/mach-au1x00/au1000.h>
21#include <asm/mach-au1x00/au1xxx_eth.h>
22#include <asm/mach-au1x00/au1xxx_dbdma.h>
23#include <asm/mach-au1x00/au1xxx_psc.h>
24#include <asm/mach-au1x00/au1550_spi.h>
25#include <asm/mach-db1x00/bcsr.h>
26#include <prom.h>
27#include "platform.h"
28
29
30const char *get_system_type(void)
31{
32 return "DB1550";
33}
34
35static void __init db1550_hw_setup(void)
36{
37 void __iomem *base;
38
39 alchemy_gpio_direction_output(203, 0); /* red led on */
40
41 /* complete SPI setup: link psc0_intclk to a 48MHz source,
42 * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
43 */
44 base = (void __iomem *)SYS_CLKSRC;
45 __raw_writel(__raw_readl(base) | 0x000001e0, base);
46 base = (void __iomem *)SYS_PINFUNC;
47 __raw_writel(__raw_readl(base) | 1, base);
48 wmb();
49
50 /* reset the AC97 codec now, the reset time in the psc-ac97 driver
51 * is apparently too short although it's ridiculous as it is.
52 */
53 base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR);
54 __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
55 base + PSC_SEL_OFFSET);
56 __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET);
57 wmb();
58 __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
59 wmb();
60
61 alchemy_gpio_direction_output(202, 0); /* green led on */
62}
63
64void __init board_setup(void)
65{
66 unsigned short whoami;
67
68 bcsr_init(DB1550_BCSR_PHYS_ADDR,
69 DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
70
71 whoami = bcsr_read(BCSR_WHOAMI);
72 printk(KERN_INFO "Alchemy/AMD DB1550 Board, CPLD Rev %d"
73 " Board-ID %d Daughtercard ID %d\n",
74 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
75
76 db1550_hw_setup();
77}
78
79/*****************************************************************************/
80
81static struct mtd_partition db1550_spiflash_parts[] = {
82 {
83 .name = "spi_flash",
84 .offset = 0,
85 .size = MTDPART_SIZ_FULL,
86 },
87};
88
89static struct flash_platform_data db1550_spiflash_data = {
90 .name = "s25fl010",
91 .parts = db1550_spiflash_parts,
92 .nr_parts = ARRAY_SIZE(db1550_spiflash_parts),
93 .type = "m25p10",
94};
95
96static struct spi_board_info db1550_spi_devs[] __initdata = {
97 {
98 /* TI TMP121AIDBVR temp sensor */
99 .modalias = "tmp121",
100 .max_speed_hz = 2400000,
101 .bus_num = 0,
102 .chip_select = 0,
103 .mode = SPI_MODE_0,
104 },
105 {
106 /* Spansion S25FL001D0FMA SPI flash */
107 .modalias = "m25p80",
108 .max_speed_hz = 2400000,
109 .bus_num = 0,
110 .chip_select = 1,
111 .mode = SPI_MODE_0,
112 .platform_data = &db1550_spiflash_data,
113 },
114};
115
116static struct i2c_board_info db1550_i2c_devs[] __initdata = {
117 { I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */
118 { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */
119 { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */
120};
121
122/**********************************************************************/
123
124static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
125 unsigned int ctrl)
126{
127 struct nand_chip *this = mtd->priv;
128 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
129
130 ioaddr &= 0xffffff00;
131
132 if (ctrl & NAND_CLE) {
133 ioaddr += MEM_STNAND_CMD;
134 } else if (ctrl & NAND_ALE) {
135 ioaddr += MEM_STNAND_ADDR;
136 } else {
137 /* assume we want to r/w real data by default */
138 ioaddr += MEM_STNAND_DATA;
139 }
140 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
141 if (cmd != NAND_CMD_NONE) {
142 __raw_writeb(cmd, this->IO_ADDR_W);
143 wmb();
144 }
145}
146
147static int au1550_nand_device_ready(struct mtd_info *mtd)
148{
149 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
150}
151
152static const char *db1550_part_probes[] = { "cmdlinepart", NULL };
153
154static struct mtd_partition db1550_nand_parts[] = {
155 {
156 .name = "NAND FS 0",
157 .offset = 0,
158 .size = 8 * 1024 * 1024,
159 },
160 {
161 .name = "NAND FS 1",
162 .offset = MTDPART_OFS_APPEND,
163 .size = MTDPART_SIZ_FULL
164 },
165};
166
167struct platform_nand_data db1550_nand_platdata = {
168 .chip = {
169 .nr_chips = 1,
170 .chip_offset = 0,
171 .nr_partitions = ARRAY_SIZE(db1550_nand_parts),
172 .partitions = db1550_nand_parts,
173 .chip_delay = 20,
174 .part_probe_types = db1550_part_probes,
175 },
176 .ctrl = {
177 .dev_ready = au1550_nand_device_ready,
178 .cmd_ctrl = au1550_nand_cmd_ctrl,
179 },
180};
181
182static struct resource db1550_nand_res[] = {
183 [0] = {
184 .start = 0x20000000,
185 .end = 0x200000ff,
186 .flags = IORESOURCE_MEM,
187 },
188};
189
190static struct platform_device db1550_nand_dev = {
191 .name = "gen_nand",
192 .num_resources = ARRAY_SIZE(db1550_nand_res),
193 .resource = db1550_nand_res,
194 .id = -1,
195 .dev = {
196 .platform_data = &db1550_nand_platdata,
197 }
198};
199
200/**********************************************************************/
201
202static struct resource au1550_psc0_res[] = {
203 [0] = {
204 .start = AU1550_PSC0_PHYS_ADDR,
205 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
206 .flags = IORESOURCE_MEM,
207 },
208 [1] = {
209 .start = AU1550_PSC0_INT,
210 .end = AU1550_PSC0_INT,
211 .flags = IORESOURCE_IRQ,
212 },
213 [2] = {
214 .start = AU1550_DSCR_CMD0_PSC0_TX,
215 .end = AU1550_DSCR_CMD0_PSC0_TX,
216 .flags = IORESOURCE_DMA,
217 },
218 [3] = {
219 .start = AU1550_DSCR_CMD0_PSC0_RX,
220 .end = AU1550_DSCR_CMD0_PSC0_RX,
221 .flags = IORESOURCE_DMA,
222 },
223};
224
225static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
226{
227 if (cs)
228 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL);
229 else
230 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0);
231}
232
233static struct au1550_spi_info db1550_spi_platdata = {
234 .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */
235 .num_chipselect = 2,
236 .activate_cs = db1550_spi_cs_en,
237};
238
239static u64 spi_dmamask = DMA_BIT_MASK(32);
240
241static struct platform_device db1550_spi_dev = {
242 .dev = {
243 .dma_mask = &spi_dmamask,
244 .coherent_dma_mask = DMA_BIT_MASK(32),
245 .platform_data = &db1550_spi_platdata,
246 },
247 .name = "au1550-spi",
248 .id = 0, /* bus number */
249 .num_resources = ARRAY_SIZE(au1550_psc0_res),
250 .resource = au1550_psc0_res,
251};
252
253/**********************************************************************/
254
255static struct resource au1550_psc1_res[] = {
256 [0] = {
257 .start = AU1550_PSC1_PHYS_ADDR,
258 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
259 .flags = IORESOURCE_MEM,
260 },
261 [1] = {
262 .start = AU1550_PSC1_INT,
263 .end = AU1550_PSC1_INT,
264 .flags = IORESOURCE_IRQ,
265 },
266 [2] = {
267 .start = AU1550_DSCR_CMD0_PSC1_TX,
268 .end = AU1550_DSCR_CMD0_PSC1_TX,
269 .flags = IORESOURCE_DMA,
270 },
271 [3] = {
272 .start = AU1550_DSCR_CMD0_PSC1_RX,
273 .end = AU1550_DSCR_CMD0_PSC1_RX,
274 .flags = IORESOURCE_DMA,
275 },
276};
277
278static struct platform_device db1550_ac97_dev = {
279 .name = "au1xpsc_ac97",
280 .id = 1, /* PSC ID */
281 .num_resources = ARRAY_SIZE(au1550_psc1_res),
282 .resource = au1550_psc1_res,
283};
284
285
286static struct resource au1550_psc2_res[] = {
287 [0] = {
288 .start = AU1550_PSC2_PHYS_ADDR,
289 .end = AU1550_PSC2_PHYS_ADDR + 0xfff,
290 .flags = IORESOURCE_MEM,
291 },
292 [1] = {
293 .start = AU1550_PSC2_INT,
294 .end = AU1550_PSC2_INT,
295 .flags = IORESOURCE_IRQ,
296 },
297 [2] = {
298 .start = AU1550_DSCR_CMD0_PSC2_TX,
299 .end = AU1550_DSCR_CMD0_PSC2_TX,
300 .flags = IORESOURCE_DMA,
301 },
302 [3] = {
303 .start = AU1550_DSCR_CMD0_PSC2_RX,
304 .end = AU1550_DSCR_CMD0_PSC2_RX,
305 .flags = IORESOURCE_DMA,
306 },
307};
308
309static struct platform_device db1550_i2c_dev = {
310 .name = "au1xpsc_smbus",
311 .id = 0, /* bus number */
312 .num_resources = ARRAY_SIZE(au1550_psc2_res),
313 .resource = au1550_psc2_res,
314};
315
316/**********************************************************************/
317
318static struct resource au1550_psc3_res[] = {
319 [0] = {
320 .start = AU1550_PSC3_PHYS_ADDR,
321 .end = AU1550_PSC3_PHYS_ADDR + 0xfff,
322 .flags = IORESOURCE_MEM,
323 },
324 [1] = {
325 .start = AU1550_PSC3_INT,
326 .end = AU1550_PSC3_INT,
327 .flags = IORESOURCE_IRQ,
328 },
329 [2] = {
330 .start = AU1550_DSCR_CMD0_PSC3_TX,
331 .end = AU1550_DSCR_CMD0_PSC3_TX,
332 .flags = IORESOURCE_DMA,
333 },
334 [3] = {
335 .start = AU1550_DSCR_CMD0_PSC3_RX,
336 .end = AU1550_DSCR_CMD0_PSC3_RX,
337 .flags = IORESOURCE_DMA,
338 },
339};
340
341static struct platform_device db1550_i2s_dev = {
342 .name = "au1xpsc_i2s",
343 .id = 3, /* PSC ID */
344 .num_resources = ARRAY_SIZE(au1550_psc3_res),
345 .resource = au1550_psc3_res,
346};
347
348/**********************************************************************/
349
350static struct platform_device db1550_stac_dev = {
351 .name = "ac97-codec",
352 .id = 1, /* on PSC1 */
353};
354
355static struct platform_device db1550_ac97dma_dev = {
356 .name = "au1xpsc-pcm",
357 .id = 1, /* on PSC3 */
358};
359
360static struct platform_device db1550_i2sdma_dev = {
361 .name = "au1xpsc-pcm",
362 .id = 3, /* on PSC3 */
363};
364
365static struct platform_device db1550_sndac97_dev = {
366 .name = "db1550-ac97",
367};
368
369static struct platform_device db1550_sndi2s_dev = {
370 .name = "db1550-i2s",
371};
372
373/**********************************************************************/
374
375static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
376{
377 if ((slot < 11) || (slot > 13) || pin == 0)
378 return -1;
379 if (slot == 11)
380 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
381 if (slot == 12) {
382 switch (pin) {
383 case 1: return AU1550_PCI_INTB;
384 case 2: return AU1550_PCI_INTC;
385 case 3: return AU1550_PCI_INTD;
386 case 4: return AU1550_PCI_INTA;
387 }
388 }
389 if (slot == 13) {
390 switch (pin) {
391 case 1: return AU1550_PCI_INTA;
392 case 2: return AU1550_PCI_INTB;
393 case 3: return AU1550_PCI_INTC;
394 case 4: return AU1550_PCI_INTD;
395 }
396 }
397 return -1;
398}
399
400static struct resource alchemy_pci_host_res[] = {
401 [0] = {
402 .start = AU1500_PCI_PHYS_ADDR,
403 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
404 .flags = IORESOURCE_MEM,
405 },
406};
407
408static struct alchemy_pci_platdata db1550_pci_pd = {
409 .board_map_irq = db1550_map_pci_irq,
410};
411
412static struct platform_device db1550_pci_host_dev = {
413 .dev.platform_data = &db1550_pci_pd,
414 .name = "alchemy-pci",
415 .id = 0,
416 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
417 .resource = alchemy_pci_host_res,
418};
419
420/**********************************************************************/
421
422static struct platform_device *db1550_devs[] __initdata = {
423 &db1550_nand_dev,
424 &db1550_i2c_dev,
425 &db1550_ac97_dev,
426 &db1550_spi_dev,
427 &db1550_i2s_dev,
428 &db1550_stac_dev,
429 &db1550_ac97dma_dev,
430 &db1550_i2sdma_dev,
431 &db1550_sndac97_dev,
432 &db1550_sndi2s_dev,
433};
434
435/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
436static int __init db1550_pci_init(void)
437{
438 return platform_device_register(&db1550_pci_host_dev);
439}
440arch_initcall(db1550_pci_init);
441
442static int __init db1550_dev_init(void)
443{
444 int swapped;
445
446 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */
447 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */
448 irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */
449 irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */
450 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
451 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
452
453 i2c_register_board_info(0, db1550_i2c_devs,
454 ARRAY_SIZE(db1550_i2c_devs));
455 spi_register_board_info(db1550_spi_devs,
456 ARRAY_SIZE(db1550_i2c_devs));
457
458 /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
459 __raw_writel(PSC_SEL_CLK_SERCLK,
460 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
461 wmb();
462 __raw_writel(PSC_SEL_CLK_SERCLK,
463 (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
464 wmb();
465 /* SPI/I2C use internally supplied 50MHz source */
466 __raw_writel(PSC_SEL_CLK_INTCLK,
467 (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET);
468 wmb();
469 __raw_writel(PSC_SEL_CLK_INTCLK,
470 (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
471 wmb();
472
473 db1x_register_pcmcia_socket(
474 AU1000_PCMCIA_ATTR_PHYS_ADDR,
475 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
476 AU1000_PCMCIA_MEM_PHYS_ADDR,
477 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
478 AU1000_PCMCIA_IO_PHYS_ADDR,
479 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
480 AU1550_GPIO3_INT, AU1550_GPIO0_INT,
481 /*AU1550_GPIO21_INT*/0, 0, 0);
482
483 db1x_register_pcmcia_socket(
484 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
485 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
486 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
487 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
488 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
489 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
490 AU1550_GPIO5_INT, AU1550_GPIO1_INT,
491 /*AU1550_GPIO22_INT*/0, 0, 1);
492
493 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
494 db1x_register_norflash(128 << 20, 4, swapped);
495
496 return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));
497}
498device_initcall(db1550_dev_init);
diff --git a/arch/mips/alchemy/devboards/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile
deleted file mode 100644
index 613c0c0c8be9..000000000000
--- a/arch/mips/alchemy/devboards/db1x00/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2000, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor DBAu1xx0 boards.
6#
7
8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
deleted file mode 100644
index 7cd36e631f6c..000000000000
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ /dev/null
@@ -1,229 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Db1x00 board setup.
5 *
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/gpio.h>
31#include <linux/init.h>
32#include <linux/interrupt.h>
33#include <linux/pm.h>
34
35#include <asm/mach-au1x00/au1000.h>
36#include <asm/mach-au1x00/au1xxx_eth.h>
37#include <asm/mach-db1x00/db1x00.h>
38#include <asm/mach-db1x00/bcsr.h>
39#include <asm/reboot.h>
40
41#include <prom.h>
42
43#ifdef CONFIG_MIPS_BOSPORUS
44char irq_tab_alchemy[][5] __initdata = {
45 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
46 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */
47 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
48};
49
50/*
51 * Micrel/Kendin 5 port switch attached to MAC0,
52 * MAC0 is associated with PHY address 5 (== WAN port)
53 * MAC1 is not associated with any PHY, since it's connected directly
54 * to the switch.
55 * no interrupts are used
56 */
57static struct au1000_eth_platform_data eth0_pdata = {
58 .phy_static_config = 1,
59 .phy_addr = 5,
60};
61
62static void bosporus_power_off(void)
63{
64 while (1)
65 asm volatile (".set mips3 ; wait ; .set mips0");
66}
67
68const char *get_system_type(void)
69{
70 return "Alchemy Bosporus Gateway Reference";
71}
72#endif
73
74
75#ifdef CONFIG_MIPS_MIRAGE
76static void mirage_power_off(void)
77{
78 alchemy_gpio_direction_output(210, 1);
79}
80
81const char *get_system_type(void)
82{
83 return "Alchemy Mirage";
84}
85#endif
86
87
88#if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
89static void mips_softreset(void)
90{
91 asm volatile ("jr\t%0" : : "r"(0xbfc00000));
92}
93
94#else
95
96const char *get_system_type(void)
97{
98 return "Alchemy Db1x00";
99}
100#endif
101
102
103void __init board_setup(void)
104{
105 unsigned long bcsr1, bcsr2;
106
107 bcsr1 = DB1000_BCSR_PHYS_ADDR;
108 bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
109
110#ifdef CONFIG_MIPS_DB1000
111 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
112#endif
113#ifdef CONFIG_MIPS_DB1500
114 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
115#endif
116#ifdef CONFIG_MIPS_DB1100
117 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
118#endif
119#ifdef CONFIG_MIPS_BOSPORUS
120 au1xxx_override_eth_cfg(0, &eth0_pdata);
121
122 printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
123#endif
124#ifdef CONFIG_MIPS_MIRAGE
125 printk(KERN_INFO "AMD Alchemy Mirage Board\n");
126#endif
127#ifdef CONFIG_MIPS_DB1550
128 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
129
130 bcsr1 = DB1550_BCSR_PHYS_ADDR;
131 bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
132#endif
133
134 /* initialize board register space */
135 bcsr_init(bcsr1, bcsr2);
136
137#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR)
138 {
139 u32 pin_func;
140
141 /* Set IRFIRSEL instead of GPIO15 */
142 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
143 au_writel(pin_func, SYS_PINFUNC);
144 /* Power off until the driver is in use */
145 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
146 BCSR_RESETS_IRDA_MODE_OFF);
147 }
148#endif
149 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
150
151 /* Enable GPIO[31:0] inputs */
152 alchemy_gpio1_input_enable();
153
154#ifdef CONFIG_MIPS_MIRAGE
155 {
156 u32 pin_func;
157
158 /* GPIO[20] is output */
159 alchemy_gpio_direction_output(20, 0);
160
161 /* Set GPIO[210:208] instead of SSI_0 */
162 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
163
164 /* Set GPIO[215:211] for LEDs */
165 pin_func |= 5 << 2;
166
167 /* Set GPIO[214:213] for more LEDs */
168 pin_func |= 5 << 12;
169
170 /* Set GPIO[207:200] instead of PCMCIA/LCD */
171 pin_func |= SYS_PF_LCD | SYS_PF_PC;
172 au_writel(pin_func, SYS_PINFUNC);
173
174 /*
175 * Enable speaker amplifier. This should
176 * be part of the audio driver.
177 */
178 alchemy_gpio_direction_output(209, 1);
179
180 pm_power_off = mirage_power_off;
181 _machine_halt = mirage_power_off;
182 _machine_restart = (void(*)(char *))mips_softreset;
183 }
184#endif
185
186#ifdef CONFIG_MIPS_BOSPORUS
187 pm_power_off = bosporus_power_off;
188 _machine_halt = bosporus_power_off;
189 _machine_restart = (void(*)(char *))mips_softreset;
190#endif
191 au_sync();
192}
193
194static int __init db1x00_init_irq(void)
195{
196#if defined(CONFIG_MIPS_MIRAGE)
197 irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
198#elif defined(CONFIG_MIPS_DB1550)
199 irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
200 irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
201 irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
202 irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
203 irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
204 irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
205#elif defined(CONFIG_MIPS_DB1500)
206 irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
207 irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
208 irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
209 irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
210 irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
211 irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
212#elif defined(CONFIG_MIPS_DB1100)
213 irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
214 irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
215 irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
216 irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
217 irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
218 irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
219#elif defined(CONFIG_MIPS_DB1000)
220 irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
221 irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
222 irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
223 irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
224 irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
225 irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
226#endif
227 return 0;
228}
229arch_initcall(db1x00_init_irq);
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
deleted file mode 100644
index 9e6b3d442acd..000000000000
--- a/arch/mips/alchemy/devboards/db1x00/platform.c
+++ /dev/null
@@ -1,316 +0,0 @@
1/*
2 * DBAu1xxx board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/dma-mapping.h>
24#include <linux/platform_device.h>
25
26#include <asm/mach-au1x00/au1000.h>
27#include <asm/mach-au1x00/au1000_dma.h>
28#include <asm/mach-db1x00/bcsr.h>
29#include "../platform.h"
30
31struct pci_dev;
32
33/* DB1xxx PCMCIA interrupt sources:
34 * CD0/1 GPIO0/3
35 * STSCHG0/1 GPIO1/4
36 * CARD0/1 GPIO2/5
37 * Db1550: 0/1, 21/22, 3/5
38 */
39
40#define DB1XXX_HAS_PCMCIA
41#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
42
43#if defined(CONFIG_MIPS_DB1000)
44#define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT
45#define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO1_INT
46#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO2_INT
47#define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT
48#define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT
49#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT
50#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
51#define BOARD_FLASH_WIDTH 4 /* 32-bits */
52#elif defined(CONFIG_MIPS_DB1100)
53#define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT
54#define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT
55#define DB1XXX_PCMCIA_CARD0 AU1100_GPIO2_INT
56#define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT
57#define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT
58#define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT
59#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
60#define BOARD_FLASH_WIDTH 4 /* 32-bits */
61#elif defined(CONFIG_MIPS_DB1500)
62#define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT
63#define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT
64#define DB1XXX_PCMCIA_CARD0 AU1500_GPIO2_INT
65#define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT
66#define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT
67#define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT
68#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
69#define BOARD_FLASH_WIDTH 4 /* 32-bits */
70#elif defined(CONFIG_MIPS_DB1550)
71#define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT
72#define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT
73#define DB1XXX_PCMCIA_CARD0 AU1550_GPIO3_INT
74#define DB1XXX_PCMCIA_CD1 AU1550_GPIO1_INT
75#define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT
76#define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT
77#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
78#define BOARD_FLASH_WIDTH 4 /* 32-bits */
79#else
80/* other board: no PCMCIA */
81#undef DB1XXX_HAS_PCMCIA
82#undef F_SWAPPED
83#define F_SWAPPED 0
84#if defined(CONFIG_MIPS_BOSPORUS)
85#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */
86#define BOARD_FLASH_WIDTH 2 /* 16-bits */
87#elif defined(CONFIG_MIPS_MIRAGE)
88#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
89#define BOARD_FLASH_WIDTH 4 /* 32-bits */
90#endif
91#endif
92
93#ifdef CONFIG_PCI
94#ifdef CONFIG_MIPS_DB1500
95static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
96{
97 if ((slot < 12) || (slot > 13) || pin == 0)
98 return -1;
99 if (slot == 12)
100 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
101 if (slot == 13) {
102 switch (pin) {
103 case 1: return AU1500_PCI_INTA;
104 case 2: return AU1500_PCI_INTB;
105 case 3: return AU1500_PCI_INTC;
106 case 4: return AU1500_PCI_INTD;
107 }
108 }
109 return -1;
110}
111#endif
112
113#ifdef CONFIG_MIPS_DB1550
114static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
115{
116 if ((slot < 11) || (slot > 13) || pin == 0)
117 return -1;
118 if (slot == 11)
119 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
120 if (slot == 12) {
121 switch (pin) {
122 case 1: return AU1550_PCI_INTB;
123 case 2: return AU1550_PCI_INTC;
124 case 3: return AU1550_PCI_INTD;
125 case 4: return AU1550_PCI_INTA;
126 }
127 }
128 if (slot == 13) {
129 switch (pin) {
130 case 1: return AU1550_PCI_INTA;
131 case 2: return AU1550_PCI_INTB;
132 case 3: return AU1550_PCI_INTC;
133 case 4: return AU1550_PCI_INTD;
134 }
135 }
136 return -1;
137}
138#endif
139
140#ifdef CONFIG_MIPS_BOSPORUS
141static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
142{
143 if ((slot < 11) || (slot > 13) || pin == 0)
144 return -1;
145 if (slot == 12)
146 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
147 if (slot == 11) {
148 switch (pin) {
149 case 1: return AU1500_PCI_INTA;
150 case 2: return AU1500_PCI_INTB;
151 default: return 0xff;
152 }
153 }
154 if (slot == 13) {
155 switch (pin) {
156 case 1: return AU1500_PCI_INTA;
157 case 2: return AU1500_PCI_INTB;
158 case 3: return AU1500_PCI_INTC;
159 case 4: return AU1500_PCI_INTD;
160 }
161 }
162 return -1;
163}
164#endif
165
166#ifdef CONFIG_MIPS_MIRAGE
167static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
168{
169 if ((slot < 11) || (slot > 13) || pin == 0)
170 return -1;
171 if (slot == 11)
172 return (pin == 1) ? AU1500_PCI_INTD : 0xff;
173 if (slot == 12)
174 return (pin == 3) ? AU1500_PCI_INTC : 0xff;
175 if (slot == 13) {
176 switch (pin) {
177 case 1: return AU1500_PCI_INTA;
178 case 2: return AU1500_PCI_INTB;
179 default: return 0xff;
180 }
181 }
182 return -1;
183}
184#endif
185
186static struct resource alchemy_pci_host_res[] = {
187 [0] = {
188 .start = AU1500_PCI_PHYS_ADDR,
189 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
190 .flags = IORESOURCE_MEM,
191 },
192};
193
194static struct alchemy_pci_platdata db1xxx_pci_pd = {
195 .board_map_irq = db1xxx_map_pci_irq,
196};
197
198static struct platform_device db1xxx_pci_host_dev = {
199 .dev.platform_data = &db1xxx_pci_pd,
200 .name = "alchemy-pci",
201 .id = 0,
202 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
203 .resource = alchemy_pci_host_res,
204};
205
206static int __init db15x0_pci_init(void)
207{
208 return platform_device_register(&db1xxx_pci_host_dev);
209}
210/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
211arch_initcall(db15x0_pci_init);
212#endif
213
214#ifdef CONFIG_MIPS_DB1100
215static struct resource au1100_lcd_resources[] = {
216 [0] = {
217 .start = AU1100_LCD_PHYS_ADDR,
218 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 [1] = {
222 .start = AU1100_LCD_INT,
223 .end = AU1100_LCD_INT,
224 .flags = IORESOURCE_IRQ,
225 }
226};
227
228static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
229
230static struct platform_device au1100_lcd_device = {
231 .name = "au1100-lcd",
232 .id = 0,
233 .dev = {
234 .dma_mask = &au1100_lcd_dmamask,
235 .coherent_dma_mask = DMA_BIT_MASK(32),
236 },
237 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
238 .resource = au1100_lcd_resources,
239};
240#endif
241
242static struct resource alchemy_ac97c_res[] = {
243 [0] = {
244 .start = AU1000_AC97_PHYS_ADDR,
245 .end = AU1000_AC97_PHYS_ADDR + 0xfff,
246 .flags = IORESOURCE_MEM,
247 },
248 [1] = {
249 .start = DMA_ID_AC97C_TX,
250 .end = DMA_ID_AC97C_TX,
251 .flags = IORESOURCE_DMA,
252 },
253 [2] = {
254 .start = DMA_ID_AC97C_RX,
255 .end = DMA_ID_AC97C_RX,
256 .flags = IORESOURCE_DMA,
257 },
258};
259
260static struct platform_device alchemy_ac97c_dev = {
261 .name = "alchemy-ac97c",
262 .id = -1,
263 .resource = alchemy_ac97c_res,
264 .num_resources = ARRAY_SIZE(alchemy_ac97c_res),
265};
266
267static struct platform_device alchemy_ac97c_dma_dev = {
268 .name = "alchemy-pcm-dma",
269 .id = 0,
270};
271
272static struct platform_device db1x00_codec_dev = {
273 .name = "ac97-codec",
274 .id = -1,
275};
276
277static struct platform_device db1x00_audio_dev = {
278 .name = "db1000-audio",
279};
280
281static int __init db1xxx_dev_init(void)
282{
283#ifdef DB1XXX_HAS_PCMCIA
284 db1x_register_pcmcia_socket(
285 AU1000_PCMCIA_ATTR_PHYS_ADDR,
286 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
287 AU1000_PCMCIA_MEM_PHYS_ADDR,
288 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
289 AU1000_PCMCIA_IO_PHYS_ADDR,
290 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
291 DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0,
292 /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0);
293
294 db1x_register_pcmcia_socket(
295 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
296 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
297 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
298 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
299 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
300 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
301 DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1,
302 /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1);
303#endif
304#ifdef CONFIG_MIPS_DB1100
305 platform_device_register(&au1100_lcd_device);
306#endif
307 db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
308
309 platform_device_register(&db1x00_codec_dev);
310 platform_device_register(&alchemy_ac97c_dma_dev);
311 platform_device_register(&alchemy_ac97c_dev);
312 platform_device_register(&db1x00_audio_dev);
313
314 return 0;
315}
316device_initcall(db1xxx_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1000/Makefile b/arch/mips/alchemy/devboards/pb1000/Makefile
deleted file mode 100644
index 97c6615ba2bb..000000000000
--- a/arch/mips/alchemy/devboards/pb1000/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2000, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1000 board.
6#
7
8obj-y := board_setup.o
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
deleted file mode 100644
index e64fdcbf75d0..000000000000
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ /dev/null
@@ -1,209 +0,0 @@
1/*
2 * Copyright 2000, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/delay.h>
27#include <linux/gpio.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/pm.h>
31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-pb1x00/pb1000.h>
33#include <asm/reboot.h>
34#include <prom.h>
35
36#include "../platform.h"
37
38const char *get_system_type(void)
39{
40 return "Alchemy Pb1000";
41}
42
43static void board_reset(char *c)
44{
45 asm volatile ("jr %0" : : "r" (0xbfc00000));
46}
47
48static void board_power_off(void)
49{
50 while (1)
51 asm volatile (
52 " .set mips32 \n"
53 " wait \n"
54 " .set mips0 \n");
55}
56
57void __init board_setup(void)
58{
59 u32 pin_func, static_cfg0;
60 u32 sys_freqctrl, sys_clksrc;
61 u32 prid = read_c0_prid();
62
63 sys_freqctrl = 0;
64 sys_clksrc = 0;
65
66 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
67 au_writel(8, SYS_AUXPLL);
68 alchemy_gpio1_input_enable();
69 udelay(100);
70
71#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
72 /* Zero and disable FREQ2 */
73 sys_freqctrl = au_readl(SYS_FREQCTRL0);
74 sys_freqctrl &= ~0xFFF00000;
75 au_writel(sys_freqctrl, SYS_FREQCTRL0);
76
77 /* Zero and disable USBH/USBD clocks */
78 sys_clksrc = au_readl(SYS_CLKSRC);
79 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
80 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
81 au_writel(sys_clksrc, SYS_CLKSRC);
82
83 sys_freqctrl = au_readl(SYS_FREQCTRL0);
84 sys_freqctrl &= ~0xFFF00000;
85
86 sys_clksrc = au_readl(SYS_CLKSRC);
87 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
88 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
89
90 switch (prid & 0x000000FF) {
91 case 0x00: /* DA */
92 case 0x01: /* HA */
93 case 0x02: /* HB */
94 /* CPU core freq to 48 MHz to slow it way down... */
95 au_writel(4, SYS_CPUPLL);
96
97 /*
98 * Setup 48 MHz FREQ2 from CPUPLL for USB Host
99 * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
100 */
101 sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
102 au_writel(sys_freqctrl, SYS_FREQCTRL0);
103
104 /* CPU core freq to 384 MHz */
105 au_writel(0x20, SYS_CPUPLL);
106
107 printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
108 break;
109
110 default: /* HC and newer */
111 /* FREQ2 = aux / 2 = 48 MHz */
112 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
113 SYS_FC_FE2 | SYS_FC_FS2;
114 au_writel(sys_freqctrl, SYS_FREQCTRL0);
115 break;
116 }
117
118 /*
119 * Route 48 MHz FREQ2 into USB Host and/or Device
120 */
121 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
122 au_writel(sys_clksrc, SYS_CLKSRC);
123
124 /* Configure pins GPIO[14:9] as GPIO */
125 pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
126
127 /* 2nd USB port is USB host */
128 pin_func |= SYS_PF_USB;
129
130 au_writel(pin_func, SYS_PINFUNC);
131
132 alchemy_gpio_direction_input(11);
133 alchemy_gpio_direction_input(13);
134 alchemy_gpio_direction_output(4, 0);
135 alchemy_gpio_direction_output(5, 0);
136#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
137
138 /* Make GPIO 15 an input (for interrupt line) */
139 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
140 /* We don't need I2S, so make it available for GPIO[31:29] */
141 pin_func |= SYS_PF_I2S;
142 au_writel(pin_func, SYS_PINFUNC);
143
144 alchemy_gpio_direction_input(15);
145
146 static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
147 au_writel(static_cfg0, MEM_STCFG0);
148
149 /* configure RCE2* for LCD */
150 au_writel(0x00000004, MEM_STCFG2);
151
152 /* MEM_STTIME2 */
153 au_writel(0x09000000, MEM_STTIME2);
154
155 /* Set 32-bit base address decoding for RCE2* */
156 au_writel(0x10003ff0, MEM_STADDR2);
157
158 /*
159 * PCI CPLD setup
160 * Expand CE0 to cover PCI
161 */
162 au_writel(0x11803e40, MEM_STADDR1);
163
164 /* Burst visibility on */
165 au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
166
167 au_writel(0x83, MEM_STCFG1); /* ewait enabled, flash timing */
168 au_writel(0x33030a10, MEM_STTIME1); /* slower timing for FPGA */
169
170 /* Setup the static bus controller */
171 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
172 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
173 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
174
175 /*
176 * Enable Au1000 BCLK switching - note: sed1356 must not use
177 * its BCLK (Au1000 LCLK) for any timings
178 */
179 switch (prid & 0x000000FF) {
180 case 0x00: /* DA */
181 case 0x01: /* HA */
182 case 0x02: /* HB */
183 break;
184 default: /* HC and newer */
185 /*
186 * Enable sys bus clock divider when IDLE state or no bus
187 * activity.
188 */
189 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
190 break;
191 }
192
193 pm_power_off = board_power_off;
194 _machine_halt = board_power_off;
195 _machine_restart = board_reset;
196}
197
198static int __init pb1000_init_irq(void)
199{
200 irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
201 return 0;
202}
203arch_initcall(pb1000_init_irq);
204
205static int __init pb1000_device_init(void)
206{
207 return db1x_register_norflash(8 * 1024 * 1024, 4, 0);
208}
209device_initcall(pb1000_device_init);
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100.c
index d108fd573aaf..cff50d05ddd4 100644
--- a/arch/mips/alchemy/devboards/pb1100/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1100.c
@@ -1,42 +1,37 @@
1/* 1/*
2 * Copyright 2002, 2008 MontaVista Software Inc. 2 * Pb1100 board platform device registration
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 * 3 *
5 * This program is free software; you can redistribute it and/or modify it 4 * Copyright (C) 2009 Manuel Lauss
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 * 5 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 6 * This program is free software; you can redistribute it and/or modify
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 7 * it under the terms of the GNU General Public License as published by
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 8 * the Free Software Foundation; either version 2 of the License, or
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 9 * (at your option) any later version.
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 * 10 *
21 * You should have received a copy of the GNU General Public License along 11 * This program is distributed in the hope that it will be useful,
22 * with this program; if not, write to the Free Software Foundation, Inc., 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * 675 Mass Ave, Cambridge, MA 02139, USA. 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 */ 19 */
25 20
21#include <linux/delay.h>
26#include <linux/gpio.h> 22#include <linux/gpio.h>
27#include <linux/init.h> 23#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h> 24#include <linux/interrupt.h>
30 25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
31#include <asm/mach-au1x00/au1000.h> 27#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-db1x00/bcsr.h> 28#include <asm/mach-db1x00/bcsr.h>
33
34#include <prom.h> 29#include <prom.h>
35 30#include "platform.h"
36 31
37const char *get_system_type(void) 32const char *get_system_type(void)
38{ 33{
39 return "Alchemy Pb1100"; 34 return "PB1100";
40} 35}
41 36
42void __init board_setup(void) 37void __init board_setup(void)
@@ -115,13 +110,58 @@ void __init board_setup(void)
115 } 110 }
116} 111}
117 112
118static int __init pb1100_init_irq(void) 113/******************************************************************************/
114
115static struct resource au1100_lcd_resources[] = {
116 [0] = {
117 .start = AU1100_LCD_PHYS_ADDR,
118 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
119 .flags = IORESOURCE_MEM,
120 },
121 [1] = {
122 .start = AU1100_LCD_INT,
123 .end = AU1100_LCD_INT,
124 .flags = IORESOURCE_IRQ,
125 }
126};
127
128static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
129
130static struct platform_device au1100_lcd_device = {
131 .name = "au1100-lcd",
132 .id = 0,
133 .dev = {
134 .dma_mask = &au1100_lcd_dmamask,
135 .coherent_dma_mask = DMA_BIT_MASK(32),
136 },
137 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
138 .resource = au1100_lcd_resources,
139};
140
141static int __init pb1100_dev_init(void)
119{ 142{
143 int swapped;
144
120 irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */ 145 irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
121 irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */ 146 irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
122 irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */ 147 irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
123 irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */ 148 irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
124 149
150 /* PCMCIA. single socket, identical to Pb1500 */
151 db1x_register_pcmcia_socket(
152 AU1000_PCMCIA_ATTR_PHYS_ADDR,
153 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
154 AU1000_PCMCIA_MEM_PHYS_ADDR,
155 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
156 AU1000_PCMCIA_IO_PHYS_ADDR,
157 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
158 AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */
159 /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
160
161 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
162 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
163 platform_device_register(&au1100_lcd_device);
164
125 return 0; 165 return 0;
126} 166}
127arch_initcall(pb1100_init_irq); 167device_initcall(pb1100_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile
deleted file mode 100644
index 7e3756c83fe5..000000000000
--- a/arch/mips/alchemy/devboards/pb1100/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2000, 2001, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1100 board.
6#
7
8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c
deleted file mode 100644
index 9c57c01a68c4..000000000000
--- a/arch/mips/alchemy/devboards/pb1100/platform.c
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * Pb1100 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/dma-mapping.h>
23#include <linux/platform_device.h>
24
25#include <asm/mach-au1x00/au1000.h>
26#include <asm/mach-db1x00/bcsr.h>
27
28#include "../platform.h"
29
30static struct resource au1100_lcd_resources[] = {
31 [0] = {
32 .start = AU1100_LCD_PHYS_ADDR,
33 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
34 .flags = IORESOURCE_MEM,
35 },
36 [1] = {
37 .start = AU1100_LCD_INT,
38 .end = AU1100_LCD_INT,
39 .flags = IORESOURCE_IRQ,
40 }
41};
42
43static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
44
45static struct platform_device au1100_lcd_device = {
46 .name = "au1100-lcd",
47 .id = 0,
48 .dev = {
49 .dma_mask = &au1100_lcd_dmamask,
50 .coherent_dma_mask = DMA_BIT_MASK(32),
51 },
52 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
53 .resource = au1100_lcd_resources,
54};
55
56static int __init pb1100_dev_init(void)
57{
58 int swapped;
59
60 /* PCMCIA. single socket, identical to Pb1500 */
61 db1x_register_pcmcia_socket(
62 AU1000_PCMCIA_ATTR_PHYS_ADDR,
63 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
64 AU1000_PCMCIA_MEM_PHYS_ADDR,
65 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
66 AU1000_PCMCIA_IO_PHYS_ADDR,
67 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
68 AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */
69 /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
70
71 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
72 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
73 platform_device_register(&au1100_lcd_device);
74
75 return 0;
76}
77device_initcall(pb1100_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile
deleted file mode 100644
index 18c1bd53e4c0..000000000000
--- a/arch/mips/alchemy/devboards/pb1200/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1#
2# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards.
3#
4
5obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
deleted file mode 100644
index 6d06b07c2381..000000000000
--- a/arch/mips/alchemy/devboards/pb1200/board_setup.c
+++ /dev/null
@@ -1,174 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1200/Db1200 board setup.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/sched.h>
30
31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-db1x00/bcsr.h>
33
34#ifdef CONFIG_MIPS_PB1200
35#include <asm/mach-pb1x00/pb1200.h>
36#endif
37
38#ifdef CONFIG_MIPS_DB1200
39#include <asm/mach-db1x00/db1200.h>
40#define PB1200_INT_BEGIN DB1200_INT_BEGIN
41#define PB1200_INT_END DB1200_INT_END
42#endif
43
44#include <prom.h>
45
46const char *get_system_type(void)
47{
48 return "Alchemy Pb1200";
49}
50
51void __init board_setup(void)
52{
53 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
54 bcsr_init(PB1200_BCSR_PHYS_ADDR,
55 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
56
57#if 0
58 {
59 u32 pin_func;
60
61 /*
62 * Enable PSC1 SYNC for AC97. Normaly done in audio driver,
63 * but it is board specific code, so put it here.
64 */
65 pin_func = au_readl(SYS_PINFUNC);
66 au_sync();
67 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
68 au_writel(pin_func, SYS_PINFUNC);
69
70 au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
71 au_sync();
72 }
73#endif
74
75#if defined(CONFIG_I2C_AU1550)
76 {
77 u32 freq0, clksrc;
78 u32 pin_func;
79
80 /* Select SMBus in CPLD */
81 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
82
83 pin_func = au_readl(SYS_PINFUNC);
84 au_sync();
85 pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
86 /* Set GPIOs correctly */
87 pin_func |= 2 << 17;
88 au_writel(pin_func, SYS_PINFUNC);
89 au_sync();
90
91 /* The I2C driver depends on 50 MHz clock */
92 freq0 = au_readl(SYS_FREQCTRL0);
93 au_sync();
94 freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
95 freq0 |= 3 << SYS_FC_FRDIV1_BIT;
96 /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */
97 au_writel(freq0, SYS_FREQCTRL0);
98 au_sync();
99 freq0 |= SYS_FC_FE1;
100 au_writel(freq0, SYS_FREQCTRL0);
101 au_sync();
102
103 clksrc = au_readl(SYS_CLKSRC);
104 au_sync();
105 clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK);
106 /* Bit 22 is EXTCLK0 for PSC0 */
107 clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT;
108 au_writel(clksrc, SYS_CLKSRC);
109 au_sync();
110 }
111#endif
112
113 /*
114 * The Pb1200 development board uses external MUX for PSC0 to
115 * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI
116 */
117#ifdef CONFIG_I2C_AU1550
118 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
119#endif
120 au_sync();
121}
122
123static int __init pb1200_init_irq(void)
124{
125 /* We have a problem with CPLD rev 3. */
126 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
127 printk(KERN_ERR "WARNING!!!\n");
128 printk(KERN_ERR "WARNING!!!\n");
129 printk(KERN_ERR "WARNING!!!\n");
130 printk(KERN_ERR "WARNING!!!\n");
131 printk(KERN_ERR "WARNING!!!\n");
132 printk(KERN_ERR "WARNING!!!\n");
133 printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
134 printk(KERN_ERR "updated to latest revision. This software will\n");
135 printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
136 printk(KERN_ERR "WARNING!!!\n");
137 printk(KERN_ERR "WARNING!!!\n");
138 printk(KERN_ERR "WARNING!!!\n");
139 printk(KERN_ERR "WARNING!!!\n");
140 printk(KERN_ERR "WARNING!!!\n");
141 printk(KERN_ERR "WARNING!!!\n");
142 panic("Game over. Your score is 0.");
143 }
144
145 irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
146 bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
147
148 return 0;
149}
150arch_initcall(pb1200_init_irq);
151
152
153int board_au1200fb_panel(void)
154{
155 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
156}
157
158int board_au1200fb_panel_init(void)
159{
160 /* Apply power */
161 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
162 BCSR_BOARD_LCDBL);
163 /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
164 return 0;
165}
166
167int board_au1200fb_panel_shutdown(void)
168{
169 /* Remove power */
170 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
171 BCSR_BOARD_LCDBL, 0);
172 /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
173 return 0;
174}
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
deleted file mode 100644
index 54f7f7b0676e..000000000000
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ /dev/null
@@ -1,339 +0,0 @@
1/*
2 * Pb1200/DBAu1200 board platform device registration
3 *
4 * Copyright (C) 2008 MontaVista Software Inc. <source@mvista.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/init.h>
23#include <linux/leds.h>
24#include <linux/platform_device.h>
25#include <linux/smc91x.h>
26
27#include <asm/mach-au1x00/au1000.h>
28#include <asm/mach-au1x00/au1100_mmc.h>
29#include <asm/mach-au1x00/au1xxx_dbdma.h>
30#include <asm/mach-db1x00/bcsr.h>
31#include <asm/mach-pb1x00/pb1200.h>
32
33#include "../platform.h"
34
35static int mmc_activity;
36
37static void pb1200mmc0_set_power(void *mmc_host, int state)
38{
39 if (state)
40 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
41 else
42 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
43
44 msleep(1);
45}
46
47static int pb1200mmc0_card_readonly(void *mmc_host)
48{
49 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
50}
51
52static int pb1200mmc0_card_inserted(void *mmc_host)
53{
54 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
55}
56
57static void pb1200_mmcled_set(struct led_classdev *led,
58 enum led_brightness brightness)
59{
60 if (brightness != LED_OFF) {
61 if (++mmc_activity == 1)
62 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
63 } else {
64 if (--mmc_activity == 0)
65 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
66 }
67}
68
69static struct led_classdev pb1200mmc_led = {
70 .brightness_set = pb1200_mmcled_set,
71};
72
73static void pb1200mmc1_set_power(void *mmc_host, int state)
74{
75 if (state)
76 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
77 else
78 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
79
80 msleep(1);
81}
82
83static int pb1200mmc1_card_readonly(void *mmc_host)
84{
85 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
86}
87
88static int pb1200mmc1_card_inserted(void *mmc_host)
89{
90 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
91}
92
93static struct au1xmmc_platform_data pb1200mmc_platdata[2] = {
94 [0] = {
95 .set_power = pb1200mmc0_set_power,
96 .card_inserted = pb1200mmc0_card_inserted,
97 .card_readonly = pb1200mmc0_card_readonly,
98 .cd_setup = NULL, /* use poll-timer in driver */
99 .led = &pb1200mmc_led,
100 },
101 [1] = {
102 .set_power = pb1200mmc1_set_power,
103 .card_inserted = pb1200mmc1_card_inserted,
104 .card_readonly = pb1200mmc1_card_readonly,
105 .cd_setup = NULL, /* use poll-timer in driver */
106 .led = &pb1200mmc_led,
107 },
108};
109
110static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
111
112static struct resource au1200_mmc0_res[] = {
113 [0] = {
114 .start = AU1100_SD0_PHYS_ADDR,
115 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
116 .flags = IORESOURCE_MEM,
117 },
118 [1] = {
119 .start = AU1200_SD_INT,
120 .end = AU1200_SD_INT,
121 .flags = IORESOURCE_IRQ,
122 },
123 [2] = {
124 .start = AU1200_DSCR_CMD0_SDMS_TX0,
125 .end = AU1200_DSCR_CMD0_SDMS_TX0,
126 .flags = IORESOURCE_DMA,
127 },
128 [3] = {
129 .start = AU1200_DSCR_CMD0_SDMS_RX0,
130 .end = AU1200_DSCR_CMD0_SDMS_RX0,
131 .flags = IORESOURCE_DMA,
132 }
133};
134
135static struct platform_device pb1200_mmc0_dev = {
136 .name = "au1xxx-mmc",
137 .id = 0,
138 .dev = {
139 .dma_mask = &au1xxx_mmc_dmamask,
140 .coherent_dma_mask = DMA_BIT_MASK(32),
141 .platform_data = &pb1200mmc_platdata[0],
142 },
143 .num_resources = ARRAY_SIZE(au1200_mmc0_res),
144 .resource = au1200_mmc0_res,
145};
146
147static struct resource au1200_mmc1_res[] = {
148 [0] = {
149 .start = AU1100_SD1_PHYS_ADDR,
150 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
151 .flags = IORESOURCE_MEM,
152 },
153 [1] = {
154 .start = AU1200_SD_INT,
155 .end = AU1200_SD_INT,
156 .flags = IORESOURCE_IRQ,
157 },
158 [2] = {
159 .start = AU1200_DSCR_CMD0_SDMS_TX1,
160 .end = AU1200_DSCR_CMD0_SDMS_TX1,
161 .flags = IORESOURCE_DMA,
162 },
163 [3] = {
164 .start = AU1200_DSCR_CMD0_SDMS_RX1,
165 .end = AU1200_DSCR_CMD0_SDMS_RX1,
166 .flags = IORESOURCE_DMA,
167 }
168};
169
170static struct platform_device pb1200_mmc1_dev = {
171 .name = "au1xxx-mmc",
172 .id = 1,
173 .dev = {
174 .dma_mask = &au1xxx_mmc_dmamask,
175 .coherent_dma_mask = DMA_BIT_MASK(32),
176 .platform_data = &pb1200mmc_platdata[1],
177 },
178 .num_resources = ARRAY_SIZE(au1200_mmc1_res),
179 .resource = au1200_mmc1_res,
180};
181
182
183static struct resource ide_resources[] = {
184 [0] = {
185 .start = IDE_PHYS_ADDR,
186 .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1,
187 .flags = IORESOURCE_MEM
188 },
189 [1] = {
190 .start = IDE_INT,
191 .end = IDE_INT,
192 .flags = IORESOURCE_IRQ
193 },
194 [2] = {
195 .start = AU1200_DSCR_CMD0_DMA_REQ1,
196 .end = AU1200_DSCR_CMD0_DMA_REQ1,
197 .flags = IORESOURCE_DMA,
198 },
199};
200
201static u64 ide_dmamask = DMA_BIT_MASK(32);
202
203static struct platform_device ide_device = {
204 .name = "au1200-ide",
205 .id = 0,
206 .dev = {
207 .dma_mask = &ide_dmamask,
208 .coherent_dma_mask = DMA_BIT_MASK(32),
209 },
210 .num_resources = ARRAY_SIZE(ide_resources),
211 .resource = ide_resources
212};
213
214static struct smc91x_platdata smc_data = {
215 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
216 .leda = RPC_LED_100_10,
217 .ledb = RPC_LED_TX_RX,
218};
219
220static struct resource smc91c111_resources[] = {
221 [0] = {
222 .name = "smc91x-regs",
223 .start = SMC91C111_PHYS_ADDR,
224 .end = SMC91C111_PHYS_ADDR + 0xf,
225 .flags = IORESOURCE_MEM
226 },
227 [1] = {
228 .start = SMC91C111_INT,
229 .end = SMC91C111_INT,
230 .flags = IORESOURCE_IRQ
231 },
232};
233
234static struct platform_device smc91c111_device = {
235 .dev = {
236 .platform_data = &smc_data,
237 },
238 .name = "smc91x",
239 .id = -1,
240 .num_resources = ARRAY_SIZE(smc91c111_resources),
241 .resource = smc91c111_resources
242};
243
244static struct resource au1200_psc0_res[] = {
245 [0] = {
246 .start = AU1550_PSC0_PHYS_ADDR,
247 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
248 .flags = IORESOURCE_MEM,
249 },
250 [1] = {
251 .start = AU1200_PSC0_INT,
252 .end = AU1200_PSC0_INT,
253 .flags = IORESOURCE_IRQ,
254 },
255 [2] = {
256 .start = AU1200_DSCR_CMD0_PSC0_TX,
257 .end = AU1200_DSCR_CMD0_PSC0_TX,
258 .flags = IORESOURCE_DMA,
259 },
260 [3] = {
261 .start = AU1200_DSCR_CMD0_PSC0_RX,
262 .end = AU1200_DSCR_CMD0_PSC0_RX,
263 .flags = IORESOURCE_DMA,
264 },
265};
266
267static struct platform_device pb1200_i2c_dev = {
268 .name = "au1xpsc_smbus",
269 .id = 0, /* bus number */
270 .num_resources = ARRAY_SIZE(au1200_psc0_res),
271 .resource = au1200_psc0_res,
272};
273
274static struct resource au1200_lcd_res[] = {
275 [0] = {
276 .start = AU1200_LCD_PHYS_ADDR,
277 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
278 .flags = IORESOURCE_MEM,
279 },
280 [1] = {
281 .start = AU1200_LCD_INT,
282 .end = AU1200_LCD_INT,
283 .flags = IORESOURCE_IRQ,
284 }
285};
286
287static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
288
289static struct platform_device au1200_lcd_dev = {
290 .name = "au1200-lcd",
291 .id = 0,
292 .dev = {
293 .dma_mask = &au1200_lcd_dmamask,
294 .coherent_dma_mask = DMA_BIT_MASK(32),
295 },
296 .num_resources = ARRAY_SIZE(au1200_lcd_res),
297 .resource = au1200_lcd_res,
298};
299
300static struct platform_device *board_platform_devices[] __initdata = {
301 &ide_device,
302 &smc91c111_device,
303 &pb1200_i2c_dev,
304 &pb1200_mmc0_dev,
305 &pb1200_mmc1_dev,
306 &au1200_lcd_dev,
307};
308
309static int __init board_register_devices(void)
310{
311 int swapped;
312
313 db1x_register_pcmcia_socket(
314 AU1000_PCMCIA_ATTR_PHYS_ADDR,
315 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
316 AU1000_PCMCIA_MEM_PHYS_ADDR,
317 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
318 AU1000_PCMCIA_IO_PHYS_ADDR,
319 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
320 PB1200_PC0_INT, PB1200_PC0_INSERT_INT,
321 /*PB1200_PC0_STSCHG_INT*/0, PB1200_PC0_EJECT_INT, 0);
322
323 db1x_register_pcmcia_socket(
324 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
325 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
326 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
327 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
328 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
329 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
330 PB1200_PC1_INT, PB1200_PC1_INSERT_INT,
331 /*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1);
332
333 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
334 db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
335
336 return platform_add_devices(board_platform_devices,
337 ARRAY_SIZE(board_platform_devices));
338}
339device_initcall(board_register_devices);
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500.c
index 37c1883b5ea9..e7b807b3ec51 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500.c
@@ -1,41 +1,37 @@
1/* 1/*
2 * Copyright 2000, 2008 MontaVista Software Inc. 2 * Pb1500 board support.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 * 3 *
5 * This program is free software; you can redistribute it and/or modify it 4 * Copyright (C) 2009 Manuel Lauss
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 * 5 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 6 * This program is free software; you can redistribute it and/or modify
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 7 * it under the terms of the GNU General Public License as published by
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 8 * the Free Software Foundation; either version 2 of the License, or
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 9 * (at your option) any later version.
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 * 10 *
21 * You should have received a copy of the GNU General Public License along 11 * This program is distributed in the hope that it will be useful,
22 * with this program; if not, write to the Free Software Foundation, Inc., 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * 675 Mass Ave, Cambridge, MA 02139, USA. 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 */ 19 */
25 20
26#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/dma-mapping.h>
27#include <linux/gpio.h> 23#include <linux/gpio.h>
28#include <linux/init.h> 24#include <linux/init.h>
29#include <linux/interrupt.h> 25#include <linux/interrupt.h>
30 26#include <linux/platform_device.h>
31#include <asm/mach-au1x00/au1000.h> 27#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-db1x00/bcsr.h> 28#include <asm/mach-db1x00/bcsr.h>
33
34#include <prom.h> 29#include <prom.h>
30#include "platform.h"
35 31
36const char *get_system_type(void) 32const char *get_system_type(void)
37{ 33{
38 return "Alchemy Pb1500"; 34 return "PB1500";
39} 35}
40 36
41void __init board_setup(void) 37void __init board_setup(void)
@@ -123,17 +119,80 @@ void __init board_setup(void)
123 } 119 }
124} 120}
125 121
126static int __init pb1500_init_irq(void) 122/******************************************************************************/
123
124static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
127{ 125{
128 irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ 126 if ((slot < 12) || (slot > 13) || pin == 0)
129 irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ 127 return -1;
130 irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 128 if (slot == 12)
129 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
130 if (slot == 13) {
131 switch (pin) {
132 case 1: return AU1500_PCI_INTA;
133 case 2: return AU1500_PCI_INTB;
134 case 3: return AU1500_PCI_INTC;
135 case 4: return AU1500_PCI_INTD;
136 }
137 }
138 return -1;
139}
140
141static struct resource alchemy_pci_host_res[] = {
142 [0] = {
143 .start = AU1500_PCI_PHYS_ADDR,
144 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
145 .flags = IORESOURCE_MEM,
146 },
147};
148
149static struct alchemy_pci_platdata pb1500_pci_pd = {
150 .board_map_irq = pb1500_map_pci_irq,
151 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
152 PCI_CONFIG_CH |
153#if defined(__MIPSEB__)
154 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
155#else
156 0,
157#endif
158};
159
160static struct platform_device pb1500_pci_host = {
161 .dev.platform_data = &pb1500_pci_pd,
162 .name = "alchemy-pci",
163 .id = 0,
164 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
165 .resource = alchemy_pci_host_res,
166};
167
168static int __init pb1500_dev_init(void)
169{
170 int swapped;
171
172 irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
173 irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
174 irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
131 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); 175 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
132 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); 176 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
133 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); 177 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
134 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); 178 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
135 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); 179 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
136 180
181 /* PCMCIA. single socket, identical to Pb1100 */
182 db1x_register_pcmcia_socket(
183 AU1000_PCMCIA_ATTR_PHYS_ADDR,
184 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
185 AU1000_PCMCIA_MEM_PHYS_ADDR,
186 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
187 AU1000_PCMCIA_IO_PHYS_ADDR,
188 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
189 AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */
190 /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
191
192 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
193 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
194 platform_device_register(&pb1500_pci_host);
195
137 return 0; 196 return 0;
138} 197}
139arch_initcall(pb1500_init_irq); 198arch_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile
deleted file mode 100644
index e83b151b5b63..000000000000
--- a/arch/mips/alchemy/devboards/pb1500/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2000, 2001, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1500 board.
6#
7
8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
deleted file mode 100644
index 1e52a01bac00..000000000000
--- a/arch/mips/alchemy/devboards/pb1500/platform.c
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * Pb1500 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <asm/mach-au1x00/au1000.h>
25#include <asm/mach-db1x00/bcsr.h>
26
27#include "../platform.h"
28
29static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
30{
31 if ((slot < 12) || (slot > 13) || pin == 0)
32 return -1;
33 if (slot == 12)
34 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
35 if (slot == 13) {
36 switch (pin) {
37 case 1: return AU1500_PCI_INTA;
38 case 2: return AU1500_PCI_INTB;
39 case 3: return AU1500_PCI_INTC;
40 case 4: return AU1500_PCI_INTD;
41 }
42 }
43 return -1;
44}
45
46static struct resource alchemy_pci_host_res[] = {
47 [0] = {
48 .start = AU1500_PCI_PHYS_ADDR,
49 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
50 .flags = IORESOURCE_MEM,
51 },
52};
53
54static struct alchemy_pci_platdata pb1500_pci_pd = {
55 .board_map_irq = pb1500_map_pci_irq,
56 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
57 PCI_CONFIG_CH |
58#if defined(__MIPSEB__)
59 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
60#else
61 0,
62#endif
63};
64
65static struct platform_device pb1500_pci_host = {
66 .dev.platform_data = &pb1500_pci_pd,
67 .name = "alchemy-pci",
68 .id = 0,
69 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
70 .resource = alchemy_pci_host_res,
71};
72
73static int __init pb1500_dev_init(void)
74{
75 int swapped;
76
77 /* PCMCIA. single socket, identical to Pb1100 */
78 db1x_register_pcmcia_socket(
79 AU1000_PCMCIA_ATTR_PHYS_ADDR,
80 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
81 AU1000_PCMCIA_MEM_PHYS_ADDR,
82 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
83 AU1000_PCMCIA_IO_PHYS_ADDR,
84 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
85 AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */
86 /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
87
88 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
89 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
90 platform_device_register(&pb1500_pci_host);
91
92 return 0;
93}
94arch_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550.c
index a4604b8a349e..b37e7de8d920 100644
--- a/arch/mips/alchemy/devboards/pb1550/platform.c
+++ b/arch/mips/alchemy/devboards/pb1550.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Pb1550 board platform device registration 2 * Pb1550 board support.
3 * 3 *
4 * Copyright (C) 2009 Manuel Lauss 4 * Copyright (C) 2009-2011 Manuel Lauss
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -20,13 +20,44 @@
20 20
21#include <linux/dma-mapping.h> 21#include <linux/dma-mapping.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/interrupt.h>
23#include <linux/platform_device.h> 24#include <linux/platform_device.h>
24#include <asm/mach-au1x00/au1000.h> 25#include <asm/mach-au1x00/au1000.h>
25#include <asm/mach-au1x00/au1xxx_dbdma.h> 26#include <asm/mach-au1x00/au1xxx_dbdma.h>
26#include <asm/mach-pb1x00/pb1550.h> 27#include <asm/mach-au1x00/au1550nd.h>
28#include <asm/mach-au1x00/gpio.h>
27#include <asm/mach-db1x00/bcsr.h> 29#include <asm/mach-db1x00/bcsr.h>
30#include "platform.h"
28 31
29#include "../platform.h" 32const char *get_system_type(void)
33{
34 return "PB1550";
35}
36
37void __init board_setup(void)
38{
39 u32 pin_func;
40
41 bcsr_init(PB1550_BCSR_PHYS_ADDR,
42 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
43
44 alchemy_gpio2_enable();
45
46 /*
47 * Enable PSC1 SYNC for AC'97. Normaly done in audio driver,
48 * but it is board specific code, so put it here.
49 */
50 pin_func = au_readl(SYS_PINFUNC);
51 au_sync();
52 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
53 au_writel(pin_func, SYS_PINFUNC);
54
55 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
56
57 printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
58}
59
60/******************************************************************************/
30 61
31static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) 62static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
32{ 63{
@@ -101,10 +132,79 @@ static struct platform_device pb1550_i2c_dev = {
101 .resource = au1550_psc2_res, 132 .resource = au1550_psc2_res,
102}; 133};
103 134
135static struct mtd_partition pb1550_nand_parts[] = {
136 [0] = {
137 .name = "NAND FS 0",
138 .offset = 0,
139 .size = 8 * 1024 * 1024,
140 },
141 [1] = {
142 .name = "NAND FS 1",
143 .offset = MTDPART_OFS_APPEND,
144 .size = MTDPART_SIZ_FULL,
145 },
146};
147
148static struct au1550nd_platdata pb1550_nand_pd = {
149 .parts = pb1550_nand_parts,
150 .num_parts = ARRAY_SIZE(pb1550_nand_parts),
151 .devwidth = 0, /* x8 NAND default, needs fixing up */
152};
153
154static struct resource pb1550_nand_res[] = {
155 [0] = {
156 .start = 0x20000000,
157 .end = 0x20000fff,
158 .flags = IORESOURCE_MEM,
159 },
160};
161
162static struct platform_device pb1550_nand_dev = {
163 .name = "au1550-nand",
164 .id = -1,
165 .resource = pb1550_nand_res,
166 .num_resources = ARRAY_SIZE(pb1550_nand_res),
167 .dev = {
168 .platform_data = &pb1550_nand_pd,
169 },
170};
171
172static void __init pb1550_nand_setup(void)
173{
174 int boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) |
175 ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
176
177 switch (boot_swapboot) {
178 case 0:
179 case 2:
180 case 8:
181 case 0xC:
182 case 0xD:
183 /* x16 NAND Flash */
184 pb1550_nand_pd.devwidth = 1;
185 /* fallthrough */
186 case 1:
187 case 9:
188 case 3:
189 case 0xE:
190 case 0xF:
191 /* x8 NAND, already set up */
192 platform_device_register(&pb1550_nand_dev);
193 }
194}
195
104static int __init pb1550_dev_init(void) 196static int __init pb1550_dev_init(void)
105{ 197{
106 int swapped; 198 int swapped;
107 199
200 irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
201 irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
202 irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
203
204 /* enable both PCMCIA card irqs in the shared line */
205 alchemy_gpio2_enable_int(201);
206 alchemy_gpio2_enable_int(202);
207
108 /* Pb1550, like all others, also has statuschange irqs; however they're 208 /* Pb1550, like all others, also has statuschange irqs; however they're
109 * wired up on one of the Au1550's shared GPIO201_205 line, which also 209 * wired up on one of the Au1550's shared GPIO201_205 line, which also
110 * services the PCMCIA card interrupts. So we ignore statuschange and 210 * services the PCMCIA card interrupts. So we ignore statuschange and
@@ -130,6 +230,10 @@ static int __init pb1550_dev_init(void)
130 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, 230 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
131 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1); 231 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
132 232
233 /* NAND setup */
234 gpio_direction_input(206); /* GPIO206 high */
235 pb1550_nand_setup();
236
133 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; 237 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
134 db1x_register_norflash(128 * 1024 * 1024, 4, swapped); 238 db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
135 platform_device_register(&pb1550_pci_host); 239 platform_device_register(&pb1550_pci_host);
diff --git a/arch/mips/alchemy/devboards/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile
deleted file mode 100644
index 9661b6ec5dd3..000000000000
--- a/arch/mips/alchemy/devboards/pb1550/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2000, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1550 board.
6#
7
8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
deleted file mode 100644
index 0f62d1e3df24..000000000000
--- a/arch/mips/alchemy/devboards/pb1550/board_setup.c
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1550 board setup.
5 *
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/init.h>
31#include <linux/interrupt.h>
32
33#include <asm/mach-au1x00/au1000.h>
34#include <asm/mach-pb1x00/pb1550.h>
35#include <asm/mach-db1x00/bcsr.h>
36#include <asm/mach-au1x00/gpio.h>
37
38#include <prom.h>
39
40const char *get_system_type(void)
41{
42 return "Alchemy Pb1550";
43}
44
45void __init board_setup(void)
46{
47 u32 pin_func;
48
49 bcsr_init(PB1550_BCSR_PHYS_ADDR,
50 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
51
52 alchemy_gpio2_enable();
53
54 /*
55 * Enable PSC1 SYNC for AC'97. Normaly done in audio driver,
56 * but it is board specific code, so put it here.
57 */
58 pin_func = au_readl(SYS_PINFUNC);
59 au_sync();
60 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
61 au_writel(pin_func, SYS_PINFUNC);
62
63 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
64
65 printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
66}
67
68static int __init pb1550_init_irq(void)
69{
70 irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
71 irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
72 irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
73
74 /* enable both PCMCIA card irqs in the shared line */
75 alchemy_gpio2_enable_int(201);
76 alchemy_gpio2_enable_int(202);
77
78 return 0;
79}
80arch_initcall(pb1550_init_irq);
diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c
index 49a4b3244d8e..621f70afb63a 100644
--- a/arch/mips/alchemy/devboards/platform.c
+++ b/arch/mips/alchemy/devboards/platform.c
@@ -13,6 +13,13 @@
13#include <asm/reboot.h> 13#include <asm/reboot.h>
14#include <asm/mach-db1x00/bcsr.h> 14#include <asm/mach-db1x00/bcsr.h>
15 15
16
17static struct platform_device db1x00_rtc_dev = {
18 .name = "rtc-au1xxx",
19 .id = -1,
20};
21
22
16static void db1x_power_off(void) 23static void db1x_power_off(void)
17{ 24{
18 bcsr_write(BCSR_RESETS, 0); 25 bcsr_write(BCSR_RESETS, 0);
@@ -25,7 +32,7 @@ static void db1x_reset(char *c)
25 bcsr_write(BCSR_SYSTEM, 0); 32 bcsr_write(BCSR_SYSTEM, 0);
26} 33}
27 34
28static int __init db1x_poweroff_setup(void) 35static int __init db1x_late_setup(void)
29{ 36{
30 if (!pm_power_off) 37 if (!pm_power_off)
31 pm_power_off = db1x_power_off; 38 pm_power_off = db1x_power_off;
@@ -34,9 +41,11 @@ static int __init db1x_poweroff_setup(void)
34 if (!_machine_restart) 41 if (!_machine_restart)
35 _machine_restart = db1x_reset; 42 _machine_restart = db1x_reset;
36 43
44 platform_device_register(&db1x00_rtc_dev);
45
37 return 0; 46 return 0;
38} 47}
39late_initcall(db1x_poweroff_setup); 48device_initcall(db1x_late_setup);
40 49
41/* register a pcmcia socket */ 50/* register a pcmcia socket */
42int __init db1x_register_pcmcia_socket(phys_addr_t pcmcia_attr_start, 51int __init db1x_register_pcmcia_socket(phys_addr_t pcmcia_attr_start,
diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c
index e5306b56da6d..93a22107cc41 100644
--- a/arch/mips/alchemy/devboards/prom.c
+++ b/arch/mips/alchemy/devboards/prom.c
@@ -33,10 +33,9 @@
33#include <asm/mach-au1x00/au1000.h> 33#include <asm/mach-au1x00/au1000.h>
34#include <prom.h> 34#include <prom.h>
35 35
36#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || \ 36#if defined(CONFIG_MIPS_DB1000) || \
37 defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \ 37 defined(CONFIG_MIPS_PB1100) || \
38 defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \ 38 defined(CONFIG_MIPS_PB1500)
39 defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
40#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000 39#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000
41 40
42#else /* Au1550/Au1200-based develboards */ 41#else /* Au1550/Au1200-based develboards */
@@ -62,5 +61,9 @@ void __init prom_init(void)
62 61
63void prom_putchar(unsigned char c) 62void prom_putchar(unsigned char c)
64{ 63{
64#ifdef CONFIG_MIPS_DB1300
65 alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
66#else
65 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); 67 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
68#endif
66} 69}
diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile
deleted file mode 100644
index cb73fe256dce..000000000000
--- a/arch/mips/alchemy/gpr/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2003 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for Trapeze ITS GPR board.
6#
7
8obj-y += board_setup.o init.o platform.o
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
deleted file mode 100644
index dea45c78fdcd..000000000000
--- a/arch/mips/alchemy/gpr/board_setup.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
3 *
4 * Copyright 2000-2003, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/gpio.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/delay.h>
32#include <linux/pm.h>
33
34#include <asm/reboot.h>
35#include <asm/mach-au1x00/au1000.h>
36
37#include <prom.h>
38
39static void gpr_reset(char *c)
40{
41 /* switch System-LED to orange (red# and green# on) */
42 alchemy_gpio_direction_output(4, 0);
43 alchemy_gpio_direction_output(5, 0);
44
45 /* trigger watchdog to reset board in 200ms */
46 printk(KERN_EMERG "Triggering watchdog soft reset...\n");
47 raw_local_irq_disable();
48 alchemy_gpio_direction_output(1, 0);
49 udelay(1);
50 alchemy_gpio_set_value(1, 1);
51 while (1)
52 cpu_wait();
53}
54
55static void gpr_power_off(void)
56{
57 while (1)
58 cpu_wait();
59}
60
61void __init board_setup(void)
62{
63 printk(KERN_INFO "Trapeze ITS GPR board\n");
64
65 pm_power_off = gpr_power_off;
66 _machine_halt = gpr_power_off;
67 _machine_restart = gpr_reset;
68
69 /* Enable UART1/3 */
70 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
71 alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
72
73 /* Take away Reset of UMTS-card */
74 alchemy_gpio_direction_output(215, 1);
75}
diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c
deleted file mode 100644
index 229aafae680c..000000000000
--- a/arch/mips/alchemy/gpr/init.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
3 *
4 * Copyright 2003, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <linux/kernel.h>
30
31#include <asm/bootinfo.h>
32#include <asm/mach-au1x00/au1000.h>
33
34#include <prom.h>
35
36const char *get_system_type(void)
37{
38 return "GPR";
39}
40
41void __init prom_init(void)
42{
43 unsigned char *memsize_str;
44 unsigned long memsize;
45
46 prom_argc = fw_arg0;
47 prom_argv = (char **)fw_arg1;
48 prom_envp = (char **)fw_arg2;
49
50 prom_init_cmdline();
51
52 memsize_str = prom_getenv("memsize");
53 if (!memsize_str)
54 memsize = 0x04000000;
55 else
56 strict_strtoul(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58}
59
60void prom_putchar(unsigned char c)
61{
62 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
63}
diff --git a/arch/mips/alchemy/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile
deleted file mode 100644
index 81b540ceaf88..000000000000
--- a/arch/mips/alchemy/mtx-1/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
1#
2# Copyright 2003 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4# Bruno Randolf <bruno.randolf@4g-systems.biz>
5#
6# Makefile for 4G Systems MTX-1 board.
7#
8
9obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
deleted file mode 100644
index 851a5ab4c8f2..000000000000
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * 4G Systems MTX-1 board setup.
5 *
6 * Copyright 2003, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Bruno Randolf <bruno.randolf@4g-systems.biz>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/gpio.h>
32#include <linux/init.h>
33#include <linux/interrupt.h>
34#include <linux/pm.h>
35
36#include <asm/reboot.h>
37#include <asm/mach-au1x00/au1000.h>
38
39#include <prom.h>
40
41static void mtx1_reset(char *c)
42{
43 /* Jump to the reset vector */
44 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
45}
46
47static void mtx1_power_off(void)
48{
49 while (1)
50 asm volatile (
51 " .set mips32 \n"
52 " wait \n"
53 " .set mips0 \n");
54}
55
56void __init board_setup(void)
57{
58#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
59 /* Enable USB power switch */
60 alchemy_gpio_direction_output(204, 0);
61#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
62
63 /* Initialize sys_pinfunc */
64 au_writel(SYS_PF_NI2, SYS_PINFUNC);
65
66 /* Initialize GPIO */
67 au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR);
68 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
69 alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
70 alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
71 alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */
72
73 /* Enable LED and set it to green */
74 alchemy_gpio_direction_output(211, 1); /* green on */
75 alchemy_gpio_direction_output(212, 0); /* red off */
76
77 pm_power_off = mtx1_power_off;
78 _machine_halt = mtx1_power_off;
79 _machine_restart = mtx1_reset;
80
81 printk(KERN_INFO "4G Systems MTX-1 Board\n");
82}
83
84static int __init mtx1_init_irq(void)
85{
86 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
87 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
88 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
89 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
90 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
91
92 return 0;
93}
94arch_initcall(mtx1_init_irq);
diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c
deleted file mode 100644
index 2e81cc7f3422..000000000000
--- a/arch/mips/alchemy/mtx-1/init.c
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * 4G Systems MTX-1 board setup
5 *
6 * Copyright 2003, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Bruno Randolf <bruno.randolf@4g-systems.biz>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/kernel.h>
32#include <linux/init.h>
33
34#include <asm/bootinfo.h>
35#include <asm/mach-au1x00/au1000.h>
36
37#include <prom.h>
38
39const char *get_system_type(void)
40{
41 return "MTX-1";
42}
43
44void __init prom_init(void)
45{
46 unsigned char *memsize_str;
47 unsigned long memsize;
48
49 prom_argc = fw_arg0;
50 prom_argv = (char **)fw_arg1;
51 prom_envp = (char **)fw_arg2;
52
53 prom_init_cmdline();
54
55 memsize_str = prom_getenv("memsize");
56 if (!memsize_str)
57 memsize = 0x04000000;
58 else
59 strict_strtoul(memsize_str, 0, &memsize);
60 add_memory_region(0, memsize, BOOT_MEM_RAM);
61}
62
63void prom_putchar(unsigned char c)
64{
65 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
66}
diff --git a/arch/mips/alchemy/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile
deleted file mode 100644
index 91defcf4f335..000000000000
--- a/arch/mips/alchemy/xxs1500/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2003 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for MyCable XXS1500 board.
6#
7
8obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
deleted file mode 100644
index 3fa83f72e014..000000000000
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * Copyright 2000-2003, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/gpio.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/delay.h>
30#include <linux/pm.h>
31
32#include <asm/reboot.h>
33#include <asm/mach-au1x00/au1000.h>
34
35#include <prom.h>
36
37static void xxs1500_reset(char *c)
38{
39 /* Jump to the reset vector */
40 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
41}
42
43static void xxs1500_power_off(void)
44{
45 while (1)
46 asm volatile (
47 " .set mips32 \n"
48 " wait \n"
49 " .set mips0 \n");
50}
51
52void __init board_setup(void)
53{
54 u32 pin_func;
55
56 pm_power_off = xxs1500_power_off;
57 _machine_halt = xxs1500_power_off;
58 _machine_restart = xxs1500_reset;
59
60 alchemy_gpio1_input_enable();
61 alchemy_gpio2_enable();
62
63 /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
64 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
65 pin_func |= SYS_PF_UR3;
66 au_writel(pin_func, SYS_PINFUNC);
67
68 /* Enable UART */
69 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
70 /* Enable DTR (MCR bit 0) = USB power up */
71 __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
72 wmb();
73}
74
75static int __init xxs1500_init_irq(void)
76{
77 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
78 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
79 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
80 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
81 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
82 irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
83
84 irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
85 irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
86 irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
87 irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
88 irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
89 irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
90
91 return 0;
92}
93arch_initcall(xxs1500_init_irq);
diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
deleted file mode 100644
index 0ee02cfa989d..000000000000
--- a/arch/mips/alchemy/xxs1500/init.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * XXS1500 board setup
4 *
5 * Copyright 2003, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/kernel.h>
31
32#include <asm/bootinfo.h>
33#include <asm/mach-au1x00/au1000.h>
34
35#include <prom.h>
36
37const char *get_system_type(void)
38{
39 return "XXS1500";
40}
41
42void __init prom_init(void)
43{
44 unsigned char *memsize_str;
45 unsigned long memsize;
46
47 prom_argc = fw_arg0;
48 prom_argv = (char **)fw_arg1;
49 prom_envp = (char **)fw_arg2;
50
51 prom_init_cmdline();
52
53 memsize_str = prom_getenv("memsize");
54 if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
55 memsize = 0x04000000;
56
57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58}
59
60void prom_putchar(unsigned char c)
61{
62 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
63}
diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c
deleted file mode 100644
index 06a3a459b8aa..000000000000
--- a/arch/mips/alchemy/xxs1500/platform.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * XXS1500 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23
24#include <asm/mach-au1x00/au1000.h>
25
26static struct resource xxs1500_pcmcia_res[] = {
27 {
28 .name = "pcmcia-io",
29 .flags = IORESOURCE_MEM,
30 .start = AU1000_PCMCIA_IO_PHYS_ADDR,
31 .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
32 },
33 {
34 .name = "pcmcia-attr",
35 .flags = IORESOURCE_MEM,
36 .start = AU1000_PCMCIA_ATTR_PHYS_ADDR,
37 .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
38 },
39 {
40 .name = "pcmcia-mem",
41 .flags = IORESOURCE_MEM,
42 .start = AU1000_PCMCIA_MEM_PHYS_ADDR,
43 .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
44 },
45};
46
47static struct platform_device xxs1500_pcmcia_dev = {
48 .name = "xxs1500_pcmcia",
49 .id = -1,
50 .num_resources = ARRAY_SIZE(xxs1500_pcmcia_res),
51 .resource = xxs1500_pcmcia_res,
52};
53
54static struct platform_device *xxs1500_devs[] __initdata = {
55 &xxs1500_pcmcia_dev,
56};
57
58static int __init xxs1500_dev_init(void)
59{
60 return platform_add_devices(xxs1500_devs,
61 ARRAY_SIZE(xxs1500_devs));
62}
63device_initcall(xxs1500_dev_init);
diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c
index eb063e6dead9..3112df8f90db 100644
--- a/arch/mips/boot/compressed/uart-alchemy.c
+++ b/arch/mips/boot/compressed/uart-alchemy.c
@@ -2,6 +2,9 @@
2 2
3void putc(char c) 3void putc(char c)
4{ 4{
5 /* all current (Jan. 2010) in-kernel boards */ 5#ifdef CONFIG_MIPS_DB1300
6 alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
7#else
6 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); 8 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
9#endif
7} 10}
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 4044c9e0fb73..17a36c125172 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -1,118 +1,359 @@
1CONFIG_MIPS=y
1CONFIG_MIPS_ALCHEMY=y 2CONFIG_MIPS_ALCHEMY=y
3CONFIG_MIPS_DB1000=y
4CONFIG_SCHED_OMIT_FRAME_POINTER=y
5CONFIG_TICK_ONESHOT=y
2CONFIG_NO_HZ=y 6CONFIG_NO_HZ=y
3CONFIG_HIGH_RES_TIMERS=y 7CONFIG_HIGH_RES_TIMERS=y
4CONFIG_HZ_100=y 8CONFIG_HZ_100=y
5# CONFIG_SECCOMP is not set 9CONFIG_HZ=100
10CONFIG_PREEMPT_NONE=y
6CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
7CONFIG_LOCALVERSION="-db1000" 12CONFIG_BROKEN_ON_SMP=y
13CONFIG_INIT_ENV_ARG_LIMIT=32
14CONFIG_CROSS_COMPILE=""
15CONFIG_LOCALVERSION="-db1x00"
16CONFIG_LOCALVERSION_AUTO=y
8CONFIG_KERNEL_LZMA=y 17CONFIG_KERNEL_LZMA=y
18CONFIG_DEFAULT_HOSTNAME="db1x00"
19CONFIG_SWAP=y
9CONFIG_SYSVIPC=y 20CONFIG_SYSVIPC=y
10CONFIG_POSIX_MQUEUE=y 21CONFIG_SYSVIPC_SYSCTL=y
22CONFIG_FHANDLE=y
23CONFIG_AUDIT=y
11CONFIG_TINY_RCU=y 24CONFIG_TINY_RCU=y
12CONFIG_LOG_BUF_SHIFT=14 25CONFIG_LOG_BUF_SHIFT=18
13# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 26CONFIG_NAMESPACES=y
27CONFIG_UTS_NS=y
28CONFIG_IPC_NS=y
29CONFIG_USER_NS=y
30CONFIG_PID_NS=y
31CONFIG_NET_NS=y
32CONFIG_SYSCTL=y
14CONFIG_EXPERT=y 33CONFIG_EXPERT=y
15# CONFIG_KALLSYMS is not set 34CONFIG_KALLSYMS=y
16# CONFIG_PCSPKR_PLATFORM is not set 35CONFIG_KALLSYMS_ALL=y
17# CONFIG_VM_EVENT_COUNTERS is not set 36CONFIG_HOTPLUG=y
18# CONFIG_COMPAT_BRK is not set 37CONFIG_PRINTK=y
38CONFIG_BUG=y
39CONFIG_ELF_CORE=y
40CONFIG_BASE_FULL=y
41CONFIG_FUTEX=y
42CONFIG_EPOLL=y
43CONFIG_SIGNALFD=y
44CONFIG_TIMERFD=y
45CONFIG_EVENTFD=y
46CONFIG_SHMEM=y
47CONFIG_AIO=y
48CONFIG_EMBEDDED=y
49CONFIG_HAVE_PERF_EVENTS=y
50CONFIG_PERF_USE_VMALLOC=y
51CONFIG_PCI_QUIRKS=y
19CONFIG_SLAB=y 52CONFIG_SLAB=y
20CONFIG_MODULES=y 53CONFIG_SLABINFO=y
21CONFIG_MODULE_UNLOAD=y 54CONFIG_BLOCK=y
22# CONFIG_LBDAF is not set 55CONFIG_LBDAF=y
23# CONFIG_BLK_DEV_BSG is not set 56CONFIG_BLK_DEV_BSG=y
24# CONFIG_IOSCHED_DEADLINE is not set 57CONFIG_BLK_DEV_BSGLIB=y
25# CONFIG_IOSCHED_CFQ is not set 58CONFIG_IOSCHED_NOOP=y
59CONFIG_DEFAULT_NOOP=y
60CONFIG_DEFAULT_IOSCHED="noop"
61CONFIG_FREEZER=y
62CONFIG_PCI=y
63CONFIG_PCI_DOMAINS=y
26CONFIG_PCCARD=y 64CONFIG_PCCARD=y
65CONFIG_PCMCIA=y
66CONFIG_PCMCIA_LOAD_CIS=y
27CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y 67CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
28CONFIG_PM=y 68CONFIG_BINFMT_ELF=y
69CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
70CONFIG_SUSPEND=y
71CONFIG_SUSPEND_FREEZER=y
72CONFIG_PM_SLEEP=y
29CONFIG_PM_RUNTIME=y 73CONFIG_PM_RUNTIME=y
74CONFIG_PM=y
30CONFIG_NET=y 75CONFIG_NET=y
31CONFIG_PACKET=y 76CONFIG_PACKET=y
32CONFIG_UNIX=y 77CONFIG_UNIX=y
78CONFIG_XFRM=y
33CONFIG_INET=y 79CONFIG_INET=y
34CONFIG_IP_MULTICAST=y 80CONFIG_IP_MULTICAST=y
35CONFIG_IP_PNP=y 81CONFIG_IP_PNP=y
36CONFIG_IP_PNP_DHCP=y 82CONFIG_IP_PNP_DHCP=y
37CONFIG_IP_PNP_BOOTP=y 83CONFIG_IP_PNP_BOOTP=y
38CONFIG_IP_PNP_RARP=y 84CONFIG_IP_PNP_RARP=y
39# CONFIG_INET_XFRM_MODE_TRANSPORT is not set 85CONFIG_NET_IPIP=y
40# CONFIG_INET_XFRM_MODE_TUNNEL is not set 86CONFIG_INET_TUNNEL=y
41# CONFIG_INET_XFRM_MODE_BEET is not set 87CONFIG_INET_LRO=y
42# CONFIG_INET_DIAG is not set 88CONFIG_TCP_CONG_CUBIC=y
43# CONFIG_IPV6 is not set 89CONFIG_DEFAULT_TCP_CONG="cubic"
44# CONFIG_WIRELESS is not set 90CONFIG_IPV6=y
45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 91CONFIG_INET6_XFRM_MODE_TRANSPORT=y
92CONFIG_INET6_XFRM_MODE_TUNNEL=y
93CONFIG_INET6_XFRM_MODE_BEET=y
94CONFIG_IPV6_SIT=y
95CONFIG_IPV6_NDISC_NODETYPE=y
96CONFIG_STP=y
97CONFIG_GARP=y
98CONFIG_BRIDGE=y
99CONFIG_BRIDGE_IGMP_SNOOPING=y
100CONFIG_VLAN_8021Q=y
101CONFIG_VLAN_8021Q_GVRP=y
102CONFIG_LLC=y
103CONFIG_LLC2=y
104CONFIG_DNS_RESOLVER=y
105CONFIG_BT=y
106CONFIG_BT_L2CAP=y
107CONFIG_BT_SCO=y
108CONFIG_BT_RFCOMM=y
109CONFIG_BT_RFCOMM_TTY=y
110CONFIG_BT_BNEP=y
111CONFIG_BT_BNEP_MC_FILTER=y
112CONFIG_BT_BNEP_PROTO_FILTER=y
113CONFIG_BT_HIDP=y
114CONFIG_BT_HCIBTUSB=y
115CONFIG_UEVENT_HELPER_PATH=""
116CONFIG_STANDALONE=y
117CONFIG_PREVENT_FIRMWARE_BUILD=y
118CONFIG_FW_LOADER=y
46CONFIG_MTD=y 119CONFIG_MTD=y
47CONFIG_MTD_PARTITIONS=y
48CONFIG_MTD_CMDLINE_PARTS=y 120CONFIG_MTD_CMDLINE_PARTS=y
49CONFIG_MTD_CHAR=y 121CONFIG_MTD_CHAR=y
122CONFIG_MTD_BLKDEVS=y
50CONFIG_MTD_BLOCK=y 123CONFIG_MTD_BLOCK=y
51CONFIG_MTD_CFI=y 124CONFIG_MTD_CFI=y
125CONFIG_MTD_GEN_PROBE=y
126CONFIG_MTD_CFI_ADV_OPTIONS=y
127CONFIG_MTD_CFI_NOSWAP=y
128CONFIG_MTD_CFI_GEOMETRY=y
129CONFIG_MTD_MAP_BANK_WIDTH_1=y
130CONFIG_MTD_MAP_BANK_WIDTH_2=y
131CONFIG_MTD_MAP_BANK_WIDTH_4=y
132CONFIG_MTD_CFI_I1=y
133CONFIG_MTD_CFI_I2=y
134CONFIG_MTD_CFI_I4=y
135CONFIG_MTD_CFI_I8=y
136CONFIG_MTD_CFI_INTELEXT=y
52CONFIG_MTD_CFI_AMDSTD=y 137CONFIG_MTD_CFI_AMDSTD=y
138CONFIG_MTD_CFI_UTIL=y
53CONFIG_MTD_PHYSMAP=y 139CONFIG_MTD_PHYSMAP=y
54# CONFIG_MISC_DEVICES is not set 140CONFIG_SCSI_MOD=y
141CONFIG_SCSI=y
142CONFIG_SCSI_DMA=y
143CONFIG_SCSI_PROC_FS=y
144CONFIG_BLK_DEV_SD=y
145CONFIG_CHR_DEV_SG=y
146CONFIG_SCSI_MULTI_LUN=y
147CONFIG_SCSI_CONSTANTS=y
148CONFIG_ATA=y
149CONFIG_ATA_VERBOSE_ERROR=y
150CONFIG_ATA_SFF=y
151CONFIG_ATA_BMDMA=y
152CONFIG_PATA_HPT37X=y
153CONFIG_PATA_PCMCIA=y
154CONFIG_MD=y
155CONFIG_BLK_DEV_DM=y
156CONFIG_FIREWIRE=y
157CONFIG_FIREWIRE_OHCI=y
158CONFIG_FIREWIRE_OHCI_DEBUG=y
159CONFIG_FIREWIRE_NET=y
55CONFIG_NETDEVICES=y 160CONFIG_NETDEVICES=y
56CONFIG_MARVELL_PHY=y
57CONFIG_DAVICOM_PHY=y
58CONFIG_QSEMI_PHY=y
59CONFIG_LXT_PHY=y
60CONFIG_CICADA_PHY=y
61CONFIG_VITESSE_PHY=y
62CONFIG_SMSC_PHY=y
63CONFIG_BROADCOM_PHY=y
64CONFIG_ICPLUS_PHY=y
65CONFIG_REALTEK_PHY=y
66CONFIG_NATIONAL_PHY=y
67CONFIG_STE10XP=y
68CONFIG_LSI_ET1011C_PHY=y
69CONFIG_NET_ETHERNET=y
70CONFIG_MII=y 161CONFIG_MII=y
162CONFIG_PHYLIB=y
163CONFIG_NET_ETHERNET=y
71CONFIG_MIPS_AU1X00_ENET=y 164CONFIG_MIPS_AU1X00_ENET=y
72# CONFIG_NETDEV_1000 is not set 165CONFIG_NET_PCMCIA=y
73# CONFIG_NETDEV_10000 is not set 166CONFIG_PCMCIA_3C589=y
74# CONFIG_WLAN is not set 167CONFIG_PCMCIA_PCNET=y
75# CONFIG_INPUT_MOUSEDEV is not set 168CONFIG_PPP=y
169CONFIG_PPP_MULTILINK=y
170CONFIG_PPP_FILTER=y
171CONFIG_PPP_ASYNC=y
172CONFIG_PPP_SYNC_TTY=y
173CONFIG_PPP_DEFLATE=y
174CONFIG_PPP_BSDCOMP=y
175CONFIG_PPP_MPPE=y
176CONFIG_PPPOE=y
177CONFIG_INPUT=y
76CONFIG_INPUT_EVDEV=y 178CONFIG_INPUT_EVDEV=y
77# CONFIG_INPUT_KEYBOARD is not set 179CONFIG_INPUT_MISC=y
78# CONFIG_INPUT_MOUSE is not set 180CONFIG_INPUT_UINPUT=y
79# CONFIG_SERIO is not set 181CONFIG_VT=y
182CONFIG_CONSOLE_TRANSLATIONS=y
183CONFIG_VT_CONSOLE=y
184CONFIG_HW_CONSOLE=y
185CONFIG_UNIX98_PTYS=y
186CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
187CONFIG_DEVKMEM=y
80CONFIG_SERIAL_8250=y 188CONFIG_SERIAL_8250=y
81CONFIG_SERIAL_8250_CONSOLE=y 189CONFIG_SERIAL_8250_CONSOLE=y
82# CONFIG_LEGACY_PTYS is not set 190CONFIG_SERIAL_8250_NR_UARTS=4
83# CONFIG_HW_RANDOM is not set 191CONFIG_SERIAL_8250_RUNTIME_UARTS=4
84# CONFIG_HWMON is not set 192CONFIG_SERIAL_CORE=y
85# CONFIG_VGA_CONSOLE is not set 193CONFIG_SERIAL_CORE_CONSOLE=y
194CONFIG_TTY_PRINTK=y
195CONFIG_DEVPORT=y
196CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
197CONFIG_FB=y
198CONFIG_FB_CFB_FILLRECT=y
199CONFIG_FB_CFB_COPYAREA=y
200CONFIG_FB_CFB_IMAGEBLIT=y
201CONFIG_FB_AU1100=y
202CONFIG_DUMMY_CONSOLE=y
203CONFIG_FRAMEBUFFER_CONSOLE=y
204CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
205CONFIG_FONTS=y
206CONFIG_FONT_8x16=y
207CONFIG_SOUND=y
208CONFIG_SND=y
209CONFIG_SND_TIMER=y
210CONFIG_SND_PCM=y
211CONFIG_SND_JACK=y
212CONFIG_SND_SEQUENCER=y
213CONFIG_SND_HRTIMER=y
214CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
215CONFIG_SND_DYNAMIC_MINORS=y
216CONFIG_SND_VMASTER=y
217CONFIG_SND_AC97_CODEC=y
218CONFIG_SND_SOC=y
219CONFIG_SND_SOC_AC97_BUS=y
220CONFIG_SND_SOC_AU1XAUDIO=y
221CONFIG_SND_SOC_AU1XAC97C=y
222CONFIG_SND_SOC_DB1000=y
223CONFIG_SND_SOC_AC97_CODEC=y
224CONFIG_AC97_BUS=y
225CONFIG_HID_SUPPORT=y
226CONFIG_HID=y
227CONFIG_HIDRAW=y
228CONFIG_USB_HID=y
229CONFIG_USB_SUPPORT=y
86CONFIG_USB=y 230CONFIG_USB=y
87# CONFIG_USB_DEVICE_CLASS is not set
88CONFIG_USB_DYNAMIC_MINORS=y
89CONFIG_USB_SUSPEND=y 231CONFIG_USB_SUSPEND=y
232CONFIG_USB_EHCI_HCD=y
233CONFIG_USB_EHCI_ROOT_HUB_TT=y
234CONFIG_USB_EHCI_TT_NEWSCHED=y
90CONFIG_USB_OHCI_HCD=y 235CONFIG_USB_OHCI_HCD=y
236CONFIG_USB_UHCI_HCD=y
237CONFIG_USB_STORAGE=y
238CONFIG_NEW_LEDS=y
239CONFIG_LEDS_CLASS=y
240CONFIG_LEDS_TRIGGERS=y
241CONFIG_RTC_LIB=y
91CONFIG_RTC_CLASS=y 242CONFIG_RTC_CLASS=y
243CONFIG_RTC_HCTOSYS=y
244CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
245CONFIG_RTC_INTF_SYSFS=y
246CONFIG_RTC_INTF_PROC=y
247CONFIG_RTC_INTF_DEV=y
92CONFIG_RTC_DRV_AU1XXX=y 248CONFIG_RTC_DRV_AU1XXX=y
93CONFIG_EXT2_FS=y 249CONFIG_EXT4_FS=y
94CONFIG_EXT3_FS=y 250CONFIG_EXT4_USE_FOR_EXT23=y
95# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 251CONFIG_EXT4_FS_XATTR=y
96# CONFIG_EXT3_FS_XATTR is not set 252CONFIG_EXT4_FS_POSIX_ACL=y
97# CONFIG_PROC_PAGE_MONITOR is not set 253CONFIG_EXT4_FS_SECURITY=y
254CONFIG_JBD2=y
255CONFIG_FS_MBCACHE=y
256CONFIG_FS_POSIX_ACL=y
257CONFIG_EXPORTFS=y
258CONFIG_FILE_LOCKING=y
259CONFIG_FSNOTIFY=y
260CONFIG_DNOTIFY=y
261CONFIG_INOTIFY_USER=y
262CONFIG_GENERIC_ACL=y
263CONFIG_PROC_FS=y
264CONFIG_PROC_KCORE=y
265CONFIG_PROC_SYSCTL=y
266CONFIG_SYSFS=y
98CONFIG_TMPFS=y 267CONFIG_TMPFS=y
99CONFIG_CRAMFS=y 268CONFIG_TMPFS_POSIX_ACL=y
269CONFIG_TMPFS_XATTR=y
270CONFIG_MISC_FILESYSTEMS=y
271CONFIG_JFFS2_FS=y
272CONFIG_JFFS2_FS_DEBUG=0
273CONFIG_JFFS2_FS_WRITEBUFFER=y
274CONFIG_JFFS2_SUMMARY=y
275CONFIG_JFFS2_FS_XATTR=y
276CONFIG_JFFS2_FS_POSIX_ACL=y
277CONFIG_JFFS2_FS_SECURITY=y
278CONFIG_JFFS2_COMPRESSION_OPTIONS=y
279CONFIG_JFFS2_ZLIB=y
280CONFIG_JFFS2_LZO=y
281CONFIG_JFFS2_RTIME=y
282CONFIG_JFFS2_RUBIN=y
283CONFIG_JFFS2_CMODE_PRIORITY=y
100CONFIG_SQUASHFS=y 284CONFIG_SQUASHFS=y
285CONFIG_SQUASHFS_ZLIB=y
286CONFIG_SQUASHFS_LZO=y
287CONFIG_SQUASHFS_XZ=y
288CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
289CONFIG_NETWORK_FILESYSTEMS=y
101CONFIG_NFS_FS=y 290CONFIG_NFS_FS=y
102CONFIG_NFS_V3=y 291CONFIG_NFS_V3=y
292CONFIG_NFS_V4=y
293CONFIG_NFS_V4_1=y
294CONFIG_PNFS_FILE_LAYOUT=y
295CONFIG_PNFS_BLOCK=y
103CONFIG_ROOT_NFS=y 296CONFIG_ROOT_NFS=y
297CONFIG_NFS_USE_KERNEL_DNS=y
298CONFIG_NFS_USE_NEW_IDMAPPER=y
299CONFIG_NFSD=y
300CONFIG_NFSD_V2_ACL=y
301CONFIG_NFSD_V3=y
302CONFIG_NFSD_V3_ACL=y
303CONFIG_NFSD_V4=y
304CONFIG_LOCKD=y
305CONFIG_LOCKD_V4=y
306CONFIG_NFS_ACL_SUPPORT=y
307CONFIG_NFS_COMMON=y
308CONFIG_SUNRPC=y
309CONFIG_SUNRPC_GSS=y
310CONFIG_SUNRPC_BACKCHANNEL=y
311CONFIG_MSDOS_PARTITION=y
312CONFIG_NLS=y
313CONFIG_NLS_DEFAULT="iso8859-1"
104CONFIG_NLS_CODEPAGE_437=y 314CONFIG_NLS_CODEPAGE_437=y
105CONFIG_NLS_CODEPAGE_850=y 315CONFIG_NLS_CODEPAGE_850=y
106CONFIG_NLS_CODEPAGE_1250=y 316CONFIG_NLS_CODEPAGE_1250=y
317CONFIG_NLS_ASCII=y
107CONFIG_NLS_ISO8859_1=y 318CONFIG_NLS_ISO8859_1=y
108CONFIG_NLS_ISO8859_15=y 319CONFIG_NLS_ISO8859_15=y
109CONFIG_NLS_UTF8=y 320CONFIG_NLS_UTF8=y
110# CONFIG_ENABLE_WARN_DEPRECATED is not set 321CONFIG_HAVE_ARCH_KGDB=y
111# CONFIG_ENABLE_MUST_CHECK is not set 322CONFIG_EARLY_PRINTK=y
112CONFIG_STRIP_ASM_SYMS=y 323CONFIG_CMDLINE_BOOL=y
113CONFIG_DEBUG_KERNEL=y 324CONFIG_CMDLINE="noirqdebug rootwait root=/dev/sda1 rootfstype=ext4 console=ttyS0,115200 video=au1100fb:panel:CRT_800x600_16"
114# CONFIG_SCHED_DEBUG is not set
115# CONFIG_FTRACE is not set
116CONFIG_DEBUG_ZBOOT=y 325CONFIG_DEBUG_ZBOOT=y
117CONFIG_KEYS=y 326CONFIG_KEYS=y
118CONFIG_KEYS_DEBUG_PROC_KEYS=y 327CONFIG_KEYS_DEBUG_PROC_KEYS=y
328CONFIG_SECURITYFS=y
329CONFIG_DEFAULT_SECURITY_DAC=y
330CONFIG_DEFAULT_SECURITY=""
331CONFIG_CRYPTO=y
332CONFIG_CRYPTO_ALGAPI=y
333CONFIG_CRYPTO_ALGAPI2=y
334CONFIG_CRYPTO_AEAD2=y
335CONFIG_CRYPTO_BLKCIPHER=y
336CONFIG_CRYPTO_BLKCIPHER2=y
337CONFIG_CRYPTO_HASH=y
338CONFIG_CRYPTO_HASH2=y
339CONFIG_CRYPTO_RNG=y
340CONFIG_CRYPTO_RNG2=y
341CONFIG_CRYPTO_PCOMP2=y
342CONFIG_CRYPTO_MANAGER=y
343CONFIG_CRYPTO_MANAGER2=y
344CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
345CONFIG_CRYPTO_WORKQUEUE=y
346CONFIG_CRYPTO_ECB=y
347CONFIG_CRYPTO_SHA1=y
348CONFIG_CRYPTO_AES=y
349CONFIG_CRYPTO_ANSI_CPRNG=y
350CONFIG_BITREVERSE=y
351CONFIG_CRC_CCITT=y
352CONFIG_CRC16=y
353CONFIG_CRC_ITU_T=y
354CONFIG_CRC32=y
355CONFIG_ZLIB_INFLATE=y
356CONFIG_ZLIB_DEFLATE=y
357CONFIG_LZO_COMPRESS=y
358CONFIG_LZO_DECOMPRESS=y
359CONFIG_XZ_DEC=y
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
deleted file mode 100644
index c6b49938ee84..000000000000
--- a/arch/mips/configs/db1100_defconfig
+++ /dev/null
@@ -1,122 +0,0 @@
1CONFIG_MIPS_ALCHEMY=y
2CONFIG_MIPS_DB1100=y
3CONFIG_NO_HZ=y
4CONFIG_HIGH_RES_TIMERS=y
5CONFIG_HZ_100=y
6# CONFIG_SECCOMP is not set
7CONFIG_EXPERIMENTAL=y
8CONFIG_LOCALVERSION="-db1100"
9CONFIG_KERNEL_LZMA=y
10CONFIG_SYSVIPC=y
11CONFIG_POSIX_MQUEUE=y
12CONFIG_TINY_RCU=y
13CONFIG_LOG_BUF_SHIFT=14
14CONFIG_EXPERT=y
15# CONFIG_SYSCTL_SYSCALL is not set
16# CONFIG_KALLSYMS is not set
17# CONFIG_PCSPKR_PLATFORM is not set
18# CONFIG_COMPAT_BRK is not set
19CONFIG_SLAB=y
20CONFIG_MODULES=y
21CONFIG_MODULE_UNLOAD=y
22# CONFIG_LBDAF is not set
23# CONFIG_BLK_DEV_BSG is not set
24# CONFIG_IOSCHED_DEADLINE is not set
25# CONFIG_IOSCHED_CFQ is not set
26CONFIG_PCCARD=y
27CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
28CONFIG_PM=y
29CONFIG_PM_RUNTIME=y
30CONFIG_NET=y
31CONFIG_PACKET=y
32CONFIG_UNIX=y
33CONFIG_INET=y
34CONFIG_IP_MULTICAST=y
35CONFIG_IP_PNP=y
36CONFIG_IP_PNP_DHCP=y
37CONFIG_IP_PNP_BOOTP=y
38CONFIG_IP_PNP_RARP=y
39# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
40# CONFIG_INET_XFRM_MODE_TUNNEL is not set
41# CONFIG_INET_XFRM_MODE_BEET is not set
42# CONFIG_INET_DIAG is not set
43# CONFIG_IPV6 is not set
44# CONFIG_WIRELESS is not set
45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46CONFIG_MTD=y
47CONFIG_MTD_PARTITIONS=y
48CONFIG_MTD_CHAR=y
49CONFIG_MTD_BLOCK=y
50CONFIG_MTD_CFI=y
51CONFIG_MTD_CFI_AMDSTD=y
52CONFIG_MTD_PHYSMAP=y
53# CONFIG_BLK_DEV is not set
54# CONFIG_MISC_DEVICES is not set
55CONFIG_IDE=y
56CONFIG_IDE_TASK_IOCTL=y
57CONFIG_NETDEVICES=y
58CONFIG_MARVELL_PHY=y
59CONFIG_DAVICOM_PHY=y
60CONFIG_QSEMI_PHY=y
61CONFIG_LXT_PHY=y
62CONFIG_CICADA_PHY=y
63CONFIG_VITESSE_PHY=y
64CONFIG_SMSC_PHY=y
65CONFIG_BROADCOM_PHY=y
66CONFIG_ICPLUS_PHY=y
67CONFIG_REALTEK_PHY=y
68CONFIG_NATIONAL_PHY=y
69CONFIG_STE10XP=y
70CONFIG_LSI_ET1011C_PHY=y
71CONFIG_NET_ETHERNET=y
72CONFIG_MII=y
73CONFIG_MIPS_AU1X00_ENET=y
74# CONFIG_NETDEV_1000 is not set
75# CONFIG_NETDEV_10000 is not set
76# CONFIG_WLAN is not set
77# CONFIG_INPUT_MOUSEDEV is not set
78CONFIG_INPUT_EVDEV=y
79# CONFIG_INPUT_KEYBOARD is not set
80# CONFIG_INPUT_MOUSE is not set
81# CONFIG_SERIO is not set
82CONFIG_VT_HW_CONSOLE_BINDING=y
83CONFIG_SERIAL_8250=y
84CONFIG_SERIAL_8250_CONSOLE=y
85# CONFIG_LEGACY_PTYS is not set
86# CONFIG_HW_RANDOM is not set
87# CONFIG_HWMON is not set
88CONFIG_FB=y
89CONFIG_FB_AU1100=y
90# CONFIG_VGA_CONSOLE is not set
91CONFIG_FRAMEBUFFER_CONSOLE=y
92CONFIG_FONTS=y
93CONFIG_FONT_8x16=y
94# CONFIG_HID_SUPPORT is not set
95CONFIG_USB=y
96# CONFIG_USB_DEVICE_CLASS is not set
97CONFIG_USB_DYNAMIC_MINORS=y
98CONFIG_USB_SUSPEND=y
99CONFIG_USB_OHCI_HCD=y
100CONFIG_RTC_CLASS=y
101CONFIG_RTC_DRV_AU1XXX=y
102CONFIG_EXT2_FS=y
103# CONFIG_PROC_PAGE_MONITOR is not set
104CONFIG_TMPFS=y
105CONFIG_JFFS2_FS=y
106CONFIG_JFFS2_SUMMARY=y
107CONFIG_JFFS2_FS_XATTR=y
108CONFIG_JFFS2_COMPRESSION_OPTIONS=y
109CONFIG_JFFS2_LZO=y
110CONFIG_JFFS2_RUBIN=y
111CONFIG_SQUASHFS=y
112CONFIG_NFS_FS=y
113CONFIG_NFS_V3=y
114CONFIG_ROOT_NFS=y
115CONFIG_STRIP_ASM_SYMS=y
116CONFIG_DEBUG_KERNEL=y
117# CONFIG_SCHED_DEBUG is not set
118# CONFIG_FTRACE is not set
119CONFIG_DEBUG_ZBOOT=y
120CONFIG_KEYS=y
121CONFIG_KEYS_DEBUG_PROC_KEYS=y
122CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/db1300_defconfig b/arch/mips/configs/db1300_defconfig
new file mode 100644
index 000000000000..c38b190151c4
--- /dev/null
+++ b/arch/mips/configs/db1300_defconfig
@@ -0,0 +1,391 @@
1CONFIG_MIPS=y
2CONFIG_MIPS_ALCHEMY=y
3CONFIG_ALCHEMY_GPIOINT_AU1300=y
4CONFIG_MIPS_DB1300=y
5CONFIG_SOC_AU1300=y
6CONFIG_RWSEM_GENERIC_SPINLOCK=y
7CONFIG_ARCH_SUPPORTS_OPROFILE=y
8CONFIG_GENERIC_HWEIGHT=y
9CONFIG_GENERIC_CALIBRATE_DELAY=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_GENERIC_CMOS_UPDATE=y
12CONFIG_SCHED_OMIT_FRAME_POINTER=y
13CONFIG_CEVT_R4K_LIB=y
14CONFIG_CSRC_R4K_LIB=y
15CONFIG_DMA_COHERENT=y
16CONFIG_SYS_HAS_EARLY_PRINTK=y
17CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
18CONFIG_GENERIC_GPIO=y
19CONFIG_CPU_LITTLE_ENDIAN=y
20CONFIG_SYS_SUPPORTS_APM_EMULATION=y
21CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
22CONFIG_IRQ_CPU=y
23CONFIG_MIPS_L1_CACHE_SHIFT=5
24CONFIG_CPU_MIPS32_R1=y
25CONFIG_SYS_SUPPORTS_ZBOOT=y
26CONFIG_SYS_HAS_CPU_MIPS32_R1=y
27CONFIG_CPU_MIPS32=y
28CONFIG_CPU_MIPSR1=y
29CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
30CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
31CONFIG_HARDWARE_WATCHPOINTS=y
32CONFIG_32BIT=y
33CONFIG_PAGE_SIZE_4KB=y
34CONFIG_FORCE_MAX_ZONEORDER=11
35CONFIG_CPU_HAS_PREFETCH=y
36CONFIG_MIPS_MT_DISABLED=y
37CONFIG_64BIT_PHYS_ADDR=y
38CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
39CONFIG_CPU_HAS_SYNC=y
40CONFIG_CPU_SUPPORTS_HIGHMEM=y
41CONFIG_ARCH_FLATMEM_ENABLE=y
42CONFIG_ARCH_POPULATES_NODE_MAP=y
43CONFIG_SELECT_MEMORY_MODEL=y
44CONFIG_FLATMEM_MANUAL=y
45CONFIG_FLATMEM=y
46CONFIG_FLAT_NODE_MEM_MAP=y
47CONFIG_PAGEFLAGS_EXTENDED=y
48CONFIG_SPLIT_PTLOCK_CPUS=4
49CONFIG_COMPACTION=y
50CONFIG_MIGRATION=y
51CONFIG_PHYS_ADDR_T_64BIT=y
52CONFIG_ZONE_DMA_FLAG=0
53CONFIG_VIRT_TO_BUS=y
54CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
55CONFIG_NEED_PER_CPU_KM=y
56CONFIG_TICK_ONESHOT=y
57CONFIG_NO_HZ=y
58CONFIG_HIGH_RES_TIMERS=y
59CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
60CONFIG_HZ_100=y
61CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
62CONFIG_HZ=100
63CONFIG_PREEMPT_NONE=y
64CONFIG_LOCKDEP_SUPPORT=y
65CONFIG_STACKTRACE_SUPPORT=y
66CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
67CONFIG_CONSTRUCTORS=y
68CONFIG_HAVE_IRQ_WORK=y
69CONFIG_EXPERIMENTAL=y
70CONFIG_BROKEN_ON_SMP=y
71CONFIG_INIT_ENV_ARG_LIMIT=32
72CONFIG_CROSS_COMPILE=""
73CONFIG_LOCALVERSION="-db1300"
74CONFIG_LOCALVERSION_AUTO=y
75CONFIG_HAVE_KERNEL_GZIP=y
76CONFIG_HAVE_KERNEL_BZIP2=y
77CONFIG_HAVE_KERNEL_LZMA=y
78CONFIG_HAVE_KERNEL_LZO=y
79CONFIG_KERNEL_LZMA=y
80CONFIG_SWAP=y
81CONFIG_SYSVIPC=y
82CONFIG_SYSVIPC_SYSCTL=y
83CONFIG_POSIX_MQUEUE=y
84CONFIG_POSIX_MQUEUE_SYSCTL=y
85CONFIG_FHANDLE=y
86CONFIG_HAVE_GENERIC_HARDIRQS=y
87CONFIG_GENERIC_HARDIRQS=y
88CONFIG_GENERIC_IRQ_PROBE=y
89CONFIG_GENERIC_IRQ_SHOW=y
90CONFIG_TINY_RCU=y
91CONFIG_LOG_BUF_SHIFT=19
92CONFIG_NAMESPACES=y
93CONFIG_UTS_NS=y
94CONFIG_IPC_NS=y
95CONFIG_USER_NS=y
96CONFIG_PID_NS=y
97CONFIG_NET_NS=y
98CONFIG_SYSCTL=y
99CONFIG_ANON_INODES=y
100CONFIG_EXPERT=y
101CONFIG_SYSCTL_SYSCALL=y
102CONFIG_KALLSYMS=y
103CONFIG_KALLSYMS_ALL=y
104CONFIG_HOTPLUG=y
105CONFIG_PRINTK=y
106CONFIG_BUG=y
107CONFIG_ELF_CORE=y
108CONFIG_BASE_FULL=y
109CONFIG_FUTEX=y
110CONFIG_EPOLL=y
111CONFIG_SIGNALFD=y
112CONFIG_TIMERFD=y
113CONFIG_EVENTFD=y
114CONFIG_SHMEM=y
115CONFIG_AIO=y
116CONFIG_EMBEDDED=y
117CONFIG_HAVE_PERF_EVENTS=y
118CONFIG_PERF_USE_VMALLOC=y
119CONFIG_SLAB=y
120CONFIG_HAVE_OPROFILE=y
121CONFIG_HAVE_KPROBES=y
122CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_DMA_ATTRS=y
124CONFIG_HAVE_DMA_API_DEBUG=y
125CONFIG_HAVE_ARCH_JUMP_LABEL=y
126CONFIG_HAVE_GENERIC_DMA_COHERENT=y
127CONFIG_SLABINFO=y
128CONFIG_RT_MUTEXES=y
129CONFIG_BASE_SMALL=0
130CONFIG_BLOCK=y
131CONFIG_LBDAF=y
132CONFIG_BLK_DEV_BSG=y
133CONFIG_IOSCHED_NOOP=y
134CONFIG_DEFAULT_NOOP=y
135CONFIG_DEFAULT_IOSCHED="noop"
136CONFIG_INLINE_SPIN_UNLOCK=y
137CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
138CONFIG_INLINE_READ_UNLOCK=y
139CONFIG_INLINE_READ_UNLOCK_IRQ=y
140CONFIG_INLINE_WRITE_UNLOCK=y
141CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
142CONFIG_MMU=y
143CONFIG_PCCARD=y
144CONFIG_PCMCIA=y
145CONFIG_PCMCIA_LOAD_CIS=y
146CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
147CONFIG_BINFMT_ELF=y
148CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
149CONFIG_TRAD_SIGNALS=y
150CONFIG_ARCH_HIBERNATION_POSSIBLE=y
151CONFIG_ARCH_SUSPEND_POSSIBLE=y
152CONFIG_NET=y
153CONFIG_PACKET=y
154CONFIG_UNIX=y
155CONFIG_XFRM=y
156CONFIG_INET=y
157CONFIG_IP_MULTICAST=y
158CONFIG_IP_PNP=y
159CONFIG_IP_PNP_DHCP=y
160CONFIG_IP_PNP_BOOTP=y
161CONFIG_IP_PNP_RARP=y
162CONFIG_INET_TUNNEL=y
163CONFIG_TCP_CONG_CUBIC=y
164CONFIG_DEFAULT_TCP_CONG="cubic"
165CONFIG_IPV6=y
166CONFIG_INET6_XFRM_MODE_TRANSPORT=y
167CONFIG_INET6_XFRM_MODE_TUNNEL=y
168CONFIG_INET6_XFRM_MODE_BEET=y
169CONFIG_IPV6_SIT=y
170CONFIG_IPV6_NDISC_NODETYPE=y
171CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
172CONFIG_STANDALONE=y
173CONFIG_PREVENT_FIRMWARE_BUILD=y
174CONFIG_FW_LOADER=y
175CONFIG_FIRMWARE_IN_KERNEL=y
176CONFIG_EXTRA_FIRMWARE=""
177CONFIG_MTD=y
178CONFIG_MTD_CMDLINE_PARTS=y
179CONFIG_MTD_CHAR=y
180CONFIG_MTD_BLKDEVS=y
181CONFIG_MTD_BLOCK=y
182CONFIG_MTD_CFI=y
183CONFIG_MTD_GEN_PROBE=y
184CONFIG_MTD_MAP_BANK_WIDTH_1=y
185CONFIG_MTD_MAP_BANK_WIDTH_2=y
186CONFIG_MTD_MAP_BANK_WIDTH_4=y
187CONFIG_MTD_CFI_I1=y
188CONFIG_MTD_CFI_I2=y
189CONFIG_MTD_CFI_AMDSTD=y
190CONFIG_MTD_CFI_UTIL=y
191CONFIG_MTD_PHYSMAP=y
192CONFIG_MTD_NAND_ECC=y
193CONFIG_MTD_NAND=y
194CONFIG_MTD_NAND_IDS=y
195CONFIG_MTD_NAND_PLATFORM=y
196CONFIG_BLK_DEV=y
197CONFIG_BLK_DEV_LOOP=y
198CONFIG_BLK_DEV_UB=y
199CONFIG_HAVE_IDE=y
200CONFIG_IDE=y
201CONFIG_IDE_GD=y
202CONFIG_IDE_GD_ATA=y
203CONFIG_BLK_DEV_IDECS=y
204CONFIG_IDE_TASK_IOCTL=y
205CONFIG_IDE_PROC_FS=y
206CONFIG_BLK_DEV_PLATFORM=y
207CONFIG_SCSI_MOD=y
208CONFIG_NETDEVICES=y
209CONFIG_MII=y
210CONFIG_PHYLIB=y
211CONFIG_SMSC_PHY=y
212CONFIG_NET_ETHERNET=y
213CONFIG_SMSC911X=y
214CONFIG_INPUT=y
215CONFIG_INPUT_EVDEV=y
216CONFIG_INPUT_KEYBOARD=y
217CONFIG_KEYBOARD_GPIO=y
218CONFIG_INPUT_TOUCHSCREEN=y
219CONFIG_TOUCHSCREEN_WM97XX=y
220CONFIG_TOUCHSCREEN_WM9712=y
221CONFIG_TOUCHSCREEN_WM9713=y
222CONFIG_INPUT_MISC=y
223CONFIG_INPUT_UINPUT=y
224CONFIG_VT=y
225CONFIG_CONSOLE_TRANSLATIONS=y
226CONFIG_VT_CONSOLE=y
227CONFIG_HW_CONSOLE=y
228CONFIG_VT_HW_CONSOLE_BINDING=y
229CONFIG_UNIX98_PTYS=y
230CONFIG_SERIAL_8250=y
231CONFIG_SERIAL_8250_CONSOLE=y
232CONFIG_SERIAL_8250_NR_UARTS=4
233CONFIG_SERIAL_8250_RUNTIME_UARTS=4
234CONFIG_SERIAL_CORE=y
235CONFIG_SERIAL_CORE_CONSOLE=y
236CONFIG_I2C=y
237CONFIG_I2C_BOARDINFO=y
238CONFIG_I2C_CHARDEV=y
239CONFIG_I2C_SMBUS=y
240CONFIG_I2C_AU1550=y
241CONFIG_SPI=y
242CONFIG_SPI_MASTER=y
243CONFIG_SPI_AU1550=y
244CONFIG_SPI_BITBANG=y
245CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
246CONFIG_HWMON=y
247CONFIG_HWMON_VID=y
248CONFIG_SENSORS_ADM1025=y
249CONFIG_FB=y
250CONFIG_FB_AU1200=y
251CONFIG_DUMMY_CONSOLE=y
252CONFIG_FRAMEBUFFER_CONSOLE=y
253CONFIG_FONTS=y
254CONFIG_FONT_ACORN_8x8=y
255CONFIG_LOGO=y
256CONFIG_LOGO_LINUX_CLUT224=y
257CONFIG_SOUND=y
258CONFIG_SND=y
259CONFIG_SND_TIMER=y
260CONFIG_SND_PCM=y
261CONFIG_SND_JACK=y
262CONFIG_SND_HRTIMER=y
263CONFIG_SND_DYNAMIC_MINORS=y
264CONFIG_SND_VERBOSE_PROCFS=y
265CONFIG_SND_VERBOSE_PRINTK=y
266CONFIG_SND_VMASTER=y
267CONFIG_SND_AC97_CODEC=y
268CONFIG_SND_SOC=y
269CONFIG_SND_SOC_CACHE_LZO=y
270CONFIG_SND_SOC_AC97_BUS=y
271CONFIG_SND_SOC_AU1XPSC=y
272CONFIG_SND_SOC_AU1XPSC_I2S=y
273CONFIG_SND_SOC_AU1XPSC_AC97=y
274CONFIG_SND_SOC_DB1300=y
275CONFIG_SND_SOC_I2C_AND_SPI=y
276CONFIG_SND_SOC_WM8731=y
277CONFIG_SND_SOC_WM9712=y
278CONFIG_AC97_BUS=y
279CONFIG_HID_SUPPORT=y
280CONFIG_HID=y
281CONFIG_HIDRAW=y
282CONFIG_USB_HID=y
283CONFIG_USB_HIDDEV=y
284CONFIG_USB_SUPPORT=y
285CONFIG_USB_ARCH_HAS_HCD=y
286CONFIG_USB_ARCH_HAS_OHCI=y
287CONFIG_USB_ARCH_HAS_EHCI=y
288CONFIG_USB=y
289CONFIG_USB_DYNAMIC_MINORS=y
290CONFIG_USB_EHCI_HCD=y
291CONFIG_USB_EHCI_ROOT_HUB_TT=y
292CONFIG_USB_EHCI_TT_NEWSCHED=y
293CONFIG_USB_OHCI_HCD=y
294CONFIG_USB_OHCI_LITTLE_ENDIAN=y
295CONFIG_RTC_LIB=y
296CONFIG_RTC_CLASS=y
297CONFIG_RTC_HCTOSYS=y
298CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
299CONFIG_RTC_INTF_SYSFS=y
300CONFIG_RTC_INTF_PROC=y
301CONFIG_RTC_INTF_DEV=y
302CONFIG_RTC_INTF_DEV_UIE_EMUL=y
303CONFIG_RTC_DRV_AU1XXX=y
304CONFIG_EXT2_FS=y
305CONFIG_FS_POSIX_ACL=y
306CONFIG_EXPORTFS=y
307CONFIG_FILE_LOCKING=y
308CONFIG_FSNOTIFY=y
309CONFIG_DNOTIFY=y
310CONFIG_INOTIFY_USER=y
311CONFIG_GENERIC_ACL=y
312CONFIG_FAT_FS=y
313CONFIG_VFAT_FS=y
314CONFIG_FAT_DEFAULT_CODEPAGE=437
315CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
316CONFIG_PROC_FS=y
317CONFIG_PROC_SYSCTL=y
318CONFIG_PROC_PAGE_MONITOR=y
319CONFIG_SYSFS=y
320CONFIG_TMPFS=y
321CONFIG_TMPFS_POSIX_ACL=y
322CONFIG_TMPFS_XATTR=y
323CONFIG_MISC_FILESYSTEMS=y
324CONFIG_JFFS2_FS=y
325CONFIG_JFFS2_FS_DEBUG=0
326CONFIG_JFFS2_FS_WRITEBUFFER=y
327CONFIG_JFFS2_SUMMARY=y
328CONFIG_JFFS2_FS_XATTR=y
329CONFIG_JFFS2_FS_POSIX_ACL=y
330CONFIG_JFFS2_FS_SECURITY=y
331CONFIG_JFFS2_COMPRESSION_OPTIONS=y
332CONFIG_JFFS2_ZLIB=y
333CONFIG_JFFS2_LZO=y
334CONFIG_JFFS2_RTIME=y
335CONFIG_JFFS2_RUBIN=y
336CONFIG_JFFS2_CMODE_PRIORITY=y
337CONFIG_SQUASHFS=y
338CONFIG_SQUASHFS_XZ=y
339CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
340CONFIG_NETWORK_FILESYSTEMS=y
341CONFIG_NFS_FS=y
342CONFIG_NFS_V3=y
343CONFIG_ROOT_NFS=y
344CONFIG_LOCKD=y
345CONFIG_LOCKD_V4=y
346CONFIG_NFS_COMMON=y
347CONFIG_SUNRPC=y
348CONFIG_MSDOS_PARTITION=y
349CONFIG_NLS=y
350CONFIG_NLS_DEFAULT="iso8859-1"
351CONFIG_NLS_CODEPAGE_437=y
352CONFIG_NLS_CODEPAGE_850=y
353CONFIG_NLS_ASCII=y
354CONFIG_NLS_ISO8859_1=y
355CONFIG_NLS_ISO8859_15=y
356CONFIG_NLS_UTF8=y
357CONFIG_TRACE_IRQFLAGS_SUPPORT=y
358CONFIG_PRINTK_TIME=y
359CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
360CONFIG_ENABLE_WARN_DEPRECATED=y
361CONFIG_ENABLE_MUST_CHECK=y
362CONFIG_FRAME_WARN=1024
363CONFIG_MAGIC_SYSRQ=y
364CONFIG_STRIP_ASM_SYMS=y
365CONFIG_HAVE_FUNCTION_TRACER=y
366CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
367CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
368CONFIG_HAVE_DYNAMIC_FTRACE=y
369CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
370CONFIG_HAVE_C_RECORDMCOUNT=y
371CONFIG_TRACING_SUPPORT=y
372CONFIG_HAVE_ARCH_KGDB=y
373CONFIG_EARLY_PRINTK=y
374CONFIG_CMDLINE_BOOL=y
375CONFIG_CMDLINE="video=au1200fb:panel:bs console=tty console=ttyS2,115200"
376CONFIG_DEBUG_ZBOOT=y
377CONFIG_DEFAULT_SECURITY_DAC=y
378CONFIG_DEFAULT_SECURITY=""
379CONFIG_CRYPTO=y
380CONFIG_BITREVERSE=y
381CONFIG_CRC32=y
382CONFIG_ZLIB_INFLATE=y
383CONFIG_ZLIB_DEFLATE=y
384CONFIG_LZO_COMPRESS=y
385CONFIG_LZO_DECOMPRESS=y
386CONFIG_XZ_DEC=y
387CONFIG_HAS_IOMEM=y
388CONFIG_HAS_IOPORT=y
389CONFIG_HAS_DMA=y
390CONFIG_NLATTR=y
391CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
deleted file mode 100644
index b6e21c7cb6bd..000000000000
--- a/arch/mips/configs/db1500_defconfig
+++ /dev/null
@@ -1,128 +0,0 @@
1CONFIG_MIPS_ALCHEMY=y
2CONFIG_MIPS_DB1500=y
3CONFIG_CPU_LITTLE_ENDIAN=y
4CONFIG_NO_HZ=y
5CONFIG_HIGH_RES_TIMERS=y
6CONFIG_HZ_100=y
7# CONFIG_SECCOMP is not set
8CONFIG_EXPERIMENTAL=y
9CONFIG_LOCALVERSION="-db1500"
10CONFIG_KERNEL_LZMA=y
11CONFIG_SYSVIPC=y
12CONFIG_LOG_BUF_SHIFT=14
13CONFIG_EXPERT=y
14# CONFIG_KALLSYMS is not set
15# CONFIG_PCSPKR_PLATFORM is not set
16# CONFIG_VM_EVENT_COUNTERS is not set
17# CONFIG_COMPAT_BRK is not set
18CONFIG_SLAB=y
19CONFIG_MODULES=y
20CONFIG_MODULE_UNLOAD=y
21# CONFIG_IOSCHED_DEADLINE is not set
22# CONFIG_IOSCHED_CFQ is not set
23CONFIG_PCI=y
24CONFIG_PCCARD=y
25# CONFIG_CARDBUS is not set
26CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
27CONFIG_PM=y
28CONFIG_PM_RUNTIME=y
29CONFIG_NET=y
30CONFIG_PACKET=y
31CONFIG_UNIX=y
32CONFIG_INET=y
33CONFIG_IP_MULTICAST=y
34CONFIG_IP_PNP=y
35CONFIG_IP_PNP_DHCP=y
36CONFIG_IP_PNP_BOOTP=y
37CONFIG_IP_PNP_RARP=y
38# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
39# CONFIG_INET_XFRM_MODE_TUNNEL is not set
40# CONFIG_INET_XFRM_MODE_BEET is not set
41# CONFIG_INET_DIAG is not set
42# CONFIG_IPV6 is not set
43# CONFIG_WIRELESS is not set
44CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
45CONFIG_MTD=y
46CONFIG_MTD_PARTITIONS=y
47CONFIG_MTD_CMDLINE_PARTS=y
48CONFIG_MTD_CHAR=y
49CONFIG_MTD_BLOCK=y
50CONFIG_MTD_CFI=y
51CONFIG_MTD_CFI_INTELEXT=y
52CONFIG_MTD_CFI_AMDSTD=y
53CONFIG_MTD_PHYSMAP=y
54# CONFIG_MISC_DEVICES is not set
55CONFIG_IDE=y
56CONFIG_BLK_DEV_IDECS=y
57# CONFIG_IDEPCI_PCIBUS_ORDER is not set
58CONFIG_BLK_DEV_HPT366=y
59CONFIG_NETDEVICES=y
60CONFIG_MARVELL_PHY=y
61CONFIG_DAVICOM_PHY=y
62CONFIG_QSEMI_PHY=y
63CONFIG_LXT_PHY=y
64CONFIG_CICADA_PHY=y
65CONFIG_VITESSE_PHY=y
66CONFIG_SMSC_PHY=y
67CONFIG_BROADCOM_PHY=y
68CONFIG_ICPLUS_PHY=y
69CONFIG_REALTEK_PHY=y
70CONFIG_NATIONAL_PHY=y
71CONFIG_STE10XP=y
72CONFIG_LSI_ET1011C_PHY=y
73CONFIG_NET_ETHERNET=y
74CONFIG_MII=y
75CONFIG_MIPS_AU1X00_ENET=y
76# CONFIG_NETDEV_1000 is not set
77# CONFIG_NETDEV_10000 is not set
78# CONFIG_WLAN is not set
79# CONFIG_INPUT_MOUSEDEV is not set
80CONFIG_INPUT_EVDEV=y
81# CONFIG_INPUT_KEYBOARD is not set
82# CONFIG_INPUT_MOUSE is not set
83# CONFIG_SERIO is not set
84CONFIG_SERIAL_8250=y
85CONFIG_SERIAL_8250_CONSOLE=y
86# CONFIG_SERIAL_8250_PCI is not set
87# CONFIG_LEGACY_PTYS is not set
88# CONFIG_HW_RANDOM is not set
89# CONFIG_HWMON is not set
90# CONFIG_VGA_ARB is not set
91# CONFIG_VGA_CONSOLE is not set
92# CONFIG_HID_SUPPORT is not set
93CONFIG_USB=y
94# CONFIG_USB_DEVICE_CLASS is not set
95CONFIG_USB_DYNAMIC_MINORS=y
96CONFIG_USB_SUSPEND=y
97CONFIG_USB_OHCI_HCD=y
98CONFIG_RTC_CLASS=y
99CONFIG_RTC_DRV_AU1XXX=y
100CONFIG_EXT2_FS=y
101# CONFIG_PROC_PAGE_MONITOR is not set
102CONFIG_TMPFS=y
103CONFIG_JFFS2_FS=y
104CONFIG_JFFS2_SUMMARY=y
105CONFIG_JFFS2_FS_XATTR=y
106CONFIG_JFFS2_COMPRESSION_OPTIONS=y
107CONFIG_JFFS2_LZO=y
108CONFIG_JFFS2_RUBIN=y
109CONFIG_SQUASHFS=y
110CONFIG_NFS_FS=y
111CONFIG_NFS_V3=y
112CONFIG_ROOT_NFS=y
113CONFIG_NLS_CODEPAGE_437=y
114CONFIG_NLS_CODEPAGE_850=y
115CONFIG_NLS_CODEPAGE_1250=y
116CONFIG_NLS_ASCII=y
117CONFIG_NLS_ISO8859_1=y
118CONFIG_NLS_ISO8859_15=y
119CONFIG_NLS_UTF8=y
120CONFIG_STRIP_ASM_SYMS=y
121CONFIG_DEBUG_KERNEL=y
122# CONFIG_SCHED_DEBUG is not set
123# CONFIG_RCU_CPU_STALL_DETECTOR is not set
124# CONFIG_FTRACE is not set
125CONFIG_DEBUG_ZBOOT=y
126CONFIG_KEYS=y
127CONFIG_KEYS_DEBUG_PROC_KEYS=y
128CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 798a553c9e80..36cda27725e7 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -1,145 +1,262 @@
1CONFIG_MIPS=y
1CONFIG_MIPS_ALCHEMY=y 2CONFIG_MIPS_ALCHEMY=y
2CONFIG_MIPS_DB1550=y 3CONFIG_MIPS_DB1550=y
4CONFIG_SCHED_OMIT_FRAME_POINTER=y
5CONFIG_GENERIC_GPIO=y
6CONFIG_TICK_ONESHOT=y
3CONFIG_NO_HZ=y 7CONFIG_NO_HZ=y
4CONFIG_HIGH_RES_TIMERS=y 8CONFIG_HIGH_RES_TIMERS=y
5CONFIG_HZ_100=y 9CONFIG_HZ_100=y
6# CONFIG_SECCOMP is not set 10CONFIG_HZ=100
7CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
12CONFIG_BROKEN_ON_SMP=y
13CONFIG_INIT_ENV_ARG_LIMIT=32
8CONFIG_LOCALVERSION="-db1550" 14CONFIG_LOCALVERSION="-db1550"
15CONFIG_LOCALVERSION_AUTO=y
9CONFIG_KERNEL_LZMA=y 16CONFIG_KERNEL_LZMA=y
17CONFIG_DEFAULT_HOSTNAME="db1550"
18CONFIG_SWAP=y
10CONFIG_SYSVIPC=y 19CONFIG_SYSVIPC=y
20CONFIG_SYSVIPC_SYSCTL=y
11CONFIG_POSIX_MQUEUE=y 21CONFIG_POSIX_MQUEUE=y
22CONFIG_POSIX_MQUEUE_SYSCTL=y
23CONFIG_FHANDLE=y
24CONFIG_AUDIT=y
12CONFIG_TINY_RCU=y 25CONFIG_TINY_RCU=y
13CONFIG_LOG_BUF_SHIFT=14 26CONFIG_LOG_BUF_SHIFT=18
27CONFIG_NAMESPACES=y
28CONFIG_UTS_NS=y
29CONFIG_IPC_NS=y
30CONFIG_USER_NS=y
31CONFIG_PID_NS=y
32CONFIG_NET_NS=y
14CONFIG_EXPERT=y 33CONFIG_EXPERT=y
15# CONFIG_SYSCTL_SYSCALL is not set 34CONFIG_HOTPLUG=y
16# CONFIG_KALLSYMS is not set 35CONFIG_PRINTK=y
17# CONFIG_PCSPKR_PLATFORM is not set 36CONFIG_BUG=y
18# CONFIG_VM_EVENT_COUNTERS is not set 37CONFIG_ELF_CORE=y
19# CONFIG_COMPAT_BRK is not set 38CONFIG_BASE_FULL=y
39CONFIG_FUTEX=y
40CONFIG_EPOLL=y
41CONFIG_SIGNALFD=y
42CONFIG_TIMERFD=y
43CONFIG_EVENTFD=y
44CONFIG_SHMEM=y
45CONFIG_AIO=y
46CONFIG_EMBEDDED=y
47CONFIG_PCI_QUIRKS=y
20CONFIG_SLAB=y 48CONFIG_SLAB=y
21CONFIG_MODULES=y 49CONFIG_BLOCK=y
22CONFIG_MODULE_UNLOAD=y 50CONFIG_LBDAF=y
23# CONFIG_IOSCHED_DEADLINE is not set 51CONFIG_BLK_DEV_BSG=y
24# CONFIG_IOSCHED_CFQ is not set 52CONFIG_BLK_DEV_BSGLIB=y
53CONFIG_IOSCHED_NOOP=y
54CONFIG_DEFAULT_NOOP=y
55CONFIG_DEFAULT_IOSCHED="noop"
25CONFIG_PCI=y 56CONFIG_PCI=y
26CONFIG_PCCARD=y 57CONFIG_PCCARD=y
27# CONFIG_CARDBUS is not set 58CONFIG_PCMCIA=y
59CONFIG_PCMCIA_LOAD_CIS=y
28CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y 60CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
29CONFIG_PM=y 61CONFIG_BINFMT_ELF=y
62CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
63CONFIG_BINFMT_MISC=y
64CONFIG_SUSPEND=y
65CONFIG_SUSPEND_FREEZER=y
66CONFIG_PM_SLEEP=y
30CONFIG_PM_RUNTIME=y 67CONFIG_PM_RUNTIME=y
68CONFIG_PM=y
31CONFIG_NET=y 69CONFIG_NET=y
32CONFIG_PACKET=y 70CONFIG_PACKET=y
33CONFIG_UNIX=y 71CONFIG_UNIX=y
72CONFIG_XFRM=y
34CONFIG_INET=y 73CONFIG_INET=y
35CONFIG_IP_MULTICAST=y 74CONFIG_IP_MULTICAST=y
36CONFIG_IP_PNP=y 75CONFIG_IP_PNP=y
37CONFIG_IP_PNP_DHCP=y 76CONFIG_IP_PNP_DHCP=y
38CONFIG_IP_PNP_BOOTP=y 77CONFIG_IP_PNP_BOOTP=y
39CONFIG_IP_PNP_RARP=y 78CONFIG_IP_PNP_RARP=y
40# CONFIG_INET_XFRM_MODE_TRANSPORT is not set 79CONFIG_INET_TUNNEL=y
41# CONFIG_INET_XFRM_MODE_TUNNEL is not set 80CONFIG_INET_LRO=y
42# CONFIG_INET_XFRM_MODE_BEET is not set 81CONFIG_TCP_CONG_CUBIC=y
43# CONFIG_INET_DIAG is not set 82CONFIG_DEFAULT_TCP_CONG="cubic"
44# CONFIG_IPV6 is not set 83CONFIG_IPV6=y
45# CONFIG_WIRELESS is not set 84CONFIG_INET6_XFRM_MODE_TRANSPORT=y
46CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 85CONFIG_INET6_XFRM_MODE_TUNNEL=y
86CONFIG_INET6_XFRM_MODE_BEET=y
87CONFIG_IPV6_SIT=y
88CONFIG_IPV6_NDISC_NODETYPE=y
89CONFIG_DNS_RESOLVER=y
90CONFIG_UEVENT_HELPER_PATH=""
91CONFIG_STANDALONE=y
92CONFIG_PREVENT_FIRMWARE_BUILD=y
93CONFIG_FW_LOADER=y
94CONFIG_FIRMWARE_IN_KERNEL=y
47CONFIG_MTD=y 95CONFIG_MTD=y
48CONFIG_MTD_PARTITIONS=y
49CONFIG_MTD_CHAR=y 96CONFIG_MTD_CHAR=y
97CONFIG_MTD_BLKDEVS=y
50CONFIG_MTD_BLOCK=y 98CONFIG_MTD_BLOCK=y
51CONFIG_MTD_CFI=y 99CONFIG_MTD_CFI=y
100CONFIG_MTD_GEN_PROBE=y
101CONFIG_MTD_MAP_BANK_WIDTH_1=y
102CONFIG_MTD_MAP_BANK_WIDTH_2=y
103CONFIG_MTD_MAP_BANK_WIDTH_4=y
104CONFIG_MTD_CFI_I1=y
105CONFIG_MTD_CFI_I2=y
52CONFIG_MTD_CFI_AMDSTD=y 106CONFIG_MTD_CFI_AMDSTD=y
107CONFIG_MTD_CFI_UTIL=y
53CONFIG_MTD_PHYSMAP=y 108CONFIG_MTD_PHYSMAP=y
109CONFIG_MTD_M25P80=y
110CONFIG_MTD_NAND_ECC=y
54CONFIG_MTD_NAND=y 111CONFIG_MTD_NAND=y
55CONFIG_MTD_NAND_AU1550=y 112CONFIG_MTD_NAND_IDS=y
56CONFIG_BLK_DEV_UB=y 113CONFIG_MTD_NAND_PLATFORM=y
57# CONFIG_MISC_DEVICES is not set 114CONFIG_MISC_DEVICES=y
58CONFIG_IDE=y 115CONFIG_EEPROM_AT24=y
59CONFIG_BLK_DEV_IDECS=y 116CONFIG_SCSI_MOD=y
60CONFIG_BLK_DEV_IDECD=y 117CONFIG_SCSI=y
61# CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS is not set 118CONFIG_SCSI_DMA=y
62CONFIG_IDE_TASK_IOCTL=y 119CONFIG_BLK_DEV_SD=y
63# CONFIG_IDEPCI_PCIBUS_ORDER is not set 120CONFIG_CHR_DEV_SG=y
64CONFIG_BLK_DEV_HPT366=y 121CONFIG_SCSI_MULTI_LUN=y
122CONFIG_SCSI_SCAN_ASYNC=y
123CONFIG_ATA=y
124CONFIG_ATA_SFF=y
125CONFIG_ATA_BMDMA=y
126CONFIG_PATA_HPT37X=y
127CONFIG_PATA_PCMCIA=y
128CONFIG_MD=y
129CONFIG_BLK_DEV_DM=y
65CONFIG_NETDEVICES=y 130CONFIG_NETDEVICES=y
66CONFIG_MARVELL_PHY=y
67CONFIG_DAVICOM_PHY=y
68CONFIG_QSEMI_PHY=y
69CONFIG_LXT_PHY=y
70CONFIG_CICADA_PHY=y
71CONFIG_VITESSE_PHY=y
72CONFIG_SMSC_PHY=y
73CONFIG_BROADCOM_PHY=y
74CONFIG_ICPLUS_PHY=y
75CONFIG_REALTEK_PHY=y
76CONFIG_NATIONAL_PHY=y
77CONFIG_STE10XP=y
78CONFIG_LSI_ET1011C_PHY=y
79CONFIG_NET_ETHERNET=y
80CONFIG_MII=y 131CONFIG_MII=y
132CONFIG_PHYLIB=y
133CONFIG_NET_ETHERNET=y
81CONFIG_MIPS_AU1X00_ENET=y 134CONFIG_MIPS_AU1X00_ENET=y
82# CONFIG_NETDEV_1000 is not set 135CONFIG_NET_PCMCIA=y
83# CONFIG_NETDEV_10000 is not set 136CONFIG_PCMCIA_3C589=y
84# CONFIG_WLAN is not set 137CONFIG_PCMCIA_PCNET=y
85# CONFIG_INPUT_MOUSEDEV is not set 138CONFIG_INPUT=y
86CONFIG_INPUT_EVDEV=y 139CONFIG_INPUT_EVDEV=y
87# CONFIG_INPUT_KEYBOARD is not set 140CONFIG_VT=y
88# CONFIG_INPUT_MOUSE is not set 141CONFIG_CONSOLE_TRANSLATIONS=y
89# CONFIG_SERIO is not set 142CONFIG_VT_CONSOLE=y
143CONFIG_HW_CONSOLE=y
144CONFIG_UNIX98_PTYS=y
145CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
146CONFIG_DEVKMEM=y
90CONFIG_SERIAL_8250=y 147CONFIG_SERIAL_8250=y
91CONFIG_SERIAL_8250_CONSOLE=y 148CONFIG_SERIAL_8250_CONSOLE=y
92# CONFIG_LEGACY_PTYS is not set 149CONFIG_SERIAL_8250_NR_UARTS=4
93# CONFIG_HW_RANDOM is not set 150CONFIG_SERIAL_8250_RUNTIME_UARTS=4
151CONFIG_SERIAL_CORE=y
152CONFIG_SERIAL_CORE_CONSOLE=y
153CONFIG_DEVPORT=y
94CONFIG_I2C=y 154CONFIG_I2C=y
95# CONFIG_I2C_COMPAT is not set 155CONFIG_I2C_BOARDINFO=y
96CONFIG_I2C_CHARDEV=y 156CONFIG_I2C_CHARDEV=y
97# CONFIG_I2C_HELPER_AUTO is not set
98CONFIG_I2C_AU1550=y 157CONFIG_I2C_AU1550=y
99CONFIG_SPI=y 158CONFIG_SPI=y
159CONFIG_SPI_MASTER=y
100CONFIG_SPI_AU1550=y 160CONFIG_SPI_AU1550=y
101# CONFIG_HWMON is not set 161CONFIG_SPI_BITBANG=y
102# CONFIG_VGA_ARB is not set 162CONFIG_HWMON=y
103# CONFIG_VGA_CONSOLE is not set 163CONFIG_SENSORS_ADM1025=y
164CONFIG_SENSORS_LM70=y
165CONFIG_DUMMY_CONSOLE=y
104CONFIG_SOUND=y 166CONFIG_SOUND=y
105CONFIG_SND=y 167CONFIG_SND=y
106CONFIG_SND_HRTIMER=y 168CONFIG_SND_TIMER=y
107CONFIG_SND_DYNAMIC_MINORS=y 169CONFIG_SND_PCM=y
108# CONFIG_SND_SUPPORT_OLD_API is not set 170CONFIG_SND_JACK=y
109# CONFIG_SND_VERBOSE_PROCFS is not set 171CONFIG_SND_VMASTER=y
110# CONFIG_SND_DRIVERS is not set 172CONFIG_SND_AC97_CODEC=y
111# CONFIG_SND_PCI is not set
112# CONFIG_SND_SPI is not set
113# CONFIG_SND_MIPS is not set
114# CONFIG_SND_PCMCIA is not set
115CONFIG_SND_SOC=y 173CONFIG_SND_SOC=y
174CONFIG_SND_SOC_AC97_BUS=y
116CONFIG_SND_SOC_AU1XPSC=y 175CONFIG_SND_SOC_AU1XPSC=y
117# CONFIG_HID_SUPPORT is not set 176CONFIG_SND_SOC_AU1XPSC_I2S=y
177CONFIG_SND_SOC_AU1XPSC_AC97=y
178CONFIG_SND_SOC_DB1200=y
179CONFIG_SND_SOC_I2C_AND_SPI=y
180CONFIG_SND_SOC_AC97_CODEC=y
181CONFIG_SND_SOC_WM8731=y
182CONFIG_SND_SOC_WM9712=y
183CONFIG_AC97_BUS=y
118CONFIG_USB=y 184CONFIG_USB=y
119# CONFIG_USB_DEVICE_CLASS is not set
120CONFIG_USB_DYNAMIC_MINORS=y 185CONFIG_USB_DYNAMIC_MINORS=y
121CONFIG_USB_SUSPEND=y
122CONFIG_USB_EHCI_HCD=y 186CONFIG_USB_EHCI_HCD=y
123CONFIG_USB_EHCI_ROOT_HUB_TT=y 187CONFIG_USB_EHCI_ROOT_HUB_TT=y
188CONFIG_USB_EHCI_TT_NEWSCHED=y
124CONFIG_USB_OHCI_HCD=y 189CONFIG_USB_OHCI_HCD=y
190CONFIG_USB_OHCI_LITTLE_ENDIAN=y
191CONFIG_USB_UHCI_HCD=y
192CONFIG_USB_STORAGE=y
193CONFIG_RTC_LIB=y
125CONFIG_RTC_CLASS=y 194CONFIG_RTC_CLASS=y
195CONFIG_RTC_HCTOSYS=y
196CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
197CONFIG_RTC_INTF_SYSFS=y
198CONFIG_RTC_INTF_PROC=y
199CONFIG_RTC_INTF_DEV=y
126CONFIG_RTC_DRV_AU1XXX=y 200CONFIG_RTC_DRV_AU1XXX=y
127CONFIG_EXT2_FS=y 201CONFIG_EXT4_FS=y
128# CONFIG_PROC_PAGE_MONITOR is not set 202CONFIG_EXT4_USE_FOR_EXT23=y
203CONFIG_EXT4_FS_XATTR=y
204CONFIG_EXT4_FS_POSIX_ACL=y
205CONFIG_EXT4_FS_SECURITY=y
206CONFIG_JBD2=y
207CONFIG_FS_MBCACHE=y
208CONFIG_FS_POSIX_ACL=y
209CONFIG_EXPORTFS=y
210CONFIG_FILE_LOCKING=y
211CONFIG_FSNOTIFY=y
212CONFIG_DNOTIFY=y
213CONFIG_INOTIFY_USER=y
214CONFIG_PROC_FS=y
215CONFIG_PROC_SYSCTL=y
216CONFIG_SYSFS=y
129CONFIG_TMPFS=y 217CONFIG_TMPFS=y
130CONFIG_CONFIGFS_FS=y 218CONFIG_CONFIGFS_FS=y
219CONFIG_MISC_FILESYSTEMS=y
131CONFIG_JFFS2_FS=y 220CONFIG_JFFS2_FS=y
221CONFIG_JFFS2_FS_DEBUG=0
222CONFIG_JFFS2_FS_WRITEBUFFER=y
132CONFIG_JFFS2_SUMMARY=y 223CONFIG_JFFS2_SUMMARY=y
133CONFIG_JFFS2_FS_XATTR=y 224CONFIG_JFFS2_FS_XATTR=y
134# CONFIG_JFFS2_FS_POSIX_ACL is not set
135# CONFIG_JFFS2_FS_SECURITY is not set
136CONFIG_JFFS2_COMPRESSION_OPTIONS=y 225CONFIG_JFFS2_COMPRESSION_OPTIONS=y
226CONFIG_JFFS2_ZLIB=y
137CONFIG_JFFS2_LZO=y 227CONFIG_JFFS2_LZO=y
228CONFIG_JFFS2_RTIME=y
138CONFIG_JFFS2_RUBIN=y 229CONFIG_JFFS2_RUBIN=y
230CONFIG_JFFS2_CMODE_PRIORITY=y
139CONFIG_SQUASHFS=y 231CONFIG_SQUASHFS=y
232CONFIG_SQUASHFS_ZLIB=y
233CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
234CONFIG_NETWORK_FILESYSTEMS=y
140CONFIG_NFS_FS=y 235CONFIG_NFS_FS=y
141CONFIG_NFS_V3=y 236CONFIG_NFS_V3=y
237CONFIG_NFS_V3_ACL=y
238CONFIG_NFS_V4=y
239CONFIG_NFS_V4_1=y
240CONFIG_PNFS_FILE_LAYOUT=y
241CONFIG_PNFS_BLOCK=y
142CONFIG_ROOT_NFS=y 242CONFIG_ROOT_NFS=y
243CONFIG_NFS_USE_KERNEL_DNS=y
244CONFIG_NFS_USE_NEW_IDMAPPER=y
245CONFIG_NFSD=y
246CONFIG_NFSD_V2_ACL=y
247CONFIG_NFSD_V3=y
248CONFIG_NFSD_V3_ACL=y
249CONFIG_NFSD_V4=y
250CONFIG_LOCKD=y
251CONFIG_LOCKD_V4=y
252CONFIG_NFS_ACL_SUPPORT=y
253CONFIG_NFS_COMMON=y
254CONFIG_SUNRPC=y
255CONFIG_SUNRPC_GSS=y
256CONFIG_SUNRPC_BACKCHANNEL=y
257CONFIG_MSDOS_PARTITION=y
258CONFIG_NLS=y
259CONFIG_NLS_DEFAULT="iso8859-1"
143CONFIG_NLS_CODEPAGE_437=y 260CONFIG_NLS_CODEPAGE_437=y
144CONFIG_NLS_CODEPAGE_850=y 261CONFIG_NLS_CODEPAGE_850=y
145CONFIG_NLS_CODEPAGE_852=y 262CONFIG_NLS_CODEPAGE_852=y
@@ -148,10 +265,21 @@ CONFIG_NLS_ASCII=y
148CONFIG_NLS_ISO8859_1=y 265CONFIG_NLS_ISO8859_1=y
149CONFIG_NLS_ISO8859_15=y 266CONFIG_NLS_ISO8859_15=y
150CONFIG_NLS_UTF8=y 267CONFIG_NLS_UTF8=y
151CONFIG_DEBUG_KERNEL=y 268CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
152# CONFIG_SCHED_DEBUG is not set 269CONFIG_FRAME_WARN=1024
153# CONFIG_FTRACE is not set 270CONFIG_CMDLINE_BOOL=y
154CONFIG_DEBUG_ZBOOT=y 271CONFIG_CMDLINE="noirqdebug console=ttyS0,115200 root=/dev/sda1 rootfstype=ext4"
155CONFIG_KEYS=y 272CONFIG_KEYS=y
156CONFIG_KEYS_DEBUG_PROC_KEYS=y
157CONFIG_SECURITYFS=y 273CONFIG_SECURITYFS=y
274CONFIG_DEFAULT_SECURITY_DAC=y
275CONFIG_BITREVERSE=y
276CONFIG_CRC16=y
277CONFIG_CRC_ITU_T=y
278CONFIG_CRC32=y
279CONFIG_AUDIT_GENERIC=y
280CONFIG_ZLIB_INFLATE=y
281CONFIG_ZLIB_DEFLATE=y
282CONFIG_LZO_COMPRESS=y
283CONFIG_LZO_DECOMPRESS=y
284CONFIG_BCH=y
285CONFIG_NLATTR=y
diff --git a/arch/mips/configs/pb1200_defconfig b/arch/mips/configs/pb1200_defconfig
deleted file mode 100644
index dcbe2704e5ed..000000000000
--- a/arch/mips/configs/pb1200_defconfig
+++ /dev/null
@@ -1,170 +0,0 @@
1CONFIG_MIPS_ALCHEMY=y
2CONFIG_MIPS_PB1200=y
3CONFIG_KSM=y
4CONFIG_NO_HZ=y
5CONFIG_HIGH_RES_TIMERS=y
6CONFIG_HZ_100=y
7# CONFIG_SECCOMP is not set
8CONFIG_EXPERIMENTAL=y
9CONFIG_LOCALVERSION="-pb1200"
10CONFIG_KERNEL_LZMA=y
11CONFIG_SYSVIPC=y
12CONFIG_POSIX_MQUEUE=y
13CONFIG_TINY_RCU=y
14CONFIG_LOG_BUF_SHIFT=14
15CONFIG_EXPERT=y
16# CONFIG_SYSCTL_SYSCALL is not set
17# CONFIG_KALLSYMS is not set
18# CONFIG_PCSPKR_PLATFORM is not set
19# CONFIG_VM_EVENT_COUNTERS is not set
20# CONFIG_COMPAT_BRK is not set
21CONFIG_SLAB=y
22CONFIG_MODULES=y
23CONFIG_MODULE_UNLOAD=y
24# CONFIG_LBDAF is not set
25# CONFIG_BLK_DEV_BSG is not set
26# CONFIG_IOSCHED_DEADLINE is not set
27# CONFIG_IOSCHED_CFQ is not set
28CONFIG_PCCARD=y
29CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
30CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
31CONFIG_BINFMT_MISC=y
32CONFIG_NET=y
33CONFIG_PACKET=y
34CONFIG_UNIX=y
35CONFIG_INET=y
36CONFIG_IP_MULTICAST=y
37CONFIG_IP_PNP=y
38# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
39# CONFIG_INET_XFRM_MODE_TUNNEL is not set
40# CONFIG_INET_XFRM_MODE_BEET is not set
41# CONFIG_INET_DIAG is not set
42# CONFIG_IPV6 is not set
43# CONFIG_WIRELESS is not set
44CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
45CONFIG_MTD=y
46CONFIG_MTD_PARTITIONS=y
47CONFIG_MTD_CMDLINE_PARTS=y
48CONFIG_MTD_CHAR=y
49CONFIG_MTD_BLOCK=y
50CONFIG_MTD_CFI=y
51CONFIG_MTD_CFI_AMDSTD=y
52CONFIG_MTD_PHYSMAP=y
53CONFIG_MTD_NAND=y
54CONFIG_MTD_NAND_PLATFORM=y
55CONFIG_BLK_DEV_LOOP=y
56CONFIG_BLK_DEV_UB=y
57# CONFIG_MISC_DEVICES is not set
58CONFIG_IDE=y
59CONFIG_BLK_DEV_IDECS=y
60CONFIG_BLK_DEV_IDECD=y
61CONFIG_IDE_TASK_IOCTL=y
62# CONFIG_IDE_PROC_FS is not set
63CONFIG_BLK_DEV_IDE_AU1XXX=y
64CONFIG_NETDEVICES=y
65CONFIG_NET_ETHERNET=y
66CONFIG_SMC91X=y
67# CONFIG_NETDEV_1000 is not set
68# CONFIG_NETDEV_10000 is not set
69# CONFIG_WLAN is not set
70# CONFIG_INPUT_MOUSEDEV is not set
71CONFIG_INPUT_EVDEV=y
72# CONFIG_INPUT_KEYBOARD is not set
73# CONFIG_INPUT_MOUSE is not set
74# CONFIG_SERIO is not set
75CONFIG_VT_HW_CONSOLE_BINDING=y
76CONFIG_SERIAL_8250=y
77CONFIG_SERIAL_8250_CONSOLE=y
78CONFIG_SERIAL_8250_NR_UARTS=2
79CONFIG_SERIAL_8250_RUNTIME_UARTS=2
80# CONFIG_LEGACY_PTYS is not set
81# CONFIG_HW_RANDOM is not set
82CONFIG_I2C=y
83# CONFIG_I2C_COMPAT is not set
84CONFIG_I2C_CHARDEV=y
85# CONFIG_I2C_HELPER_AUTO is not set
86CONFIG_I2C_AU1550=y
87CONFIG_SPI=y
88CONFIG_SPI_AU1550=y
89CONFIG_GPIOLIB=y
90CONFIG_GPIO_SYSFS=y
91CONFIG_SENSORS_ADM1025=y
92CONFIG_SENSORS_LM70=y
93CONFIG_FB=y
94CONFIG_FB_AU1200=y
95# CONFIG_VGA_CONSOLE is not set
96CONFIG_FRAMEBUFFER_CONSOLE=y
97CONFIG_FONTS=y
98CONFIG_FONT_8x16=y
99CONFIG_SOUND=y
100CONFIG_SND=y
101CONFIG_SND_DYNAMIC_MINORS=y
102# CONFIG_SND_SUPPORT_OLD_API is not set
103# CONFIG_SND_VERBOSE_PROCFS is not set
104# CONFIG_SND_DRIVERS is not set
105# CONFIG_SND_SPI is not set
106# CONFIG_SND_MIPS is not set
107# CONFIG_SND_USB is not set
108# CONFIG_SND_PCMCIA is not set
109CONFIG_SND_SOC=y
110CONFIG_SND_SOC_AU1XPSC=y
111CONFIG_SND_SOC_DB1200=y
112CONFIG_HIDRAW=y
113CONFIG_USB_HIDDEV=y
114CONFIG_USB=y
115CONFIG_USB_DEBUG=y
116CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
117# CONFIG_USB_DEVICE_CLASS is not set
118CONFIG_USB_DYNAMIC_MINORS=y
119CONFIG_USB_EHCI_HCD=y
120CONFIG_USB_EHCI_ROOT_HUB_TT=y
121CONFIG_USB_OHCI_HCD=y
122CONFIG_MMC=y
123# CONFIG_MMC_BLOCK_BOUNCE is not set
124CONFIG_MMC_AU1X=y
125CONFIG_NEW_LEDS=y
126CONFIG_LEDS_CLASS=y
127CONFIG_LEDS_TRIGGERS=y
128CONFIG_RTC_CLASS=y
129CONFIG_RTC_DRV_AU1XXX=y
130CONFIG_EXT2_FS=y
131CONFIG_ISO9660_FS=y
132CONFIG_JOLIET=y
133CONFIG_ZISOFS=y
134CONFIG_UDF_FS=y
135CONFIG_VFAT_FS=y
136# CONFIG_PROC_PAGE_MONITOR is not set
137CONFIG_TMPFS=y
138CONFIG_JFFS2_FS=y
139CONFIG_JFFS2_SUMMARY=y
140CONFIG_JFFS2_COMPRESSION_OPTIONS=y
141CONFIG_JFFS2_LZO=y
142CONFIG_JFFS2_RUBIN=y
143CONFIG_SQUASHFS=y
144CONFIG_NFS_FS=y
145CONFIG_NFS_V3=y
146CONFIG_ROOT_NFS=y
147CONFIG_PARTITION_ADVANCED=y
148CONFIG_EFI_PARTITION=y
149CONFIG_NLS_CODEPAGE_437=y
150CONFIG_NLS_CODEPAGE_850=y
151CONFIG_NLS_CODEPAGE_852=y
152CONFIG_NLS_CODEPAGE_1250=y
153CONFIG_NLS_ASCII=y
154CONFIG_NLS_ISO8859_1=y
155CONFIG_NLS_ISO8859_2=y
156CONFIG_NLS_ISO8859_15=y
157CONFIG_NLS_UTF8=y
158# CONFIG_ENABLE_WARN_DEPRECATED is not set
159# CONFIG_ENABLE_MUST_CHECK is not set
160CONFIG_MAGIC_SYSRQ=y
161CONFIG_STRIP_ASM_SYMS=y
162CONFIG_DEBUG_KERNEL=y
163# CONFIG_SCHED_DEBUG is not set
164# CONFIG_FTRACE is not set
165CONFIG_CMDLINE_BOOL=y
166CONFIG_CMDLINE="console=ttyS0,115200"
167CONFIG_DEBUG_ZBOOT=y
168CONFIG_KEYS=y
169CONFIG_KEYS_DEBUG_PROC_KEYS=y
170CONFIG_SECURITYFS=y
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 2f7f41873f24..79e4a0dad0d9 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -169,6 +169,7 @@
169#define PRID_IMP_NETLOGIC_XLS412B 0x4c00 169#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
170#define PRID_IMP_NETLOGIC_XLS408B 0x4e00 170#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
171#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 171#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
172#define PRID_IMP_NETLOGIC_AU13XX 0x8000
172 173
173/* 174/*
174 * Definitions for 7:0 on legacy processors 175 * Definitions for 7:0 on legacy processors
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index de24ec57dd2f..569828d3ccab 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void)
136#define ALCHEMY_CPU_AU1100 2 136#define ALCHEMY_CPU_AU1100 2
137#define ALCHEMY_CPU_AU1550 3 137#define ALCHEMY_CPU_AU1550 3
138#define ALCHEMY_CPU_AU1200 4 138#define ALCHEMY_CPU_AU1200 4
139#define ALCHEMY_CPU_AU1300 5
139 140
140static inline int alchemy_get_cputype(void) 141static inline int alchemy_get_cputype(void)
141{ 142{
@@ -156,6 +157,9 @@ static inline int alchemy_get_cputype(void)
156 case 0x05030000: 157 case 0x05030000:
157 return ALCHEMY_CPU_AU1200; 158 return ALCHEMY_CPU_AU1200;
158 break; 159 break;
160 case 0x800c0000:
161 return ALCHEMY_CPU_AU1300;
162 break;
159 } 163 }
160 164
161 return ALCHEMY_CPU_UNKNOWN; 165 return ALCHEMY_CPU_UNKNOWN;
@@ -166,6 +170,7 @@ static inline int alchemy_get_uarts(int type)
166{ 170{
167 switch (type) { 171 switch (type) {
168 case ALCHEMY_CPU_AU1000: 172 case ALCHEMY_CPU_AU1000:
173 case ALCHEMY_CPU_AU1300:
169 return 4; 174 return 4;
170 case ALCHEMY_CPU_AU1500: 175 case ALCHEMY_CPU_AU1500:
171 case ALCHEMY_CPU_AU1200: 176 case ALCHEMY_CPU_AU1200:
@@ -243,6 +248,7 @@ extern unsigned long au1xxx_calc_clock(void);
243/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ 248/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
244void alchemy_sleep_au1000(void); 249void alchemy_sleep_au1000(void);
245void alchemy_sleep_au1550(void); 250void alchemy_sleep_au1550(void);
251void alchemy_sleep_au1300(void);
246void au_sleep(void); 252void au_sleep(void);
247 253
248/* USB: drivers/usb/host/alchemy-common.c */ 254/* USB: drivers/usb/host/alchemy-common.c */
@@ -251,6 +257,7 @@ enum alchemy_usb_block {
251 ALCHEMY_USB_UDC0, 257 ALCHEMY_USB_UDC0,
252 ALCHEMY_USB_EHCI0, 258 ALCHEMY_USB_EHCI0,
253 ALCHEMY_USB_OTG0, 259 ALCHEMY_USB_OTG0,
260 ALCHEMY_USB_OHCI1,
254}; 261};
255int alchemy_usb_control(int block, int enable); 262int alchemy_usb_control(int block, int enable);
256 263
@@ -263,14 +270,92 @@ struct alchemy_pci_platdata {
263 unsigned long pci_cfg_clr; 270 unsigned long pci_cfg_clr;
264}; 271};
265 272
266/* SOC Interrupt numbers */ 273/* Multifunction pins: Each of these pins can either be assigned to the
274 * GPIO controller or a on-chip peripheral.
275 * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
276 * assign one of these to either the GPIO controller or the device.
277 */
278enum au1300_multifunc_pins {
279 /* wake-from-str pins 0-3 */
280 AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
281 AU1300_PIN_WAKE3,
282 /* external clock sources for PSCs: 4-5 */
283 AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
284 /* 8bit MMC interface on SD0: 6-9 */
285 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
286 AU1300_PIN_SD0DAT7,
287 /* aux clk input for freqgen 3: 10 */
288 AU1300_PIN_FG3AUX,
289 /* UART1 pins: 11-18 */
290 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
291 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
292 AU1300_PIN_U1RX, AU1300_PIN_U1TX,
293 /* UART0 pins: 19-24 */
294 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
295 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
296 /* UART2: 25-26 */
297 AU1300_PIN_U2RX, AU1300_PIN_U2TX,
298 /* UART3: 27-28 */
299 AU1300_PIN_U3RX, AU1300_PIN_U3TX,
300 /* LCD controller PWMs, ext pixclock: 29-31 */
301 AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
302 /* SD1 interface: 32-37 */
303 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
304 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
305 /* SD2 interface: 38-43 */
306 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
307 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
308 /* PSC0/1 clocks: 44-45 */
309 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
310 /* PSCs: 46-49/50-53/54-57/58-61 */
311 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
312 AU1300_PIN_PSC0D1,
313 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
314 AU1300_PIN_PSC1D1,
315 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
316 AU1300_PIN_PSC2D1,
317 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
318 AU1300_PIN_PSC3D1,
319 /* PCMCIA interface: 62-70 */
320 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
321 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
322 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
323 /* camera interface H/V sync inputs: 71-72 */
324 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
325 /* PSC2/3 clocks: 73-74 */
326 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
327};
328
329/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
330extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
331extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
332extern void au1300_set_irq_priority(unsigned int irq, int p);
333extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
334
335/* Au1300 allows to disconnect certain blocks from internal power supply */
336enum au1300_vss_block {
337 AU1300_VSS_MPE = 0,
338 AU1300_VSS_BSA,
339 AU1300_VSS_GPE,
340 AU1300_VSS_MGP,
341};
267 342
343extern void au1300_vss_block_control(int block, int enable);
344
345
346/* SOC Interrupt numbers */
347/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
268#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) 348#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
269#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) 349#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
270#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) 350#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
271#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) 351#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
272#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST 352#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
273 353
354/* Au1300-style (GPIC): 1 controller with up to 128 sources */
355#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
356#define ALCHEMY_GPIC_INT_NUM 128
357#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
358
274enum soc_au1000_ints { 359enum soc_au1000_ints {
275 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, 360 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
276 AU1000_UART0_INT = AU1000_FIRST_INT, 361 AU1000_UART0_INT = AU1000_FIRST_INT,
@@ -591,24 +676,77 @@ enum soc_au1200_ints {
591 676
592#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 677#endif /* !defined (_LANGUAGE_ASSEMBLY) */
593 678
679/* Au1300 peripheral interrupt numbers */
680#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
681#define AU1300_UART1_INT (AU1300_FIRST_INT + 17)
682#define AU1300_UART2_INT (AU1300_FIRST_INT + 25)
683#define AU1300_UART3_INT (AU1300_FIRST_INT + 27)
684#define AU1300_SD1_INT (AU1300_FIRST_INT + 32)
685#define AU1300_SD2_INT (AU1300_FIRST_INT + 38)
686#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48)
687#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52)
688#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56)
689#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60)
690#define AU1300_NAND_INT (AU1300_FIRST_INT + 62)
691#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75)
692#define AU1300_MMU_INT (AU1300_FIRST_INT + 76)
693#define AU1300_MPU_INT (AU1300_FIRST_INT + 77)
694#define AU1300_GPU_INT (AU1300_FIRST_INT + 78)
695#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79)
696#define AU1300_TOY_INT (AU1300_FIRST_INT + 80)
697#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81)
698#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82)
699#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83)
700#define AU1300_RTC_INT (AU1300_FIRST_INT + 84)
701#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85)
702#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86)
703#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87)
704#define AU1300_UART0_INT (AU1300_FIRST_INT + 88)
705#define AU1300_SD0_INT (AU1300_FIRST_INT + 89)
706#define AU1300_USB_INT (AU1300_FIRST_INT + 90)
707#define AU1300_LCD_INT (AU1300_FIRST_INT + 91)
708#define AU1300_BSA_INT (AU1300_FIRST_INT + 92)
709#define AU1300_MPE_INT (AU1300_FIRST_INT + 93)
710#define AU1300_ITE_INT (AU1300_FIRST_INT + 94)
711#define AU1300_AES_INT (AU1300_FIRST_INT + 95)
712#define AU1300_CIM_INT (AU1300_FIRST_INT + 96)
713
714/**********************************************************************/
715
594/* 716/*
595 * Physical base addresses for integrated peripherals 717 * Physical base addresses for integrated peripherals
596 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 718 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
597 */ 719 */
598 720
599#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ 721#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
722#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
723#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
724#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
725#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
726#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
727#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
728#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
600#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ 729#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
601#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ 730#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
731#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
602#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ 732#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
603#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */ 733#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */
604#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ 734#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
735#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
605#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ 736#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
606#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ 737#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
607#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ 738#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
608#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ 739#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */
740#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
741#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
609#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ 742#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
743#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
610#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ 744#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
611#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ 745#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
746#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
747#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
748#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
749#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
612#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ 750#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
613#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ 751#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
614#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ 752#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
@@ -622,37 +760,96 @@ enum soc_au1200_ints {
622#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ 760#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
623#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ 761#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
624#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ 762#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
625#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ 763#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */
626#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ 764#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
627#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ 765#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
628#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ 766#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
629#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ 767#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
768#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
630#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ 769#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
631#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ 770#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */
632#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ 771#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */
633#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ 772#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
634#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ 773#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
635#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */ 774#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */
636#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ 775#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
637#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ 776#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
638#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ 777#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
639#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ 778#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
779#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
780#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
640#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ 781#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
641#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ 782#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
642#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ 783#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
643#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ 784#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
644#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ 785#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
645#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ 786#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
787#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
788#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
789#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
790#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
791#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
792#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
646#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ 793#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
647#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */ 794#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */
648#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ 795#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
649#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ 796#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
650#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ 797#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
651#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ 798#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
652#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */ 799#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */
653#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */ 800#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */
654#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ 801#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */
655 802
803/**********************************************************************/
804
805
806/*
807 * Au1300 GPIO+INT controller (GPIC) register offsets and bits
808 * Registers are 128bits (0x10 bytes), divided into 4 "banks".
809 */
810#define AU1300_GPIC_PINVAL 0x0000
811#define AU1300_GPIC_PINVALCLR 0x0010
812#define AU1300_GPIC_IPEND 0x0020
813#define AU1300_GPIC_PRIENC 0x0030
814#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */
815#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */
816#define AU1300_GPIC_DMASEL 0x0060
817#define AU1300_GPIC_DEVSEL 0x0080
818#define AU1300_GPIC_DEVCLR 0x0090
819#define AU1300_GPIC_RSTVAL 0x00a0
820/* pin configuration space. one 32bit register for up to 128 IRQs */
821#define AU1300_GPIC_PINCFG 0x1000
822
823#define GPIC_GPIO_TO_BIT(gpio) \
824 (1 << ((gpio) & 0x1f))
825
826#define GPIC_GPIO_BANKOFF(gpio) \
827 (((gpio) >> 5) * 4)
828
829/* Pin Control bits: who owns the pin, what does it do */
830#define GPIC_CFG_PC_GPIN 0
831#define GPIC_CFG_PC_DEV 1
832#define GPIC_CFG_PC_GPOLOW 2
833#define GPIC_CFG_PC_GPOHIGH 3
834#define GPIC_CFG_PC_MASK 3
835
836/* assign pin to MIPS IRQ line */
837#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2)
838#define GPIC_CFG_IL_MASK (3 << 2)
839
840/* pin interrupt type setup */
841#define GPIC_CFG_IC_OFF (0 << 4)
842#define GPIC_CFG_IC_LEVEL_LOW (1 << 4)
843#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4)
844#define GPIC_CFG_IC_EDGE_FALL (5 << 4)
845#define GPIC_CFG_IC_EDGE_RISE (6 << 4)
846#define GPIC_CFG_IC_EDGE_BOTH (7 << 4)
847#define GPIC_CFG_IC_MASK (7 << 4)
848
849/* allow interrupt to wake cpu from 'wait' */
850#define GPIC_CFG_IDLEWAKE (1 << 7)
851
852/***********************************************************************/
656 853
657/* Au1000 SDRAM memory controller register offsets */ 854/* Au1000 SDRAM memory controller register offsets */
658#define AU1000_MEM_SDMODE0 0x0000 855#define AU1000_MEM_SDMODE0 0x0000
@@ -1068,44 +1265,20 @@ enum soc_au1200_ints {
1068#define SSI_ENABLE_CD (1 << 1) 1265#define SSI_ENABLE_CD (1 << 1)
1069#define SSI_ENABLE_E (1 << 0) 1266#define SSI_ENABLE_E (1 << 0)
1070 1267
1071/* IrDA Controller */ 1268
1072#define IRDA_BASE 0xB0300000 1269/*
1073#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) 1270 * The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's not
1074#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) 1271 * used to select FIR/SIR mode on the transceiver but as a GPIO. Instead a
1075#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) 1272 * CPLD has to be told about the mode.
1076#define IR_RING_SIZE (IRDA_BASE + 0x0C) 1273 */
1077#define IR_RING_PROMPT (IRDA_BASE + 0x10) 1274#define AU1000_IRDA_PHY_MODE_OFF 0
1078#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) 1275#define AU1000_IRDA_PHY_MODE_SIR 1
1079#define IR_INT_CLEAR (IRDA_BASE + 0x18) 1276#define AU1000_IRDA_PHY_MODE_FIR 2
1080#define IR_CONFIG_1 (IRDA_BASE + 0x20) 1277
1081# define IR_RX_INVERT_LED (1 << 0) 1278struct au1k_irda_platform_data {
1082# define IR_TX_INVERT_LED (1 << 1) 1279 void(*set_phy_mode)(int mode);
1083# define IR_ST (1 << 2) 1280};
1084# define IR_SF (1 << 3) 1281
1085# define IR_SIR (1 << 4)
1086# define IR_MIR (1 << 5)
1087# define IR_FIR (1 << 6)
1088# define IR_16CRC (1 << 7)
1089# define IR_TD (1 << 8)
1090# define IR_RX_ALL (1 << 9)
1091# define IR_DMA_ENABLE (1 << 10)
1092# define IR_RX_ENABLE (1 << 11)
1093# define IR_TX_ENABLE (1 << 12)
1094# define IR_LOOPBACK (1 << 14)
1095# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1096 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1097#define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1098#define IR_ENABLE (IRDA_BASE + 0x28)
1099# define IR_RX_STATUS (1 << 9)
1100# define IR_TX_STATUS (1 << 10)
1101#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1102#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1103#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1104#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1105#define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1106# define IR_MODE_INV (1 << 0)
1107# define IR_ONE_PIN (1 << 1)
1108#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1109 1282
1110/* GPIO */ 1283/* GPIO */
1111#define SYS_PINFUNC 0xB190002C 1284#define SYS_PINFUNC 0xB190002C
diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
index 94000a3b6f0b..e221659f1bca 100644
--- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -130,8 +130,10 @@ struct au1xmmc_platform_data {
130#define SD_CONFIG2_DF (0x00000008) 130#define SD_CONFIG2_DF (0x00000008)
131#define SD_CONFIG2_DC (0x00000010) 131#define SD_CONFIG2_DC (0x00000010)
132#define SD_CONFIG2_xx2 (0x000000e0) 132#define SD_CONFIG2_xx2 (0x000000e0)
133#define SD_CONFIG2_BB (0x00000080)
133#define SD_CONFIG2_WB (0x00000100) 134#define SD_CONFIG2_WB (0x00000100)
134#define SD_CONFIG2_RW (0x00000200) 135#define SD_CONFIG2_RW (0x00000200)
136#define SD_CONFIG2_DP (0x00000400)
135 137
136 138
137/* 139/*
diff --git a/arch/mips/include/asm/mach-au1x00/au1200fb.h b/arch/mips/include/asm/mach-au1x00/au1200fb.h
new file mode 100644
index 000000000000..b3c87cc64bb9
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1200fb.h
@@ -0,0 +1,14 @@
1/*
2 * platform data for au1200fb driver.
3 */
4
5#ifndef _AU1200FB_PLAT_H_
6#define _AU1200FB_PLAT_H_
7
8struct au1200fb_platdata {
9 int (*panel_index)(void);
10 int (*panel_init)(void);
11 int (*panel_shutdown)(void);
12};
13
14#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1550nd.h b/arch/mips/include/asm/mach-au1x00/au1550nd.h
new file mode 100644
index 000000000000..ad4c0a03afef
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1550nd.h
@@ -0,0 +1,16 @@
1/*
2 * platform data for the Au1550 NAND driver
3 */
4
5#ifndef _AU1550ND_H_
6#define _AU1550ND_H_
7
8#include <linux/mtd/partitions.h>
9
10struct au1550nd_platdata {
11 struct mtd_partition *parts;
12 int num_parts;
13 int devwidth; /* 0 = 8bit device, 1 = 16bit device */
14};
15
16#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 323ce2d145f2..217810e18361 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -183,6 +183,37 @@ typedef volatile struct au1xxx_ddma_desc {
183#define AU1200_DSCR_CMD0_PSC1_SYNC 25 183#define AU1200_DSCR_CMD0_PSC1_SYNC 25
184#define AU1200_DSCR_CMD0_CIM_SYNC 26 184#define AU1200_DSCR_CMD0_CIM_SYNC 26
185 185
186#define AU1300_DSCR_CMD0_UART0_TX 0
187#define AU1300_DSCR_CMD0_UART0_RX 1
188#define AU1300_DSCR_CMD0_UART1_TX 2
189#define AU1300_DSCR_CMD0_UART1_RX 3
190#define AU1300_DSCR_CMD0_UART2_TX 4
191#define AU1300_DSCR_CMD0_UART2_RX 5
192#define AU1300_DSCR_CMD0_UART3_TX 6
193#define AU1300_DSCR_CMD0_UART3_RX 7
194#define AU1300_DSCR_CMD0_SDMS_TX0 8
195#define AU1300_DSCR_CMD0_SDMS_RX0 9
196#define AU1300_DSCR_CMD0_SDMS_TX1 10
197#define AU1300_DSCR_CMD0_SDMS_RX1 11
198#define AU1300_DSCR_CMD0_AES_TX 12
199#define AU1300_DSCR_CMD0_AES_RX 13
200#define AU1300_DSCR_CMD0_PSC0_TX 14
201#define AU1300_DSCR_CMD0_PSC0_RX 15
202#define AU1300_DSCR_CMD0_PSC1_TX 16
203#define AU1300_DSCR_CMD0_PSC1_RX 17
204#define AU1300_DSCR_CMD0_PSC2_TX 18
205#define AU1300_DSCR_CMD0_PSC2_RX 19
206#define AU1300_DSCR_CMD0_PSC3_TX 20
207#define AU1300_DSCR_CMD0_PSC3_RX 21
208#define AU1300_DSCR_CMD0_LCD 22
209#define AU1300_DSCR_CMD0_NAND_FLASH 23
210#define AU1300_DSCR_CMD0_SDMS_TX2 24
211#define AU1300_DSCR_CMD0_SDMS_RX2 25
212#define AU1300_DSCR_CMD0_CIM_SYNC 26
213#define AU1300_DSCR_CMD0_UDMA 27
214#define AU1300_DSCR_CMD0_DMA_REQ0 28
215#define AU1300_DSCR_CMD0_DMA_REQ1 29
216
186#define DSCR_CMD0_THROTTLE 30 217#define DSCR_CMD0_THROTTLE 30
187#define DSCR_CMD0_ALWAYS 31 218#define DSCR_CMD0_ALWAYS 31
188#define DSCR_NDEV_IDS 32 219#define DSCR_NDEV_IDS 32
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
index d5df0cab9b87..3f741af37d47 100644
--- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -13,12 +13,14 @@
13#define cpu_has_4k_cache 1 13#define cpu_has_4k_cache 1
14#define cpu_has_tx39_cache 0 14#define cpu_has_tx39_cache 0
15#define cpu_has_fpu 0 15#define cpu_has_fpu 0
16#define cpu_has_32fpr 0
16#define cpu_has_counter 1 17#define cpu_has_counter 1
17#define cpu_has_watch 1 18#define cpu_has_watch 1
18#define cpu_has_divec 1 19#define cpu_has_divec 1
19#define cpu_has_vce 0 20#define cpu_has_vce 0
20#define cpu_has_cache_cdex_p 0 21#define cpu_has_cache_cdex_p 0
21#define cpu_has_cache_cdex_s 0 22#define cpu_has_cache_cdex_s 0
23#define cpu_has_prefetch 1
22#define cpu_has_mcheck 1 24#define cpu_has_mcheck 1
23#define cpu_has_ejtag 1 25#define cpu_has_ejtag 1
24#define cpu_has_llsc 1 26#define cpu_has_llsc 1
@@ -29,6 +31,7 @@
29#define cpu_has_vtag_icache 0 31#define cpu_has_vtag_icache 0
30#define cpu_has_dc_aliases 0 32#define cpu_has_dc_aliases 0
31#define cpu_has_ic_fills_f_dc 1 33#define cpu_has_ic_fills_f_dc 1
34#define cpu_has_pindexed_dcache 0
32#define cpu_has_mips32r1 1 35#define cpu_has_mips32r1 1
33#define cpu_has_mips32r2 0 36#define cpu_has_mips32r2 0
34#define cpu_has_mips64r1 0 37#define cpu_has_mips64r1 0
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
new file mode 100644
index 000000000000..556e1be20bf6
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
@@ -0,0 +1,241 @@
1/*
2 * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles.
3 *
4 * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
5 */
6
7#ifndef _GPIO_AU1300_H_
8#define _GPIO_AU1300_H_
9
10#include <asm/addrspace.h>
11#include <asm/io.h>
12#include <asm/mach-au1x00/au1000.h>
13
14/* with the current GPIC design, up to 128 GPIOs are possible.
15 * The only implementation so far is in the Au1300, which has 75 externally
16 * available GPIOs.
17 */
18#define AU1300_GPIO_BASE 0
19#define AU1300_GPIO_NUM 75
20#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1)
21
22#define AU1300_GPIC_ADDR \
23 (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR)
24
25static inline int au1300_gpio_get_value(unsigned int gpio)
26{
27 void __iomem *roff = AU1300_GPIC_ADDR;
28 int bit;
29
30 gpio -= AU1300_GPIO_BASE;
31 roff += GPIC_GPIO_BANKOFF(gpio);
32 bit = GPIC_GPIO_TO_BIT(gpio);
33 return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
34}
35
36static inline int au1300_gpio_direction_input(unsigned int gpio)
37{
38 void __iomem *roff = AU1300_GPIC_ADDR;
39 unsigned long bit;
40
41 gpio -= AU1300_GPIO_BASE;
42
43 roff += GPIC_GPIO_BANKOFF(gpio);
44 bit = GPIC_GPIO_TO_BIT(gpio);
45 __raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
46 wmb();
47
48 return 0;
49}
50
51static inline int au1300_gpio_set_value(unsigned int gpio, int v)
52{
53 void __iomem *roff = AU1300_GPIC_ADDR;
54 unsigned long bit;
55
56 gpio -= AU1300_GPIO_BASE;
57
58 roff += GPIC_GPIO_BANKOFF(gpio);
59 bit = GPIC_GPIO_TO_BIT(gpio);
60 __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
61 : AU1300_GPIC_PINVALCLR));
62 wmb();
63
64 return 0;
65}
66
67static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
68{
69 /* hw switches to output automatically */
70 return au1300_gpio_set_value(gpio, v);
71}
72
73static inline int au1300_gpio_to_irq(unsigned int gpio)
74{
75 return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE);
76}
77
78static inline int au1300_irq_to_gpio(unsigned int irq)
79{
80 return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE;
81}
82
83static inline int au1300_gpio_is_valid(unsigned int gpio)
84{
85 int ret;
86
87 switch (alchemy_get_cputype()) {
88 case ALCHEMY_CPU_AU1300:
89 ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX));
90 break;
91 default:
92 ret = 0;
93 }
94 return ret;
95}
96
97static inline int au1300_gpio_cansleep(unsigned int gpio)
98{
99 return 0;
100}
101
102/* hardware remembers gpio 0-63 levels on powerup */
103static inline int au1300_gpio_getinitlvl(unsigned int gpio)
104{
105 void __iomem *roff = AU1300_GPIC_ADDR;
106 unsigned long v;
107
108 if (unlikely(gpio > 63))
109 return 0;
110 else if (gpio > 31) {
111 gpio -= 32;
112 roff += 4;
113 }
114
115 v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
116 return (v >> gpio) & 1;
117}
118
119/**********************************************************************/
120
121/* Linux gpio framework integration.
122*
123* 4 use cases of Alchemy GPIOS:
124*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
125* Board must register gpiochips.
126*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
127* A gpiochip for the 75 GPIOs is registered.
128*
129*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
130* the boards' gpio.h must provide the linux gpio wrapper functions,
131*
132*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
133* inlinable gpio functions are provided which enable access to the
134* Au1300 gpios only by using the numbers straight out of the data-
135* sheets.
136
137* Cases 1 and 3 are intended for boards which want to provide their own
138* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
139* which are in part provided by spare Au1300 GPIO pins and in part by
140* an external FPGA but you still want them to be accssible in linux
141* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
142* as required).
143*/
144
145#ifndef CONFIG_GPIOLIB
146
147#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300
148
149#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
150
151static inline int gpio_direction_input(unsigned int gpio)
152{
153 return au1300_gpio_direction_input(gpio);
154}
155
156static inline int gpio_direction_output(unsigned int gpio, int v)
157{
158 return au1300_gpio_direction_output(gpio, v);
159}
160
161static inline int gpio_get_value(unsigned int gpio)
162{
163 return au1300_gpio_get_value(gpio);
164}
165
166static inline void gpio_set_value(unsigned int gpio, int v)
167{
168 au1300_gpio_set_value(gpio, v);
169}
170
171static inline int gpio_get_value_cansleep(unsigned gpio)
172{
173 return gpio_get_value(gpio);
174}
175
176static inline void gpio_set_value_cansleep(unsigned gpio, int value)
177{
178 gpio_set_value(gpio, value);
179}
180
181static inline int gpio_is_valid(unsigned int gpio)
182{
183 return au1300_gpio_is_valid(gpio);
184}
185
186static inline int gpio_cansleep(unsigned int gpio)
187{
188 return au1300_gpio_cansleep(gpio);
189}
190
191static inline int gpio_to_irq(unsigned int gpio)
192{
193 return au1300_gpio_to_irq(gpio);
194}
195
196static inline int irq_to_gpio(unsigned int irq)
197{
198 return au1300_irq_to_gpio(irq);
199}
200
201static inline int gpio_request(unsigned int gpio, const char *label)
202{
203 return 0;
204}
205
206static inline void gpio_free(unsigned int gpio)
207{
208}
209
210static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
211{
212 return -ENOSYS;
213}
214
215static inline void gpio_unexport(unsigned gpio)
216{
217}
218
219static inline int gpio_export(unsigned gpio, bool direction_may_change)
220{
221 return -ENOSYS;
222}
223
224static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
225{
226 return -ENOSYS;
227}
228
229static inline int gpio_export_link(struct device *dev, const char *name,
230 unsigned gpio)
231{
232 return -ENOSYS;
233}
234
235#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
236
237#endif /* CONFIG_ALCHEMY_GPIOINT_AU1300 */
238
239#endif /* CONFIG GPIOLIB */
240
241#endif /* _GPIO_AU1300_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index fcdc8c4809db..22e7ff17fc48 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -12,6 +12,7 @@
12 12
13#include <asm/mach-au1x00/au1000.h> 13#include <asm/mach-au1x00/au1000.h>
14#include <asm/mach-au1x00/gpio-au1000.h> 14#include <asm/mach-au1x00/gpio-au1000.h>
15#include <asm/mach-au1x00/gpio-au1300.h>
15 16
16/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before 17/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
17 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this 18 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
@@ -58,6 +59,8 @@ static inline int __au_irq_to_gpio(unsigned int irq)
58 switch (alchemy_get_cputype()) { 59 switch (alchemy_get_cputype()) {
59 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200: 60 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
60 return alchemy_irq_to_gpio(irq); 61 return alchemy_irq_to_gpio(irq);
62 case ALCHEMY_CPU_AU1300:
63 return au1300_irq_to_gpio(irq);
61 } 64 }
62 return -EINVAL; 65 return -EINVAL;
63} 66}
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
index 618d2de02ed3..bb9fc23d853a 100644
--- a/arch/mips/include/asm/mach-db1x00/bcsr.h
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -34,6 +34,8 @@
34#define PB1200_BCSR_PHYS_ADDR 0x0D800000 34#define PB1200_BCSR_PHYS_ADDR 0x0D800000
35#define PB1200_BCSR_HEXLED_OFS 0x00400000 35#define PB1200_BCSR_HEXLED_OFS 0x00400000
36 36
37#define DB1300_BCSR_PHYS_ADDR 0x19800000
38#define DB1300_BCSR_HEXLED_OFS 0x00400000
37 39
38enum bcsr_id { 40enum bcsr_id {
39 /* BCSR base 1 */ 41 /* BCSR base 1 */
@@ -105,6 +107,7 @@ enum bcsr_whoami_boards {
105 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, 107 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
106 BCSR_WHOAMI_PB1200_DDR2, 108 BCSR_WHOAMI_PB1200_DDR2,
107 BCSR_WHOAMI_DB1200, 109 BCSR_WHOAMI_DB1200,
110 BCSR_WHOAMI_DB1300,
108}; 111};
109 112
110/* STATUS reg. Unless otherwise noted, they're valid on all boards. 113/* STATUS reg. Unless otherwise noted, they're valid on all boards.
@@ -118,12 +121,12 @@ enum bcsr_whoami_boards {
118#define BCSR_STATUS_SRAMWIDTH 0x0080 121#define BCSR_STATUS_SRAMWIDTH 0x0080
119#define BCSR_STATUS_FLASHBUSY 0x0100 122#define BCSR_STATUS_FLASHBUSY 0x0100
120#define BCSR_STATUS_ROMBUSY 0x0400 123#define BCSR_STATUS_ROMBUSY 0x0400
121#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */ 124#define BCSR_STATUS_SD0WP 0x0400 /* DB1200/DB1300:SD1 */
122#define BCSR_STATUS_SD1WP 0x0800 125#define BCSR_STATUS_SD1WP 0x0800
123#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ 126#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */
124#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 127#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000
125#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */ 128#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200/1300 */
126#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */ 129#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200/1300 */
127#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ 130#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */
128#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ 131#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */
129#define BCSR_STATUS_FLASHDEN 0xC000 132#define BCSR_STATUS_FLASHDEN 0xC000
@@ -133,6 +136,11 @@ enum bcsr_whoami_boards {
133#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ 136#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */
134#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ 137#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */
135 138
139#define BCSR_STATUS_CFWP 0x4000 /* DB1300 */
140#define BCSR_STATUS_USBOCn 0x2000 /* DB1300 */
141#define BCSR_STATUS_OTGOCn 0x1000 /* DB1300 */
142#define BCSR_STATUS_DCDMARQ 0x0010 /* DB1300 */
143#define BCSR_STATUS_IDEDMARQ 0x0020 /* DB1300 */
136 144
137/* DB/PB1000,1100,1500,1550 */ 145/* DB/PB1000,1100,1500,1550 */
138#define BCSR_RESETS_PHY0 0x0001 146#define BCSR_RESETS_PHY0 0x0001
@@ -155,17 +163,17 @@ enum bcsr_whoami_boards {
155#define BCSR_BOARD_GPIO200RST 0x0400 163#define BCSR_BOARD_GPIO200RST 0x0400
156#define BCSR_BOARD_PCICLKOUT 0x0800 164#define BCSR_BOARD_PCICLKOUT 0x0800
157#define BCSR_BOARD_PCICFG 0x1000 165#define BCSR_BOARD_PCICFG 0x1000
158#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */ 166#define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */
159#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ 167#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */
160#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ 168#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */
161 169
162 170
163/* DB/PB1200 */ 171/* DB/PB1200/1300 */
164#define BCSR_RESETS_ETH 0x0001 172#define BCSR_RESETS_ETH 0x0001
165#define BCSR_RESETS_CAMERA 0x0002 173#define BCSR_RESETS_CAMERA 0x0002
166#define BCSR_RESETS_DC 0x0004 174#define BCSR_RESETS_DC 0x0004
167#define BCSR_RESETS_IDE 0x0008 175#define BCSR_RESETS_IDE 0x0008
168#define BCSR_RESETS_TV 0x0010 /* DB1200 */ 176#define BCSR_RESETS_TV 0x0010 /* DB1200/1300 */
169/* Not resets but in the same register */ 177/* Not resets but in the same register */
170#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ 178#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */
171#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ 179#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */
@@ -174,13 +182,22 @@ enum bcsr_whoami_boards {
174#define BCSR_RESETS_SPISEL 0x4000 182#define BCSR_RESETS_SPISEL 0x4000
175#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ 183#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */
176 184
185#define BCSR_RESETS_VDDQSHDN 0x0200 /* DB1300 */
186#define BCSR_RESETS_OTPPGM 0x0400 /* DB1300 */
187#define BCSR_RESETS_OTPSCLK 0x0800 /* DB1300 */
188#define BCSR_RESETS_OTPWRPROT 0x1000 /* DB1300 */
189#define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */
190#define BCSR_RESETS_OTGPWR 0x4000 /* DB1300 */
191#define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */
192
177#define BCSR_BOARD_LCDVEE 0x0001 193#define BCSR_BOARD_LCDVEE 0x0001
178#define BCSR_BOARD_LCDVDD 0x0002 194#define BCSR_BOARD_LCDVDD 0x0002
179#define BCSR_BOARD_LCDBL 0x0004 195#define BCSR_BOARD_LCDBL 0x0004
180#define BCSR_BOARD_CAMSNAP 0x0010 196#define BCSR_BOARD_CAMSNAP 0x0010
181#define BCSR_BOARD_CAMPWR 0x0020 197#define BCSR_BOARD_CAMPWR 0x0020
182#define BCSR_BOARD_SD0PWR 0x0040 198#define BCSR_BOARD_SD0PWR 0x0040
183 199#define BCSR_BOARD_CAMCS 0x0010 /* DB1300 */
200#define BCSR_BOARD_HDMI_DE 0x0040 /* DB1300 */
184 201
185#define BCSR_SWITCHES_DIP 0x00FF 202#define BCSR_SWITCHES_DIP 0x00FF
186#define BCSR_SWITCHES_DIP_1 0x0080 203#define BCSR_SWITCHES_DIP_1 0x0080
@@ -214,7 +231,10 @@ enum bcsr_whoami_boards {
214#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ 231#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */
215#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ 232#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */
216#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ 233#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */
217 234#define BCSR_SYSTEM_DEBUGCSMASK 0x003F /* DB1300 */
235#define BCSR_SYSTEM_UDMAMODE 0x0100 /* DB1300 */
236#define BCSR_SYSTEM_WAKEONIRQ 0x0200 /* DB1300 */
237#define BCSR_SYSTEM_VDDI1300 0x3C00 /* DB1300 */
218 238
219 239
220 240
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 7a39657108c4..b2a8319521e5 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -43,15 +43,20 @@
43#define BCSR_INT_PC1EJECT 0x0800 43#define BCSR_INT_PC1EJECT 0x0800
44#define BCSR_INT_SD0INSERT 0x1000 44#define BCSR_INT_SD0INSERT 0x1000
45#define BCSR_INT_SD0EJECT 0x2000 45#define BCSR_INT_SD0EJECT 0x2000
46#define BCSR_INT_SD1INSERT 0x4000
47#define BCSR_INT_SD1EJECT 0x8000
46 48
47#define IDE_PHYS_ADDR 0x18800000
48#define IDE_REG_SHIFT 5 49#define IDE_REG_SHIFT 5
49 50
50#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR 51#define DB1200_IDE_PHYS_ADDR 0x18800000
51#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) 52#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
52#define DB1200_ETH_PHYS_ADDR 0x19000300 53#define DB1200_ETH_PHYS_ADDR 0x19000300
53#define DB1200_NAND_PHYS_ADDR 0x20000000 54#define DB1200_NAND_PHYS_ADDR 0x20000000
54 55
56#define PB1200_IDE_PHYS_ADDR 0x0C800000
57#define PB1200_ETH_PHYS_ADDR 0x0D000300
58#define PB1200_NAND_PHYS_ADDR 0x1C000000
59
55/* 60/*
56 * External Interrupts for DBAu1200 as of 8/6/2004. 61 * External Interrupts for DBAu1200 as of 8/6/2004.
57 * Bit positions in the CPLD registers can be calculated by taking 62 * Bit positions in the CPLD registers can be calculated by taking
@@ -77,6 +82,8 @@ enum external_db1200_ints {
77 DB1200_PC1_EJECT_INT, 82 DB1200_PC1_EJECT_INT,
78 DB1200_SD0_INSERT_INT, 83 DB1200_SD0_INSERT_INT,
79 DB1200_SD0_EJECT_INT, 84 DB1200_SD0_EJECT_INT,
85 PB1200_SD1_INSERT_INT,
86 PB1200_SD1_EJECT_INT,
80 87
81 DB1200_INT_END = DB1200_INT_BEGIN + 15, 88 DB1200_INT_END = DB1200_INT_BEGIN + 15,
82}; 89};
diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h
new file mode 100644
index 000000000000..7fe5fb3ba877
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/db1300.h
@@ -0,0 +1,40 @@
1/*
2 * NetLogic DB1300 board constants
3 */
4
5#ifndef _DB1300_H_
6#define _DB1300_H_
7
8/* FPGA (external mux) interrupt sources */
9#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1)
10#define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
11#define DB1300_ETH_INT (DB1300_FIRST_INT + 1)
12#define DB1300_CF_INT (DB1300_FIRST_INT + 2)
13#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4)
14#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5)
15#define DB1300_DC_INT (DB1300_FIRST_INT + 6)
16#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7)
17#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8)
18#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9)
19#define DB1300_AC97_INT (DB1300_FIRST_INT + 10)
20#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11)
21#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12)
22#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13)
23#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)
24#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
25#define DB1300_LAST_INT (DB1300_FIRST_INT + 15)
26
27/* SMSC9210 CS */
28#define DB1300_ETH_PHYS_ADDR 0x19000000
29#define DB1300_ETH_PHYS_END 0x197fffff
30
31/* ATA CS */
32#define DB1300_IDE_PHYS_ADDR 0x18800000
33#define DB1300_IDE_REG_SHIFT 5
34#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT)
35
36/* NAND CS */
37#define DB1300_NAND_PHYS_ADDR 0x20000000
38#define DB1300_NAND_PHYS_END 0x20000fff
39
40#endif /* _DB1300_H_ */
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
deleted file mode 100644
index a5affb0568ef..000000000000
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * AMD Alchemy DBAu1x00 Reference Boards
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_DB1X00_H
28#define __ASM_DB1X00_H
29
30#include <asm/mach-au1x00/au1xxx_psc.h>
31
32#ifdef CONFIG_MIPS_DB1550
33
34#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
35#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
36#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
37#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
38
39#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
40#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
41#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
42#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
43
44#define NAND_PHYS_ADDR 0x20000000
45
46#endif
47
48/*
49 * NAND defines
50 *
51 * Timing values as described in databook, * ns value stripped of the
52 * lower 2 bits.
53 * These defines are here rather than an Au1550 generic file because
54 * the parts chosen on another board may be different and may require
55 * different timings.
56 */
57#define NAND_T_H (18 >> 2)
58#define NAND_T_PUL (30 >> 2)
59#define NAND_T_SU (30 >> 2)
60#define NAND_T_WH (30 >> 2)
61
62/* Bitfield shift amounts */
63#define NAND_T_H_SHIFT 0
64#define NAND_T_PUL_SHIFT 4
65#define NAND_T_SU_SHIFT 8
66#define NAND_T_WH_SHIFT 12
67
68#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
69 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
70 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
71 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
72#define NAND_CS 1
73
74/* Should be done by YAMON */
75#define NAND_STCFG 0x00400005 /* 8-bit NAND */
76#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
77#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
78
79#endif /* __ASM_DB1X00_H */
diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h
new file mode 100644
index 000000000000..15b26693238f
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/irq.h
@@ -0,0 +1,23 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_GENERIC_IRQ_H
9#define __ASM_MACH_GENERIC_IRQ_H
10
11
12#ifdef NR_IRQS
13#undef NR_IRQS
14#endif
15
16#ifndef MIPS_CPU_IRQ_BASE
17#define MIPS_CPU_IRQ_BASE 0
18#endif
19
20/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */
21#define NR_IRQS 152
22
23#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
deleted file mode 100644
index 622c58710e5b..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998, 2001, 03 by Ralf Baechle
7 *
8 * RTC routines for PC style attached Dallas chip.
9 */
10#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
11#define __ASM_MACH_AU1XX_MC146818RTC_H
12
13#include <asm/io.h>
14#include <asm/mach-au1x00/au1000.h>
15
16#define RTC_PORT(x) (0x0c000000 + (x))
17#define RTC_IRQ 8
18#define PB1500_RTC_ADDR 0x0c000000
19
20static inline unsigned char CMOS_READ(unsigned long offset)
21{
22 offset <<= 2;
23 return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
24}
25
26static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
27{
28 offset <<= 2;
29 au_writel(data, offset + PB1500_RTC_ADDR);
30}
31
32#define RTC_ALWAYS_BCD 1
33
34#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
deleted file mode 100644
index 65059255dc1e..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1000.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * Alchemy Semi Pb1000 Reference Board
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 *
24 *
25 */
26#ifndef __ASM_PB1000_H
27#define __ASM_PB1000_H
28
29/* PCMCIA PB1000 specific defines */
30#define PCMCIA_MAX_SOCK 1
31#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
32
33#define PB1000_PCR 0xBE000000
34# define PCR_SLOT_0_VPP0 (1 << 0)
35# define PCR_SLOT_0_VPP1 (1 << 1)
36# define PCR_SLOT_0_VCC0 (1 << 2)
37# define PCR_SLOT_0_VCC1 (1 << 3)
38# define PCR_SLOT_0_RST (1 << 4)
39# define PCR_SLOT_1_VPP0 (1 << 8)
40# define PCR_SLOT_1_VPP1 (1 << 9)
41# define PCR_SLOT_1_VCC0 (1 << 10)
42# define PCR_SLOT_1_VCC1 (1 << 11)
43# define PCR_SLOT_1_RST (1 << 12)
44
45#define PB1000_MDR 0xBE000004
46# define MDR_PI (1 << 5) /* PCMCIA int latch */
47# define MDR_EPI (1 << 14) /* enable PCMCIA int */
48# define MDR_CPI (1 << 15) /* clear PCMCIA int */
49
50#define PB1000_ACR1 0xBE000008
51# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
52# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
53# define ACR1_SLOT_0_READY (1 << 2) /* ready */
54# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
55# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
56# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
57# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
58# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
59# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
60# define ACR1_SLOT_1_READY (1 << 10) /* ready */
61# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
62# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
63# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
64# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
65
66#define CPLD_AUX0 0xBE00000C
67#define CPLD_AUX1 0xBE000010
68#define CPLD_AUX2 0xBE000014
69
70/* Voltage levels */
71
72/* VPPEN1 - VPPEN0 */
73#define VPP_GND ((0 << 1) | (0 << 0))
74#define VPP_5V ((1 << 1) | (0 << 0))
75#define VPP_3V ((0 << 1) | (1 << 0))
76#define VPP_12V ((0 << 1) | (1 << 0))
77#define VPP_HIZ ((1 << 1) | (1 << 0))
78
79/* VCCEN1 - VCCEN0 */
80#define VCC_3V ((0 << 1) | (1 << 0))
81#define VCC_5V ((1 << 1) | (0 << 0))
82#define VCC_HIZ ((0 << 1) | (0 << 0))
83
84/* VPP/VCC */
85#define SET_VCC_VPP(VCC, VPP, SLOT) \
86 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
87#endif /* __ASM_PB1000_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
deleted file mode 100644
index 374416adb65b..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ /dev/null
@@ -1,139 +0,0 @@
1/*
2 * AMD Alchemy Pb1200 Reference Board
3 * Board Registers defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_PB1200_H
25#define __ASM_PB1200_H
26
27#include <linux/types.h>
28#include <asm/mach-au1x00/au1000.h>
29#include <asm/mach-au1x00/au1xxx_psc.h>
30
31#define DBDMA_AC97_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
32#define DBDMA_AC97_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
33#define DBDMA_I2S_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
34#define DBDMA_I2S_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
35
36/*
37 * SPI and SMB are muxed on the Pb1200 board.
38 * Refer to board documentation.
39 */
40#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
41#define SMBUS_PSC_BASE AU1550_PSC0_PHYS_ADDR
42/*
43 * AC97 and I2S are muxed on the Pb1200 board.
44 * Refer to board documentation.
45 */
46#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
47#define I2S_PSC_BASE AU1550_PSC1_PHYS_ADDR
48
49
50#define BCSR_SYSTEM_VDDI 0x001F
51#define BCSR_SYSTEM_POWEROFF 0x4000
52#define BCSR_SYSTEM_RESET 0x8000
53
54/* Bit positions for the different interrupt sources */
55#define BCSR_INT_IDE 0x0001
56#define BCSR_INT_ETH 0x0002
57#define BCSR_INT_PC0 0x0004
58#define BCSR_INT_PC0STSCHG 0x0008
59#define BCSR_INT_PC1 0x0010
60#define BCSR_INT_PC1STSCHG 0x0020
61#define BCSR_INT_DC 0x0040
62#define BCSR_INT_FLASHBUSY 0x0080
63#define BCSR_INT_PC0INSERT 0x0100
64#define BCSR_INT_PC0EJECT 0x0200
65#define BCSR_INT_PC1INSERT 0x0400
66#define BCSR_INT_PC1EJECT 0x0800
67#define BCSR_INT_SD0INSERT 0x1000
68#define BCSR_INT_SD0EJECT 0x2000
69#define BCSR_INT_SD1INSERT 0x4000
70#define BCSR_INT_SD1EJECT 0x8000
71
72#define SMC91C111_PHYS_ADDR 0x0D000300
73#define SMC91C111_INT PB1200_ETH_INT
74
75#define IDE_PHYS_ADDR 0x0C800000
76#define IDE_REG_SHIFT 5
77#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
78#define IDE_INT PB1200_IDE_INT
79
80#define NAND_PHYS_ADDR 0x1C000000
81
82/*
83 * Timing values as described in databook, * ns value stripped of
84 * lower 2 bits.
85 * These defines are here rather than an Au1200 generic file because
86 * the parts chosen on another board may be different and may require
87 * different timings.
88 */
89#define NAND_T_H (18 >> 2)
90#define NAND_T_PUL (30 >> 2)
91#define NAND_T_SU (30 >> 2)
92#define NAND_T_WH (30 >> 2)
93
94/* Bitfield shift amounts */
95#define NAND_T_H_SHIFT 0
96#define NAND_T_PUL_SHIFT 4
97#define NAND_T_SU_SHIFT 8
98#define NAND_T_WH_SHIFT 12
99
100#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
101 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
102 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
103 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
104
105/*
106 * External Interrupts for Pb1200 as of 8/6/2004.
107 * Bit positions in the CPLD registers can be calculated by taking
108 * the interrupt define and subtracting the PB1200_INT_BEGIN value.
109 *
110 * Example: IDE bis pos is = 64 - 64
111 * ETH bit pos is = 65 - 64
112 */
113enum external_pb1200_ints {
114 PB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
115
116 PB1200_IDE_INT = PB1200_INT_BEGIN,
117 PB1200_ETH_INT,
118 PB1200_PC0_INT,
119 PB1200_PC0_STSCHG_INT,
120 PB1200_PC1_INT,
121 PB1200_PC1_STSCHG_INT,
122 PB1200_DC_INT,
123 PB1200_FLASHBUSY_INT,
124 PB1200_PC0_INSERT_INT,
125 PB1200_PC0_EJECT_INT,
126 PB1200_PC1_INSERT_INT,
127 PB1200_PC1_EJECT_INT,
128 PB1200_SD0_INSERT_INT,
129 PB1200_SD0_EJECT_INT,
130 PB1200_SD1_INSERT_INT,
131 PB1200_SD1_EJECT_INT,
132
133 PB1200_INT_END = PB1200_INT_BEGIN + 15
134};
135
136/* NAND chip select */
137#define NAND_CS 1
138
139#endif /* __ASM_PB1200_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
deleted file mode 100644
index 443b88adebf1..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * AMD Alchemy Semi PB1550 Reference Board
3 * Board Registers defines.
4 *
5 * Copyright 2004 Embedded Edge LLC.
6 * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_PB1550_H
28#define __ASM_PB1550_H
29
30#include <linux/types.h>
31#include <asm/mach-au1x00/au1xxx_psc.h>
32
33#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
34#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
35#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
36#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
37
38#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
39#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
40#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
41#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
42
43/*
44 * Timing values as described in databook, * ns value stripped of
45 * lower 2 bits.
46 * These defines are here rather than an SOC1550 generic file because
47 * the parts chosen on another board may be different and may require
48 * different timings.
49 */
50#define NAND_T_H (18 >> 2)
51#define NAND_T_PUL (30 >> 2)
52#define NAND_T_SU (30 >> 2)
53#define NAND_T_WH (30 >> 2)
54
55/* Bitfield shift amounts */
56#define NAND_T_H_SHIFT 0
57#define NAND_T_PUL_SHIFT 4
58#define NAND_T_SU_SHIFT 8
59#define NAND_T_WH_SHIFT 12
60
61#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
62 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
63 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
64 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
65
66#define NAND_CS 1
67
68/* Should be done by YAMON */
69#define NAND_STCFG 0x00400005 /* 8-bit NAND */
70#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
71#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
72
73#endif /* __ASM_PB1550_H */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c7d3cf1ce46e..98383995e6ac 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1014,6 +1014,13 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1014{ 1014{
1015 decode_configs(c); 1015 decode_configs(c);
1016 1016
1017 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1018 c->cputype = CPU_ALCHEMY;
1019 __cpu_name[cpu] = "Au1300";
1020 /* following stuff is not for Alchemy */
1021 return;
1022 }
1023
1017 c->options = (MIPS_CPU_TLB | 1024 c->options = (MIPS_CPU_TLB |
1018 MIPS_CPU_4KEX | 1025 MIPS_CPU_4KEX |
1019 MIPS_CPU_COUNTER | 1026 MIPS_CPU_COUNTER |
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-06 20:28:54 -0400