diff options
author | Loc Ho <lho@apm.com> | 2014-03-14 19:53:18 -0400 |
---|---|---|
committer | Tejun Heo <tj@kernel.org> | 2014-03-17 15:54:40 -0400 |
commit | 71b70ee9350f239ea021bbb737771ebd5d02c020 (patch) | |
tree | 9e4e70e1e2051f0b5b9e0901622982e553164928 /arch | |
parent | cdf457a4fe30980f7c15a894af2f954f85cd71d2 (diff) |
arm64: Add APM X-Gene SoC 15Gbps Multi-purpose PHY DTS entries
This patch adds the DTS entries for the APM X-Gene SoC 15Gbps Multi-purpose
PHY driver. The PHY for SATA controller 2 and 3 are enabled by default.
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm64/boot/dts/apm-storm.dtsi | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi index d37d7369e260..6d4f493aac9a 100644 --- a/arch/arm64/boot/dts/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm-storm.dtsi | |||
@@ -176,6 +176,48 @@ | |||
176 | reg-names = "csr-reg"; | 176 | reg-names = "csr-reg"; |
177 | clock-output-names = "eth8clk"; | 177 | clock-output-names = "eth8clk"; |
178 | }; | 178 | }; |
179 | |||
180 | sataphy1clk: sataphy1clk@1f21c000 { | ||
181 | compatible = "apm,xgene-device-clock"; | ||
182 | #clock-cells = <1>; | ||
183 | clocks = <&socplldiv2 0>; | ||
184 | reg = <0x0 0x1f21c000 0x0 0x1000>; | ||
185 | reg-names = "csr-reg"; | ||
186 | clock-output-names = "sataphy1clk"; | ||
187 | status = "disabled"; | ||
188 | csr-offset = <0x4>; | ||
189 | csr-mask = <0x00>; | ||
190 | enable-offset = <0x0>; | ||
191 | enable-mask = <0x06>; | ||
192 | }; | ||
193 | |||
194 | sataphy2clk: sataphy1clk@1f22c000 { | ||
195 | compatible = "apm,xgene-device-clock"; | ||
196 | #clock-cells = <1>; | ||
197 | clocks = <&socplldiv2 0>; | ||
198 | reg = <0x0 0x1f22c000 0x0 0x1000>; | ||
199 | reg-names = "csr-reg"; | ||
200 | clock-output-names = "sataphy2clk"; | ||
201 | status = "ok"; | ||
202 | csr-offset = <0x4>; | ||
203 | csr-mask = <0x3a>; | ||
204 | enable-offset = <0x0>; | ||
205 | enable-mask = <0x06>; | ||
206 | }; | ||
207 | |||
208 | sataphy3clk: sataphy1clk@1f23c000 { | ||
209 | compatible = "apm,xgene-device-clock"; | ||
210 | #clock-cells = <1>; | ||
211 | clocks = <&socplldiv2 0>; | ||
212 | reg = <0x0 0x1f23c000 0x0 0x1000>; | ||
213 | reg-names = "csr-reg"; | ||
214 | clock-output-names = "sataphy3clk"; | ||
215 | status = "ok"; | ||
216 | csr-offset = <0x4>; | ||
217 | csr-mask = <0x3a>; | ||
218 | enable-offset = <0x0>; | ||
219 | enable-mask = <0x06>; | ||
220 | }; | ||
179 | }; | 221 | }; |
180 | 222 | ||
181 | serial0: serial@1c020000 { | 223 | serial0: serial@1c020000 { |
@@ -187,5 +229,35 @@ | |||
187 | interrupt-parent = <&gic>; | 229 | interrupt-parent = <&gic>; |
188 | interrupts = <0x0 0x4c 0x4>; | 230 | interrupts = <0x0 0x4c 0x4>; |
189 | }; | 231 | }; |
232 | |||
233 | phy1: phy@1f21a000 { | ||
234 | compatible = "apm,xgene-phy"; | ||
235 | reg = <0x0 0x1f21a000 0x0 0x100>; | ||
236 | #phy-cells = <1>; | ||
237 | clocks = <&sataphy1clk 0>; | ||
238 | status = "disabled"; | ||
239 | apm,tx-boost-gain = <30 30 30 30 30 30>; | ||
240 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | ||
241 | }; | ||
242 | |||
243 | phy2: phy@1f22a000 { | ||
244 | compatible = "apm,xgene-phy"; | ||
245 | reg = <0x0 0x1f22a000 0x0 0x100>; | ||
246 | #phy-cells = <1>; | ||
247 | clocks = <&sataphy2clk 0>; | ||
248 | status = "ok"; | ||
249 | apm,tx-boost-gain = <30 30 30 30 30 30>; | ||
250 | apm,tx-eye-tuning = <1 10 10 2 10 10>; | ||
251 | }; | ||
252 | |||
253 | phy3: phy@1f23a000 { | ||
254 | compatible = "apm,xgene-phy"; | ||
255 | reg = <0x0 0x1f23a000 0x0 0x100>; | ||
256 | #phy-cells = <1>; | ||
257 | clocks = <&sataphy3clk 0>; | ||
258 | status = "ok"; | ||
259 | apm,tx-boost-gain = <31 31 31 31 31 31>; | ||
260 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | ||
261 | }; | ||
190 | }; | 262 | }; |
191 | }; | 263 | }; |