Merge branch 'next/devel-exynos5250-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc2

* 'next/devel-exynos5250-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: EXYNOS: Add AUXDATA for i2c controllers
  ARM: dts: Update device tree source files for EXYNOS5250
  ARM: EXYNOS: Add device tree support for interrupt combiner
  ARM: EXYNOS: Add irq_domain support for interrupt combiner
  ARM: EXYNOS: Remove a new bus_type instance for EXYNOS5
  ARM: EXYNOS: update irqs for EXYNOS5250 SoC
  ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
  ARM: EXYNOS: add GPC4 bank instance
  ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition
  ARM: EXYNOS: Modify the GIC physical address for static io-mapping
  ARM: EXYNOS: Add watchdog timer clock instance

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

14 files changed, 327 insertions, 124 deletions

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 399d17b231d2..49945cc1bc7d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -23,4 +23,52 @@
         chosen {
                 bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
         };
+
+        i2c@12C60000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                gpios = <&gpb3 0 2 3 0>,
+                        <&gpb3 1 2 3 0>;
+
+                eeprom@50 {
+                        compatible = "samsung,s524ad0xd1";
+                        reg = <0x50>;
+                };
+        };
+
+        i2c@12C70000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                gpios = <&gpb3 2 2 3 0>,
+                        <&gpb3 3 2 3 0>;
+
+                eeprom@51 {
+                        compatible = "samsung,s524ad0xd1";
+                        reg = <0x51>;
+                };
+        };
+
+        i2c@12C80000 {
+                status = "disabled";
+        };
+
+        i2c@12C90000 {
+                status = "disabled";
+        };
+
+        i2c@12CA0000 {
+                status = "disabled";
+        };
+
+        i2c@12CB0000 {
+                status = "disabled";
+        };
+
+        i2c@12CC0000 {
+                status = "disabled";
+        };
+
+        i2c@12CD0000 {
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dfc433599436..5ca0cdb76413 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -23,11 +23,11 @@
         compatible = "samsung,exynos5250";
         interrupt-parent = <&gic>;
 
-        gic:interrupt-controller@10490000 {
+        gic:interrupt-controller@10481000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
-                reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+                reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
         };
 
         watchdog {
@@ -42,30 +42,6 @@
                 interrupts = <0 43 0>, <0 44 0>;
         };
 
-        sdhci@12200000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12200000 0x100>;
-                interrupts = <0 75 0>;
-        };
-
-        sdhci@12210000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12210000 0x100>;
-                interrupts = <0 76 0>;
-        };
-
-        sdhci@12220000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12220000 0x100>;
-                interrupts = <0 77 0>;
-        };
-
-        sdhci@12230000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12230000 0x100>;
-                interrupts = <0 78 0>;
-        };
-
         serial@12C00000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C00000 0x100>;
@@ -94,48 +70,64 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12C60000 0x100>;
                 interrupts = <0 56 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12C70000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12C70000 0x100>;
                 interrupts = <0 57 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12C80000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12C80000 0x100>;
                 interrupts = <0 58 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12C90000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12C90000 0x100>;
                 interrupts = <0 59 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12CA0000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12CA0000 0x100>;
                 interrupts = <0 60 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12CB0000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12CB0000 0x100>;
                 interrupts = <0 61 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12CC0000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12CC0000 0x100>;
                 interrupts = <0 62 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12CD0000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12CD0000 0x100>;
                 interrupts = <0 63 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         amba {
@@ -157,13 +149,13 @@
                         interrupts = <0 35 0>;
                 };
 
-                mdma0: pdma@10800000 {
+                mdma0: mdma@10800000 {
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x10800000 0x1000>;
                         interrupts = <0 33 0>;
                 };
 
-                mdma1: pdma@11C10000 {
+                mdma1: mdma@11C10000 {
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x11C10000 0x1000>;
                         interrupts = <0 124 0>;
@@ -242,6 +234,12 @@
                         #gpio-cells = <4>;
                 };
 
+                gpc4: gpio-controller@114002E0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114002E0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
                 gpd0: gpio-controller@11400160 {
                         compatible = "samsung,exynos4-gpio";
                         reg = <0x11400160 0x20>;
@@ -388,19 +386,19 @@
 
                 gpv2: gpio-controller@10D10040 {
                         compatible = "samsung,exynos4-gpio";
-                        reg = <0x10D10040 0x20>;
+                        reg = <0x10D10060 0x20>;
                         #gpio-cells = <4>;
                 };
 
                 gpv3: gpio-controller@10D10060 {
                         compatible = "samsung,exynos4-gpio";
-                        reg = <0x10D10060 0x20>;
+                        reg = <0x10D10080 0x20>;
                         #gpio-cells = <4>;
                 };
 
                 gpv4: gpio-controller@10D10080 {
                         compatible = "samsung,exynos4-gpio";
-                        reg = <0x10D10080 0x20>;
+                        reg = <0x10D100C0 0x20>;
                         #gpio-cells = <4>;
                 };
 
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 9f87a07b0bf8..5aa460b01fdf 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -165,11 +165,29 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 };
 
+static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
+        .clk    = {
+                .name           = "mout_bpll_fout",
+        },
+        .sources = &clk_src_bpll_fout,
+        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_list[] = {
+        [0] = &clk_fin_bpll,
+        [1] = &exynos5_clk_mout_bpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll = {
+        .sources        = exynos5_clk_src_bpll_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
+};
+
 static struct clksrc_clk exynos5_clk_mout_bpll = {
         .clk    = {
                 .name           = "mout_bpll",
         },
-        .sources = &clk_src_bpll,
+        .sources = &exynos5_clk_src_bpll,
         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
 };
 
@@ -207,11 +225,29 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 };
 
+static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
+        .clk    = {
+                .name           = "mout_mpll_fout",
+        },
+        .sources = &clk_src_mpll_fout,
+        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_mpll_list[] = {
+        [0] = &clk_fin_mpll,
+        [1] = &exynos5_clk_mout_mpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll = {
+        .sources        = exynos5_clk_src_mpll_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
+};
+
 struct clksrc_clk exynos5_clk_mout_mpll = {
         .clk = {
                 .name           = "mout_mpll",
         },
-        .sources = &clk_src_mpll,
+        .sources = &exynos5_clk_src_mpll,
         .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 };
 
@@ -474,6 +510,11 @@ static struct clk exynos5_init_clocks_off[] = {
                 .enable         = exynos5_clk_ip_peris_ctrl,
                 .ctrlbit        = (1 << 20),
         }, {
+                .name           = "watchdog",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peris_ctrl,
+                .ctrlbit        = (1 << 19),
+        }, {
                 .name           = "hsmmc",
                 .devname        = "exynos4-sdhci.0",
                 .parent         = &exynos5_clk_aclk_200.clk,
@@ -1031,10 +1072,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
         &exynos5_clk_mout_apll,
         &exynos5_clk_sclk_apll,
         &exynos5_clk_mout_bpll,
+        &exynos5_clk_mout_bpll_fout,
         &exynos5_clk_mout_bpll_user,
         &exynos5_clk_mout_cpll,
         &exynos5_clk_mout_epll,
         &exynos5_clk_mout_mpll,
+        &exynos5_clk_mout_mpll_fout,
         &exynos5_clk_mout_mpll_user,
         &exynos5_clk_vpllsrc,
         &exynos5_clk_sclk_vpll,
@@ -1098,7 +1141,9 @@ static struct clk *exynos5_clks[] __initdata = {
         &exynos5_clk_sclk_hdmi27m,
         &exynos5_clk_sclk_hdmiphy,
         &clk_fout_bpll,
+        &clk_fout_bpll_div2,
         &clk_fout_cpll,
+        &clk_fout_mpll_div2,
         &exynos5_clk_armclk,
 };
 
@@ -1263,8 +1308,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
 
         clk_fout_apll.ops = &exynos5_fout_apll_ops;
         clk_fout_bpll.rate = bpll;
+        clk_fout_bpll_div2.rate = bpll >> 1;
         clk_fout_cpll.rate = cpll;
         clk_fout_mpll.rate = mpll;
+        clk_fout_mpll_div2.rate = mpll >> 1;
         clk_fout_epll.rate = epll;
         clk_fout_vpll.rate = vpll;
 
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 5ccd6e80a607..9900158f026a 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -19,6 +19,9 @@
 #include <linux/serial_core.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/export.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
 
 #include <asm/proc-fns.h>
 #include <asm/exception.h>
@@ -265,12 +268,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
         }, {
                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
-                .length         = SZ_64K,
+                .length         = SZ_8K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
-                .length         = SZ_64K,
+                .length         = SZ_4K,
                 .type           = MT_DEVICE,
         },
 };
@@ -399,6 +402,7 @@ struct combiner_chip_data {
         void __iomem *base;
 };
 
+static struct irq_domain *combiner_irq_domain;
 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 
 static inline void __iomem *combiner_base(struct irq_data *data)
@@ -411,14 +415,14 @@ static inline void __iomem *combiner_base(struct irq_data *data)
 
 static void combiner_mask_irq(struct irq_data *data)
 {
-        u32 mask = 1 << (data->irq % 32);
+        u32 mask = 1 << (data->hwirq % 32);
 
         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 }
 
 static void combiner_unmask_irq(struct irq_data *data)
 {
-        u32 mask = 1 << (data->irq % 32);
+        u32 mask = 1 << (data->hwirq % 32);
 
         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 }
@@ -474,49 +478,127 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 }
 
-static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
-                          unsigned int irq_start)
+static void __init combiner_init_one(unsigned int combiner_nr,
+                                     void __iomem *base)
 {
-        unsigned int i;
-        unsigned int max_nr;
-
-        if (soc_is_exynos5250())
-                max_nr = EXYNOS5_MAX_COMBINER_NR;
-        else
-                max_nr = EXYNOS4_MAX_COMBINER_NR;
-
-        if (combiner_nr >= max_nr)
-                BUG();
-
         combiner_data[combiner_nr].base = base;
-        combiner_data[combiner_nr].irq_offset = irq_start;
+        combiner_data[combiner_nr].irq_offset = irq_find_mapping(
+                combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 
         /* Disable all interrupts */
-
         __raw_writel(combiner_data[combiner_nr].irq_mask,
                      base + COMBINER_ENABLE_CLEAR);
+}
 
-        /* Setup the Linux IRQ subsystem */
+#ifdef CONFIG_OF
+static int combiner_irq_domain_xlate(struct irq_domain *d,
+                                     struct device_node *controller,
+                                     const u32 *intspec, unsigned int intsize,
+                                     unsigned long *out_hwirq,
+                                     unsigned int *out_type)
+{
+        if (d->of_node != controller)
+                return -EINVAL;
+
+        if (intsize < 2)
+                return -EINVAL;
 
-        for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
-                                + MAX_IRQ_IN_COMBINER; i++) {
-                irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
-                irq_set_chip_data(i, &combiner_data[combiner_nr]);
-                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+        *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
+        *out_type = 0;
+
+        return 0;
+}
+#else
+static int combiner_irq_domain_xlate(struct irq_domain *d,
+                                     struct device_node *controller,
+                                     const u32 *intspec, unsigned int intsize,
+                                     unsigned long *out_hwirq,
+                                     unsigned int *out_type)
+{
+        return -EINVAL;
+}
+#endif
+
+static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
+                                   irq_hw_number_t hw)
+{
+        irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
+        irq_set_chip_data(irq, &combiner_data[hw >> 3]);
+        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+        return 0;
+}
+
+static struct irq_domain_ops combiner_irq_domain_ops = {
+        .xlate  = combiner_irq_domain_xlate,
+        .map    = combiner_irq_domain_map,
+};
+
+void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
+{
+        int i, irq, irq_base;
+        unsigned int max_nr, nr_irq;
+
+        if (np) {
+                if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
+                        pr_warning("%s: number of combiners not specified, "
+                                "setting default as %d.\n",
+                                __func__, EXYNOS4_MAX_COMBINER_NR);
+                        max_nr = EXYNOS4_MAX_COMBINER_NR;
+                }
+        } else {
+                max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
+                                                EXYNOS4_MAX_COMBINER_NR;
+        }
+        nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
+
+        irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
+        if (IS_ERR_VALUE(irq_base)) {
+                irq_base = COMBINER_IRQ(0, 0);
+                pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
+        }
+
+        combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
+                                &combiner_irq_domain_ops, &combiner_data);
+        if (WARN_ON(!combiner_irq_domain)) {
+                pr_warning("%s: irq domain init failed\n", __func__);
+                return;
+        }
+
+        for (i = 0; i < max_nr; i++) {
+                combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
+                irq = np ? irq_of_parse_and_map(np, i) : IRQ_SPI(i);
+                combiner_cascade_irq(i, irq);
         }
 }
 
 #ifdef CONFIG_OF
+int __init combiner_of_init(struct device_node *np, struct device_node *parent)
+{
+        void __iomem *combiner_base;
+
+        combiner_base = of_iomap(np, 0);
+        if (!combiner_base) {
+                pr_err("%s: failed to map combiner registers\n", __func__);
+                return -ENXIO;
+        }
+
+        combiner_init(combiner_base, np);
+
+        return 0;
+}
+
 static const struct of_device_id exynos4_dt_irq_match[] = {
         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        { .compatible = "samsung,exynos4210-combiner",
+                        .data = combiner_of_init, },
         {},
 };
 #endif
 
 void __init exynos4_init_irq(void)
 {
-        int irq;
         unsigned int gic_bank_offset;
 
         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
@@ -528,12 +610,8 @@ void __init exynos4_init_irq(void)
                 of_irq_init(exynos4_dt_irq_match);
 #endif
 
-        for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
-
-                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
-                                COMBINER_IRQ(irq, 0));
-                combiner_cascade_irq(irq, IRQ_SPI(irq));
-        }
+        if (!of_have_populated_dt())
+                combiner_init(S5P_VA_COMBINER_BASE, NULL);
 
         /*
          * The parameters of s5p_init_irq() are for VIC init.
@@ -545,18 +623,9 @@ void __init exynos4_init_irq(void)
 
 void __init exynos5_init_irq(void)
 {
-        int irq;
-
 #ifdef CONFIG_OF
         of_irq_init(exynos4_dt_irq_match);
 #endif
-
-        for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
-                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
-                                COMBINER_IRQ(irq, 0));
-                combiner_cascade_irq(irq, IRQ_SPI(irq));
-        }
-
         /*
          * The parameters of s5p_init_irq() are for VIC init.
          * Theses parameters should be NULL and 0 because EXYNOS4
@@ -565,30 +634,18 @@ void __init exynos5_init_irq(void)
         s5p_init_irq(NULL, 0);
 }
 
-struct bus_type exynos4_subsys = {
-        .name           = "exynos4-core",
-        .dev_name       = "exynos4-core",
-};
-
-struct bus_type exynos5_subsys = {
-        .name           = "exynos5-core",
-        .dev_name       = "exynos5-core",
+struct bus_type exynos_subsys = {
+        .name           = "exynos-core",
+        .dev_name       = "exynos-core",
 };
 
 static struct device exynos4_dev = {
-        .bus    = &exynos4_subsys,
-};
-
-static struct device exynos5_dev = {
-        .bus    = &exynos5_subsys,
+        .bus    = &exynos_subsys,
 };
 
 static int __init exynos_core_init(void)
 {
-        if (soc_is_exynos5250())
-                return subsys_system_register(&exynos5_subsys, NULL);
-        else
-                return subsys_system_register(&exynos4_subsys, NULL);
+        return subsys_system_register(&exynos_subsys, NULL);
 }
 core_initcall(exynos_core_init);
 
@@ -675,10 +732,7 @@ static int __init exynos_init(void)
 {
         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 
-        if (soc_is_exynos5250())
-                return device_register(&exynos5_dev);
-        else
-                return device_register(&exynos4_dev);
+        return device_register(&exynos4_dev);
 }
 
 /* uart registration process */
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index d7498afe036a..eb24f1eb8e3b 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
 #define EXYNOS5_GPIO_B2_NR      (4)
 #define EXYNOS5_GPIO_B3_NR      (4)
 #define EXYNOS5_GPIO_C0_NR      (7)
-#define EXYNOS5_GPIO_C1_NR      (7)
+#define EXYNOS5_GPIO_C1_NR      (4)
 #define EXYNOS5_GPIO_C2_NR      (7)
 #define EXYNOS5_GPIO_C3_NR      (7)
-#define EXYNOS5_GPIO_D0_NR      (8)
+#define EXYNOS5_GPIO_C4_NR      (7)
+#define EXYNOS5_GPIO_D0_NR      (4)
 #define EXYNOS5_GPIO_D1_NR      (8)
 #define EXYNOS5_GPIO_Y0_NR      (6)
 #define EXYNOS5_GPIO_Y1_NR      (4)
@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
         EXYNOS5_GPIO_C1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
         EXYNOS5_GPIO_C2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
         EXYNOS5_GPIO_C3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
-        EXYNOS5_GPIO_D0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+        EXYNOS5_GPIO_C4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+        EXYNOS5_GPIO_D0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
         EXYNOS5_GPIO_D1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
         EXYNOS5_GPIO_Y0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
         EXYNOS5_GPIO_Y1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
 #define EXYNOS5_GPC1(_nr)       (EXYNOS5_GPIO_C1_START + (_nr))
 #define EXYNOS5_GPC2(_nr)       (EXYNOS5_GPIO_C2_START + (_nr))
 #define EXYNOS5_GPC3(_nr)       (EXYNOS5_GPIO_C3_START + (_nr))
+#define EXYNOS5_GPC4(_nr)       (EXYNOS5_GPIO_C4_START + (_nr))
 #define EXYNOS5_GPD0(_nr)       (EXYNOS5_GPIO_D0_START + (_nr))
 #define EXYNOS5_GPD1(_nr)       (EXYNOS5_GPIO_D1_START + (_nr))
 #define EXYNOS5_GPY0(_nr)       (EXYNOS5_GPIO_Y0_START + (_nr))
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 116167524051..561553a96f4b 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -286,6 +286,7 @@
 #define EXYNOS5_IRQ_MIPICSI1            IRQ_SPI(80)
 #define EXYNOS5_IRQ_EFNFCON_DMA_ABORT   IRQ_SPI(81)
 #define EXYNOS5_IRQ_MIPIDSI0            IRQ_SPI(82)
+#define EXYNOS5_IRQ_WDT_IOP             IRQ_SPI(83)
 #define EXYNOS5_IRQ_ROTATOR             IRQ_SPI(84)
 #define EXYNOS5_IRQ_GSC0                IRQ_SPI(85)
 #define EXYNOS5_IRQ_GSC1                IRQ_SPI(86)
@@ -294,8 +295,8 @@
 #define EXYNOS5_IRQ_JPEG                IRQ_SPI(89)
 #define EXYNOS5_IRQ_EFNFCON_DMA         IRQ_SPI(90)
 #define EXYNOS5_IRQ_2D                  IRQ_SPI(91)
-#define EXYNOS5_IRQ_SFMC0               IRQ_SPI(92)
-#define EXYNOS5_IRQ_SFMC1               IRQ_SPI(93)
+#define EXYNOS5_IRQ_EFNFCON_0           IRQ_SPI(92)
+#define EXYNOS5_IRQ_EFNFCON_1           IRQ_SPI(93)
 #define EXYNOS5_IRQ_MIXER               IRQ_SPI(94)
 #define EXYNOS5_IRQ_HDMI                IRQ_SPI(95)
 #define EXYNOS5_IRQ_MFC                 IRQ_SPI(96)
@@ -309,7 +310,7 @@
 #define EXYNOS5_IRQ_PCM2                IRQ_SPI(104)
 #define EXYNOS5_IRQ_SPDIF               IRQ_SPI(105)
 #define EXYNOS5_IRQ_ADC0                IRQ_SPI(106)
-
+#define EXYNOS5_IRQ_ADC1                IRQ_SPI(107)
 #define EXYNOS5_IRQ_SATA_PHY            IRQ_SPI(108)
 #define EXYNOS5_IRQ_SATA_PMEMREQ        IRQ_SPI(109)
 #define EXYNOS5_IRQ_CAM_C               IRQ_SPI(110)
@@ -318,8 +319,9 @@
 #define EXYNOS5_IRQ_DP1_INTP1           IRQ_SPI(113)
 #define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
 #define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
-#define EXYNOS5_IRQ_NFCON               IRQ_SPI(116)
 
+#define EXYNOS5_IRQ_MCT_L0              IRQ_SPI(120)
+#define EXYNOS5_IRQ_MCT_L1              IRQ_SPI(121)
 #define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
 #define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
 #define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
@@ -327,7 +329,6 @@
 #define EXYNOS5_IRQ_RP_TIMER            IRQ_SPI(127)
 
 #define EXYNOS5_IRQ_PMU                 COMBINER_IRQ(1, 2)
-#define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(1, 6)
 
 #define EXYNOS5_IRQ_SYSMMU_GSC0_0       COMBINER_IRQ(2, 0)
 #define EXYNOS5_IRQ_SYSMMU_GSC0_1       COMBINER_IRQ(2, 1)
@@ -338,6 +339,8 @@
 #define EXYNOS5_IRQ_SYSMMU_GSC3_0       COMBINER_IRQ(2, 6)
 #define EXYNOS5_IRQ_SYSMMU_GSC3_1       COMBINER_IRQ(2, 7)
 
+#define EXYNOS5_IRQ_SYSMMU_LITE2_0      COMBINER_IRQ(3, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE2_1      COMBINER_IRQ(3, 1)
 #define EXYNOS5_IRQ_SYSMMU_FIMD1_0      COMBINER_IRQ(3, 2)
 #define EXYNOS5_IRQ_SYSMMU_FIMD1_1      COMBINER_IRQ(3, 3)
 #define EXYNOS5_IRQ_SYSMMU_LITE0_0      COMBINER_IRQ(3, 4)
@@ -361,8 +364,8 @@
 
 #define EXYNOS5_IRQ_SYSMMU_ARM_0        COMBINER_IRQ(6, 0)
 #define EXYNOS5_IRQ_SYSMMU_ARM_1        COMBINER_IRQ(6, 1)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_0      COMBINER_IRQ(6, 2)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_1      COMBINER_IRQ(6, 3)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_0      COMBINER_IRQ(6, 2)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_1      COMBINER_IRQ(6, 3)
 #define EXYNOS5_IRQ_SYSMMU_RTIC_0       COMBINER_IRQ(6, 4)
 #define EXYNOS5_IRQ_SYSMMU_RTIC_1       COMBINER_IRQ(6, 5)
 #define EXYNOS5_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(6, 6)
@@ -374,11 +377,9 @@
 #define EXYNOS5_IRQ_SYSMMU_MDMA1_1      COMBINER_IRQ(7, 3)
 #define EXYNOS5_IRQ_SYSMMU_TV_0         COMBINER_IRQ(7, 4)
 #define EXYNOS5_IRQ_SYSMMU_TV_1         COMBINER_IRQ(7, 5)
-#define EXYNOS5_IRQ_SYSMMU_GPSX_0       COMBINER_IRQ(7, 6)
-#define EXYNOS5_IRQ_SYSMMU_GPSX_1       COMBINER_IRQ(7, 7)
 
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_0      COMBINER_IRQ(8, 5)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_1      COMBINER_IRQ(8, 6)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_0      COMBINER_IRQ(8, 5)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_1      COMBINER_IRQ(8, 6)
 
 #define EXYNOS5_IRQ_SYSMMU_DIS1_0       COMBINER_IRQ(9, 4)
 #define EXYNOS5_IRQ_SYSMMU_DIS1_1       COMBINER_IRQ(9, 5)
@@ -394,17 +395,24 @@
 #define EXYNOS5_IRQ_SYSMMU_DRC_0        COMBINER_IRQ(11, 6)
 #define EXYNOS5_IRQ_SYSMMU_DRC_1        COMBINER_IRQ(11, 7)
 
+#define EXYNOS5_IRQ_MDMA1_ABORT         COMBINER_IRQ(13, 1)
+
+#define EXYNOS5_IRQ_MDMA0_ABORT         COMBINER_IRQ(15, 3)
+
 #define EXYNOS5_IRQ_FIMD1_FIFO          COMBINER_IRQ(18, 4)
 #define EXYNOS5_IRQ_FIMD1_VSYNC         COMBINER_IRQ(18, 5)
 #define EXYNOS5_IRQ_FIMD1_SYSTEM        COMBINER_IRQ(18, 6)
 
+#define EXYNOS5_IRQ_ARMIOP_GIC          COMBINER_IRQ(19, 0)
+#define EXYNOS5_IRQ_ARMISP_GIC          COMBINER_IRQ(19, 1)
+#define EXYNOS5_IRQ_IOP_GIC             COMBINER_IRQ(19, 3)
+#define EXYNOS5_IRQ_ISP_GIC             COMBINER_IRQ(19, 4)
+
+#define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(22, 4)
+
 #define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_L0              COMBINER_IRQ(23, 1)
-#define EXYNOS5_IRQ_MCT_L1              COMBINER_IRQ(23, 2)
 #define EXYNOS5_IRQ_MCT_G0              COMBINER_IRQ(23, 3)
 #define EXYNOS5_IRQ_MCT_G1              COMBINER_IRQ(23, 4)
-#define EXYNOS5_IRQ_MCT_G2              COMBINER_IRQ(23, 5)
-#define EXYNOS5_IRQ_MCT_G3              COMBINER_IRQ(23, 6)
 
 #define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
 #define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
@@ -435,7 +443,7 @@
 
 #define EXYNOS5_MAX_COMBINER_NR         32
 
-#define EXYNOS5_IRQ_GPIO1_NR_GROUPS     13
+#define EXYNOS5_IRQ_GPIO1_NR_GROUPS     14
 #define EXYNOS5_IRQ_GPIO2_NR_GROUPS     9
 #define EXYNOS5_IRQ_GPIO3_NR_GROUPS     5
 #define EXYNOS5_IRQ_GPIO4_NR_GROUPS     1
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index d30643ba2739..c72f8088d93d 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -81,8 +81,8 @@
 
 #define EXYNOS4_PA_GIC_CPU              0x10480000
 #define EXYNOS4_PA_GIC_DIST             0x10490000
-#define EXYNOS5_PA_GIC_CPU              0x10480000
-#define EXYNOS5_PA_GIC_DIST             0x10490000
+#define EXYNOS5_PA_GIC_CPU              0x10482000
+#define EXYNOS5_PA_GIC_DIST             0x10481000
 
 #define EXYNOS4_PA_COREPERI             0x10500000
 #define EXYNOS4_PA_TWD                  0x10500600
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index dba83e91f0fd..b78b5f3ad9c0 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -322,6 +322,8 @@
 #define EXYNOS5_CLKSRC_CDREX                    EXYNOS_CLKREG(0x20200)
 #define EXYNOS5_CLKDIV_CDREX                    EXYNOS_CLKREG(0x20500)
 
+#define EXYNOS5_PLL_DIV2_SEL                    EXYNOS_CLKREG(0x20A24)
+
 #define EXYNOS5_EPLL_LOCK                       EXYNOS_CLKREG(0x10030)
 
 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT           (29)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 4711c8920e37..cf5d2228e998 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -43,6 +43,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                 "exynos4210-uart.2", NULL),
         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
                                 "exynos4210-uart.3", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
+                                "s3c2440-i2c.0", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
+                                "s3c2440-i2c.1", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 897d9a9cf226..b601fb8a408b 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 {
         struct mct_clock_event_device *mevt;
         unsigned int cpu = smp_processor_id();
+        int mct_lx_irq;
 
         mevt = this_cpu_ptr(&percpu_mct_tick);
         mevt->evt = evt;
@@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 
         if (mct_int_type == MCT_INT_SPI) {
                 if (cpu == 0) {
+                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
+                                                EXYNOS5_IRQ_MCT_L0;
                         mct_tick0_event_irq.dev_id = mevt;
-                        evt->irq = EXYNOS4_IRQ_MCT_L0;
-                        setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
+                        evt->irq = mct_lx_irq;
+                        setup_irq(mct_lx_irq, &mct_tick0_event_irq);
                 } else {
+                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
+                                                EXYNOS5_IRQ_MCT_L1;
                         mct_tick1_event_irq.dev_id = mevt;
-                        evt->irq = EXYNOS4_IRQ_MCT_L1;
-                        setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
-                        irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
+                        evt->irq = mct_lx_irq;
+                        setup_irq(mct_lx_irq, &mct_tick1_event_irq);
+                        irq_set_affinity(mct_lx_irq, cpumask_of(1));
                 }
         } else {
                 enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
@@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
 
 static void __init exynos4_timer_init(void)
 {
-        if (soc_is_exynos4210())
+        if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
                 mct_int_type = MCT_INT_SPI;
         else
                 mct_int_type = MCT_INT_PPI;
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index f0bb4677eb11..563dea9a6dbb 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -275,7 +275,7 @@ static void exynos4_restore_pll(void)
 
 static struct subsys_interface exynos4_pm_interface = {
         .name           = "exynos4_pm",
-        .subsys         = &exynos4_subsys,
+        .subsys         = &exynos_subsys,
         .add_dev        = exynos4_pm_add,
 };
 
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 787ceaca0be8..0721293fad63 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -202,7 +202,7 @@ extern struct bus_type s3c2443_subsys;
 extern struct bus_type s3c6410_subsys;
 extern struct bus_type s5p64x0_subsys;
 extern struct bus_type s5pv210_subsys;
-extern struct bus_type exynos4_subsys;
+extern struct bus_type exynos_subsys;
 
 extern void (*s5pc1xx_idle)(void);
 
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 1de4b32f98e9..8364b4bea8b8 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -32,8 +32,10 @@ extern struct clk clk_48m;
 extern struct clk s5p_clk_27m;
 extern struct clk clk_fout_apll;
 extern struct clk clk_fout_bpll;
+extern struct clk clk_fout_bpll_div2;
 extern struct clk clk_fout_cpll;
 extern struct clk clk_fout_mpll;
+extern struct clk clk_fout_mpll_div2;
 extern struct clk clk_fout_epll;
 extern struct clk clk_fout_dpll;
 extern struct clk clk_fout_vpll;
@@ -42,8 +44,10 @@ extern struct clk clk_vpll;
 
 extern struct clksrc_sources clk_src_apll;
 extern struct clksrc_sources clk_src_bpll;
+extern struct clksrc_sources clk_src_bpll_fout;
 extern struct clksrc_sources clk_src_cpll;
 extern struct clksrc_sources clk_src_mpll;
+extern struct clksrc_sources clk_src_mpll_fout;
 extern struct clksrc_sources clk_src_epll;
 extern struct clksrc_sources clk_src_dpll;
 
diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c
index 41d3dfd5dddb..031a61899bef 100644
--- a/arch/arm/plat-samsung/s5p-clock.c
+++ b/arch/arm/plat-samsung/s5p-clock.c
@@ -67,6 +67,11 @@ struct clk clk_fout_bpll = {
         .id             = -1,
 };
 
+struct clk clk_fout_bpll_div2 = {
+        .name           = "fout_bpll_div2",
+        .id             = -1,
+};
+
 /* CPLL clock output */
 
 struct clk clk_fout_cpll = {
@@ -82,6 +87,11 @@ struct clk clk_fout_mpll = {
         .id             = -1,
 };
 
+struct clk clk_fout_mpll_div2 = {
+        .name           = "fout_mpll_div2",
+        .id             = -1,
+};
+
 /* EPLL clock output */
 struct clk clk_fout_epll = {
         .name           = "fout_epll",
@@ -125,6 +135,16 @@ struct clksrc_sources clk_src_bpll = {
         .nr_sources     = ARRAY_SIZE(clk_src_bpll_list),
 };
 
+static struct clk *clk_src_bpll_fout_list[] = {
+        [0] = &clk_fout_bpll_div2,
+        [1] = &clk_fout_bpll,
+};
+
+struct clksrc_sources clk_src_bpll_fout = {
+        .sources        = clk_src_bpll_fout_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_bpll_fout_list),
+};
+
 /* Possible clock sources for CPLL Mux */
 static struct clk *clk_src_cpll_list[] = {
         [0] = &clk_fin_cpll,
@@ -147,6 +167,16 @@ struct clksrc_sources clk_src_mpll = {
         .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
 };
 
+static struct clk *clk_src_mpll_fout_list[] = {
+        [0] = &clk_fout_mpll_div2,
+        [1] = &clk_fout_mpll,
+};
+
+struct clksrc_sources clk_src_mpll_fout = {
+        .sources        = clk_src_mpll_fout_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mpll_fout_list),
+};
+
 /* Possible clock sources for EPLL Mux */
 static struct clk *clk_src_epll_list[] = {
         [0] = &clk_fin_epll,