ARM: shmobile: r8a7790 SCIF support

Add SCIF serial port support to the r8a7790 SoC by
adding platform devices for SCIFA0 -> SCIFA2 as well
as SCIFB0 -> SCIFB2 and SCIF0 -> SCIF1 together with
clock bindings. DT device description is excluded at
this point since such bindings are still under
development.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

2 files changed, 88 insertions, 1 deletions

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 6869798effa3..bad9bf2e34d6 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -27,19 +27,51 @@
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 
+#define SMSTPCR2 0xe6150138
+#define SMSTPCR7 0xe615014c
+
 static struct clk_mapping cpg_mapping = {
         .phys   = CPG_BASE,
         .len    = CPG_LEN,
 };
 
+static struct clk p_clk = {
+        .rate   = 65000000, /* shortcut for now */
+        .mapping        = &cpg_mapping,
+};
+
+static struct clk mp_clk = {
+        .rate   = 52000000,  /* shortcut for now */
+        .mapping        = &cpg_mapping,
+};
+
 static struct clk *main_clks[] = {
+        &p_clk,
+        &mp_clk,
 };
 
-enum { MSTP_NR };
+enum { MSTP721, MSTP720,
+        MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
+        [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+        [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
+        [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
+        [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
+        [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
+        [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
+        [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
 };
 
 static struct clk_lookup lookups[] = {
+        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
+        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
+        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
+        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
+        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
+        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
+        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
+        CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
 };
 
 void __init r8a7790_clock_init(void)
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index af432ba11020..3bb5bf16000c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -22,13 +22,68 @@
 #include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
+#include <linux/serial_sci.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7790.h>
 #include <asm/mach/arch.h>
 
+#define SCIF_COMMON(scif_type, baseaddr, irq)                   \
+        .type           = scif_type,                            \
+        .mapbase        = baseaddr,                             \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
+        .irqs           = SCIx_IRQ_MUXED(irq)
+
+#define SCIFA_DATA(index, baseaddr, irq)                \
+[index] = {                                             \
+        SCIF_COMMON(PORT_SCIFA, baseaddr, irq),         \
+        .scbrr_algo_id  = SCBRR_ALGO_4,                 \
+        .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0,      \
+}
+
+#define SCIFB_DATA(index, baseaddr, irq)        \
+[index] = {                                     \
+        SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
+        .scbrr_algo_id  = SCBRR_ALGO_4,         \
+        .scscr = SCSCR_RE | SCSCR_TE,           \
+}
+
+#define SCIF_DATA(index, baseaddr, irq)         \
+[index] = {                                             \
+        SCIF_COMMON(PORT_SCIF, baseaddr, irq),          \
+        .scbrr_algo_id  = SCBRR_ALGO_2,                 \
+        .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,      \
+}
+
+enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
+
+static const struct plat_sci_port scif[] = {
+        SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
+        SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
+        SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
+        SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
+        SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
+        SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
+        SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
+        SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
+};
+
+static inline void r8a7790_register_scif(int idx)
+{
+        platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
+                                      sizeof(struct plat_sci_port));
+}
+
 void __init r8a7790_add_standard_devices(void)
 {
+        r8a7790_register_scif(SCIFA0);
+        r8a7790_register_scif(SCIFA1);
+        r8a7790_register_scif(SCIFB0);
+        r8a7790_register_scif(SCIFB1);
+        r8a7790_register_scif(SCIFB2);
+        r8a7790_register_scif(SCIFA2);
+        r8a7790_register_scif(SCIF0);
+        r8a7790_register_scif(SCIF1);
 }
 
 #ifdef CONFIG_USE_OF