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authorPaul Walmsley <paul@pwsan.com>2010-01-26 22:13:06 -0500
committerPaul Walmsley <paul@pwsan.com>2010-01-28 20:13:49 -0500
commit49214640f52506fbba00eb998fc39f10653a840a (patch)
treeba907ff88094145942c9cf09db8013559ee44ee6 /arch
parent734f69a773d8ff65111562116c18c987049ddac4 (diff)
OMAP2xxx clock: move the APLL clock code into mach-omap2/clkt2xxx_apll.c
Move the APLL-related clock functions from clock2xxx.c to mach-omap2/clkt2xxx_apll.c. This is intended to make the clock code easier to understand, since all of the functions needed to manage APLLs are now located in their own file, rather than being mixed with other, unrelated functions. Clock debugging is also now more finely-grained, since the DEBUG macro can now be defined for APLL clocks alone. This should reduce unnecessary console noise when debugging. Also, if at some future point the mach-omap2/ directory is split into OMAP2/3/4 variants, this clkt file can be placed in the mach-omap2xxx/ directory, rather than shared with other chip types that don't use this clock type. Thanks to Alexander Shishkin <virtuoso@slind.org> for his comments to improve the patch description. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Alexander Shishkin <virtuoso@slind.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/Makefile3
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c120
-rw-r--r--arch/arm/mach-omap2/clock2xxx.c86
-rw-r--r--arch/arm/mach-omap2/clock2xxx.h1
4 files changed, 124 insertions, 86 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 2b58363a8947..825c303f671f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -12,7 +12,8 @@ clock-common = clock.o clock_common_data.o \
12 clockdomain.o clkt_dpll.o \ 12 clockdomain.o clkt_dpll.o \
13 clkt_clksel.o 13 clkt_clksel.o
14clock-omap2xxx = clkt2xxx_dpllcore.o \ 14clock-omap2xxx = clkt2xxx_dpllcore.o \
15 clkt2xxx_virt_prcm_set.o 15 clkt2xxx_virt_prcm_set.o \
16 clkt2xxx_apll.o
16 17
17obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) \ 18obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
18 $(clock-omap2xxx) 19 $(clock-omap2xxx)
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
new file mode 100644
index 000000000000..fc32ff8e790f
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -0,0 +1,120 @@
1/*
2 * OMAP2xxx APLL clock control functions
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18#undef DEBUG
19
20#include <linux/kernel.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23
24#include <plat/clock.h>
25#include <plat/prcm.h>
26
27#include "clock.h"
28#include "clock2xxx.h"
29#include "cm.h"
30#include "cm-regbits-24xx.h"
31
32/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
33#define EN_APLL_STOPPED 0
34#define EN_APLL_LOCKED 3
35
36/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
37#define APLLS_CLKIN_19_2MHZ 0
38#define APLLS_CLKIN_13MHZ 2
39#define APLLS_CLKIN_12MHZ 3
40
41/* Private functions */
42
43/* Enable an APLL if off */
44static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
45{
46 u32 cval, apll_mask;
47
48 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
49
50 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
51
52 if ((cval & apll_mask) == apll_mask)
53 return 0; /* apll already enabled */
54
55 cval &= ~apll_mask;
56 cval |= apll_mask;
57 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
58
59 omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,
60 clk->name);
61
62 /*
63 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
64 * fails?
65 */
66 return 0;
67}
68
69static int omap2_clk_apll96_enable(struct clk *clk)
70{
71 return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
72}
73
74static int omap2_clk_apll54_enable(struct clk *clk)
75{
76 return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
77}
78
79/* Stop APLL */
80static void omap2_clk_apll_disable(struct clk *clk)
81{
82 u32 cval;
83
84 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
85 cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
86 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
87}
88
89/* Public data */
90
91const struct clkops clkops_apll96 = {
92 .enable = omap2_clk_apll96_enable,
93 .disable = omap2_clk_apll_disable,
94};
95
96const struct clkops clkops_apll54 = {
97 .enable = omap2_clk_apll54_enable,
98 .disable = omap2_clk_apll_disable,
99};
100
101/* Public functions */
102
103u32 omap2xxx_get_apll_clkin(void)
104{
105 u32 aplls, srate = 0;
106
107 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
108 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
109 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
110
111 if (aplls == APLLS_CLKIN_19_2MHZ)
112 srate = 19200000;
113 else if (aplls == APLLS_CLKIN_13MHZ)
114 srate = 13000000;
115 else if (aplls == APLLS_CLKIN_12MHZ)
116 srate = 12000000;
117
118 return srate;
119}
120
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index 11d6edb0b32f..88077e746966 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -44,16 +44,6 @@
44#include "cm.h" 44#include "cm.h"
45#include "cm-regbits-24xx.h" 45#include "cm-regbits-24xx.h"
46 46
47
48/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
49#define EN_APLL_STOPPED 0
50#define EN_APLL_LOCKED 3
51
52/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
53#define APLLS_CLKIN_19_2MHZ 0
54#define APLLS_CLKIN_13MHZ 2
55#define APLLS_CLKIN_12MHZ 3
56
57struct clk *vclk, *sclk, *dclk; 47struct clk *vclk, *sclk, *dclk;
58 48
59void __iomem *prcm_clksrc_ctrl; 49void __iomem *prcm_clksrc_ctrl;
@@ -126,80 +116,6 @@ static void omap2_sys_clk_recalc(struct clk *clk)
126} 116}
127#endif /* OLD_CK */ 117#endif /* OLD_CK */
128 118
129/* Enable an APLL if off */
130static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
131{
132 u32 cval, apll_mask;
133
134 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
135
136 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
137
138 if ((cval & apll_mask) == apll_mask)
139 return 0; /* apll already enabled */
140
141 cval &= ~apll_mask;
142 cval |= apll_mask;
143 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
144
145 omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,
146 clk->name);
147
148 /*
149 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
150 * fails?
151 */
152 return 0;
153}
154
155static int omap2_clk_apll96_enable(struct clk *clk)
156{
157 return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
158}
159
160static int omap2_clk_apll54_enable(struct clk *clk)
161{
162 return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
163}
164
165/* Stop APLL */
166static void omap2_clk_apll_disable(struct clk *clk)
167{
168 u32 cval;
169
170 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
171 cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
172 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
173}
174
175const struct clkops clkops_apll96 = {
176 .enable = omap2_clk_apll96_enable,
177 .disable = omap2_clk_apll_disable,
178};
179
180const struct clkops clkops_apll54 = {
181 .enable = omap2_clk_apll54_enable,
182 .disable = omap2_clk_apll_disable,
183};
184
185static u32 omap2_get_apll_clkin(void)
186{
187 u32 aplls, srate = 0;
188
189 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
190 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
191 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
192
193 if (aplls == APLLS_CLKIN_19_2MHZ)
194 srate = 19200000;
195 else if (aplls == APLLS_CLKIN_13MHZ)
196 srate = 13000000;
197 else if (aplls == APLLS_CLKIN_12MHZ)
198 srate = 12000000;
199
200 return srate;
201}
202
203static u32 omap2_get_sysclkdiv(void) 119static u32 omap2_get_sysclkdiv(void)
204{ 120{
205 u32 div; 121 u32 div;
@@ -213,7 +129,7 @@ static u32 omap2_get_sysclkdiv(void)
213 129
214unsigned long omap2_osc_clk_recalc(struct clk *clk) 130unsigned long omap2_osc_clk_recalc(struct clk *clk)
215{ 131{
216 return omap2_get_apll_clkin() * omap2_get_sysclkdiv(); 132 return omap2xxx_get_apll_clkin() * omap2_get_sysclkdiv();
217} 133}
218 134
219unsigned long omap2_sys_clk_recalc(struct clk *clk) 135unsigned long omap2_sys_clk_recalc(struct clk *clk)
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index e35efde4bd80..3f1672e071c2 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -17,6 +17,7 @@ unsigned long omap2_sys_clk_recalc(struct clk *clk);
17unsigned long omap2_dpllcore_recalc(struct clk *clk); 17unsigned long omap2_dpllcore_recalc(struct clk *clk);
18int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); 18int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
19unsigned long omap2xxx_clk_get_core_rate(struct clk *clk); 19unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);
20u32 omap2xxx_get_apll_clkin(void);
20 21
21/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */ 22/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
22#ifdef CONFIG_ARCH_OMAP2420 23#ifdef CONFIG_ARCH_OMAP2420