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authorDavid Daney <david.daney@cavium.com>2014-05-28 17:52:10 -0400
committerRalf Baechle <ralf@linux-mips.org>2014-05-30 15:01:11 -0400
commit45b585c8dcdc469bb40b58cc2801acd7a2332525 (patch)
tree7aa6acb2c1085b8074cc30cee2c71d0c5335f94b /arch
parent18a8cd63c0d800bbc8b91f03054fcb13d308f6ec (diff)
MIPS: Add function get_ebase_cpunum
This returns the CPUNum from the low order Ebase bits. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7012/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/mipsregs.h9
-rw-r--r--arch/mips/kernel/cpu-probe.c2
2 files changed, 10 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index fb2d17487ec2..98e9754a4b6b 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1792,6 +1792,15 @@ __BUILD_SET_C0(brcm_cmt_ctrl)
1792__BUILD_SET_C0(brcm_config) 1792__BUILD_SET_C0(brcm_config)
1793__BUILD_SET_C0(brcm_mode) 1793__BUILD_SET_C0(brcm_mode)
1794 1794
1795/*
1796 * Return low 10 bits of ebase.
1797 * Note that under KVM (MIPSVZ) this returns vcpu id.
1798 */
1799static inline unsigned int get_ebase_cpunum(void)
1800{
1801 return read_c0_ebase() & 0x3ff;
1802}
1803
1795#endif /* !__ASSEMBLY__ */ 1804#endif /* !__ASSEMBLY__ */
1796 1805
1797#endif /* _ASM_MIPSREGS_H */ 1806#endif /* _ASM_MIPSREGS_H */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b1b580d69db0..d74f957c561e 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -423,7 +423,7 @@ static void decode_configs(struct cpuinfo_mips *c)
423 423
424#ifndef CONFIG_MIPS_CPS 424#ifndef CONFIG_MIPS_CPS
425 if (cpu_has_mips_r2) { 425 if (cpu_has_mips_r2) {
426 c->core = read_c0_ebase() & 0x3ff; 426 c->core = get_ebase_cpunum();
427 if (cpu_has_mipsmt) 427 if (cpu_has_mipsmt)
428 c->core >>= fls(core_nvpes()) - 1; 428 c->core >>= fls(core_nvpes()) - 1;
429 } 429 }