diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2012-04-24 18:33:32 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-05-15 18:03:42 -0400 |
commit | 3a08f7f85a885da15d47ad92464f829535aff7cb (patch) | |
tree | 4b280b771a2b925938c3a376c861966062404629 /arch | |
parent | 57b317f912b3f4b05c834818c73d7c8ea22642f7 (diff) |
ARM: EXYNOS: update irqs for EXYNOS5250 SoC
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-exynos/include/mach/irqs.h | 34 |
1 files changed, 21 insertions, 13 deletions
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index b1d3b68fcc9f..561553a96f4b 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h | |||
@@ -286,6 +286,7 @@ | |||
286 | #define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80) | 286 | #define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80) |
287 | #define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81) | 287 | #define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81) |
288 | #define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82) | 288 | #define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82) |
289 | #define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83) | ||
289 | #define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84) | 290 | #define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84) |
290 | #define EXYNOS5_IRQ_GSC0 IRQ_SPI(85) | 291 | #define EXYNOS5_IRQ_GSC0 IRQ_SPI(85) |
291 | #define EXYNOS5_IRQ_GSC1 IRQ_SPI(86) | 292 | #define EXYNOS5_IRQ_GSC1 IRQ_SPI(86) |
@@ -294,8 +295,8 @@ | |||
294 | #define EXYNOS5_IRQ_JPEG IRQ_SPI(89) | 295 | #define EXYNOS5_IRQ_JPEG IRQ_SPI(89) |
295 | #define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90) | 296 | #define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90) |
296 | #define EXYNOS5_IRQ_2D IRQ_SPI(91) | 297 | #define EXYNOS5_IRQ_2D IRQ_SPI(91) |
297 | #define EXYNOS5_IRQ_SFMC0 IRQ_SPI(92) | 298 | #define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92) |
298 | #define EXYNOS5_IRQ_SFMC1 IRQ_SPI(93) | 299 | #define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93) |
299 | #define EXYNOS5_IRQ_MIXER IRQ_SPI(94) | 300 | #define EXYNOS5_IRQ_MIXER IRQ_SPI(94) |
300 | #define EXYNOS5_IRQ_HDMI IRQ_SPI(95) | 301 | #define EXYNOS5_IRQ_HDMI IRQ_SPI(95) |
301 | #define EXYNOS5_IRQ_MFC IRQ_SPI(96) | 302 | #define EXYNOS5_IRQ_MFC IRQ_SPI(96) |
@@ -309,7 +310,7 @@ | |||
309 | #define EXYNOS5_IRQ_PCM2 IRQ_SPI(104) | 310 | #define EXYNOS5_IRQ_PCM2 IRQ_SPI(104) |
310 | #define EXYNOS5_IRQ_SPDIF IRQ_SPI(105) | 311 | #define EXYNOS5_IRQ_SPDIF IRQ_SPI(105) |
311 | #define EXYNOS5_IRQ_ADC0 IRQ_SPI(106) | 312 | #define EXYNOS5_IRQ_ADC0 IRQ_SPI(106) |
312 | 313 | #define EXYNOS5_IRQ_ADC1 IRQ_SPI(107) | |
313 | #define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108) | 314 | #define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108) |
314 | #define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109) | 315 | #define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109) |
315 | #define EXYNOS5_IRQ_CAM_C IRQ_SPI(110) | 316 | #define EXYNOS5_IRQ_CAM_C IRQ_SPI(110) |
@@ -318,7 +319,6 @@ | |||
318 | #define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113) | 319 | #define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113) |
319 | #define EXYNOS5_IRQ_CEC IRQ_SPI(114) | 320 | #define EXYNOS5_IRQ_CEC IRQ_SPI(114) |
320 | #define EXYNOS5_IRQ_SATA IRQ_SPI(115) | 321 | #define EXYNOS5_IRQ_SATA IRQ_SPI(115) |
321 | #define EXYNOS5_IRQ_NFCON IRQ_SPI(116) | ||
322 | 322 | ||
323 | #define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120) | 323 | #define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120) |
324 | #define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121) | 324 | #define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121) |
@@ -329,7 +329,6 @@ | |||
329 | #define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127) | 329 | #define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127) |
330 | 330 | ||
331 | #define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2) | 331 | #define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2) |
332 | #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(1, 6) | ||
333 | 332 | ||
334 | #define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0) | 333 | #define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0) |
335 | #define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1) | 334 | #define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1) |
@@ -340,6 +339,8 @@ | |||
340 | #define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6) | 339 | #define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6) |
341 | #define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7) | 340 | #define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7) |
342 | 341 | ||
342 | #define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0) | ||
343 | #define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1) | ||
343 | #define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2) | 344 | #define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2) |
344 | #define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3) | 345 | #define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3) |
345 | #define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4) | 346 | #define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4) |
@@ -363,8 +364,8 @@ | |||
363 | 364 | ||
364 | #define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0) | 365 | #define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0) |
365 | #define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1) | 366 | #define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1) |
366 | #define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(6, 2) | 367 | #define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2) |
367 | #define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(6, 3) | 368 | #define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3) |
368 | #define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4) | 369 | #define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4) |
369 | #define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5) | 370 | #define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5) |
370 | #define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6) | 371 | #define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6) |
@@ -376,11 +377,9 @@ | |||
376 | #define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3) | 377 | #define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3) |
377 | #define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4) | 378 | #define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4) |
378 | #define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5) | 379 | #define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5) |
379 | #define EXYNOS5_IRQ_SYSMMU_GPSX_0 COMBINER_IRQ(7, 6) | ||
380 | #define EXYNOS5_IRQ_SYSMMU_GPSX_1 COMBINER_IRQ(7, 7) | ||
381 | 380 | ||
382 | #define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(8, 5) | 381 | #define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5) |
383 | #define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(8, 6) | 382 | #define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6) |
384 | 383 | ||
385 | #define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4) | 384 | #define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4) |
386 | #define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5) | 385 | #define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5) |
@@ -396,15 +395,24 @@ | |||
396 | #define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6) | 395 | #define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6) |
397 | #define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7) | 396 | #define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7) |
398 | 397 | ||
398 | #define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1) | ||
399 | |||
400 | #define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3) | ||
401 | |||
399 | #define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4) | 402 | #define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4) |
400 | #define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5) | 403 | #define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5) |
401 | #define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6) | 404 | #define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6) |
402 | 405 | ||
406 | #define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0) | ||
407 | #define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1) | ||
408 | #define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3) | ||
409 | #define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4) | ||
410 | |||
411 | #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4) | ||
412 | |||
403 | #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) | 413 | #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) |
404 | #define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3) | 414 | #define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3) |
405 | #define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4) | 415 | #define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4) |
406 | #define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5) | ||
407 | #define EXYNOS5_IRQ_MCT_G3 COMBINER_IRQ(23, 6) | ||
408 | 416 | ||
409 | #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) | 417 | #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) |
410 | #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) | 418 | #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) |